-LiteX is a MiSoC-based SoC builder using Migen as Python DSL.
+LiteX is a FPGA design/SoC builder that can be used to build cores, create
+SoCs and full FPGA designs.
-Unless otherwise noted, LiteX is copyright (C) 2012-2019 Enjoy-Digital.
+LiteX is based on Migen/MiSoC and provides specific building/debugging tools
+for a higher level of abstraction and compatibily with the LiteX core ecosystem.
+
+Unless otherwise noted, LiteX is copyright (C) 2012-2020 Enjoy-Digital.
Unless otherwise noted, MiSoC is copyright (C) 2012-2015 Enjoy-Digital.
Unless otherwise noted, MiSoC is copyright (C) 2007-2015 M-Labs Ltd.
All rights reserved.

```
- Copyright 2012-2019 / EnjoyDigital
+ Copyright 2012-2020 / EnjoyDigital
```
[](https://travis-ci.com/enjoy-digital/litex)

LiteX is a FPGA design/SoC builder that can be used to build cores, create
SoCs and full FPGA designs.
-LiteX is based on Migen and provides specific building/debugging tools for
-a higher level of abstraction and compatibily with the LiteX core ecosystem.
+LiteX is based on Migen/MiSoC and provides specific building/debugging tools
+for a higher level of abstraction and compatibily with the LiteX core ecosystem.
Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
SoC builder to create/develop/debug FPGA SoCs in Python.
printf("\e[1m / /__/ / __/ -_)> <\e[0m\n");
printf("\e[1m /____/_/\\__/\\__/_/|_|\e[0m\n");
printf("\n");
- printf(" (c) Copyright 2012-2019 Enjoy-Digital\n");
+ printf(" (c) Copyright 2012-2020 Enjoy-Digital\n");
printf("\n");
printf(" BIOS built on "__DATE__" "__TIME__"\n");
crcbios();