litesata: update build core target generation

diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py
index 80452cdfcf977b8d57a4cc26e84e3ceca2802774..f4f17715d5366c2211e4ef47614b0b35189775e1 100755 (executable)
--- a/misoclib/mem/litesata/example_designs/make.py
+++ b/misoclib/mem/litesata/example_designs/make.py
@@ -69,8 +69,11 @@ if __name__ == "__main__":
        top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
        soc = top_class(platform, **top_kwargs)
        soc.finalize()
-       memory_regions = soc.get_memory_regions()
-       csr_regions = soc.get_csr_regions()
+       try:
+               memory_regions = soc.get_memory_regions()
+               csr_regions = soc.get_csr_regions()
+       except:
+               pass
 
        # decode actions
        action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@@ -139,8 +142,8 @@ BIST: {}
                        MultiReg:                                       XilinxMultiReg,
                        AsyncResetSynchronizer:         XilinxAsyncResetSynchronizer
                }
-               src = verilog.convert(soc, ios, special_overrides=so)
-               tools.write_to_file("build/litesata.v", src)
+               v_output = verilog.convert(soc, ios, special_overrides=so)
+               v_output.write("build/litesata.v")
 
        if actions["build-bitstream"]:
                vns = platform.build(soc, build_name=build_name, run=True)

diff --git a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
index 7302a0eb215b6d28583e29348d89b9139a9d964a..8880947b322862ea69a991017bf810d2bfbef56b 100644 (file)
--- a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
+++ b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
@@ -1,6 +1,5 @@
 from mibuild.generic_platform import *
-from mibuild.xilinx.common import CRG_DS
-from mibuild.xilinx.vivado import XilinxVivadoPlatform
+from mibuild.xilinx.platform import XilinxPlatform
 
 _io = [
        ("sys_clk", 0, Pins("X")),
@@ -16,9 +15,9 @@ _io = [
        ),
 ]
 
-class Platform(XilinxVivadoPlatform):
-       def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset"), **kwargs):
-               XilinxVivadoPlatform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
+class Platform(XilinxPlatform):
+       def __init__(self, device="xc7k325t", programmer=""):
+               XilinxPlatform.__init__(self, device, _io)
 
        def do_finalize(self, *args, **kwargs):
                pass