cores/spi: rename add_control paramter to add_csr

diff --git a/litex/soc/cores/spi.py b/litex/soc/cores/spi.py
index 6fb1e4680ebf89a4e77d62324f2c127a7184a842..5758397acb1a8b9f244fdf4ad1b0f38cd03c8ffd 100755 (executable)
--- a/litex/soc/cores/spi.py
+++ b/litex/soc/cores/spi.py
@@ -21,7 +21,7 @@ class SPIMaster(Module, AutoCSR):
     configurable data_width and frequency.
     """
     pads_layout = [("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)]
-    def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_control=True):
+    def __init__(self, pads, data_width, sys_clk_freq, spi_clk_freq, with_csr=True):
         if pads is None:
             pads = Record(self.pads_layout)
         if not hasattr(pads, "cs_n"):
@@ -38,8 +38,8 @@ class SPIMaster(Module, AutoCSR):
         self.cs       = Signal(len(pads.cs_n), reset=1)
         self.loopback = Signal()
 
-        if with_control:
-            self.add_control()
+        if with_csr:
+            self.add_csr()
 
         # # #
 
@@ -127,7 +127,7 @@ class SPIMaster(Module, AutoCSR):
                 )
             )
 
-    def add_control(self):
+    def add_csr(self):
         self._control  = CSRStorage(16)
         self._status   = CSRStatus()
         self._mosi     = CSRStorage(self.data_width)

diff --git a/test/test_spi.py b/test/test_spi.py
index 9914dbd2dd348a007e8817cf1859059656de9912..5d101a6c30079cb58cd7685e5947e8013330d248 100644 (file)
--- a/test/test_spi.py
+++ b/test/test_spi.py
@@ -26,5 +26,5 @@ class TestSPI(unittest.TestCase):
                 yield
             self.assertEqual((yield dut.miso), 0xdeadbeef)
 
-        dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_control=False)
+        dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_csr=False)
         run_simulation(dut, generator(dut))