litesata: pep8 (E225)

diff --git a/misoclib/mem/litesata/core/link/cont.py b/misoclib/mem/litesata/core/link/cont.py
index ddd3ed89a988f4a948b9437c98cd4a6659df4f22..6a62193fb0e054f8cf16e88c4f01a4cc95d7f366 100644 (file)
--- a/misoclib/mem/litesata/core/link/cont.py
+++ b/misoclib/mem/litesata/core/link/cont.py
@@ -47,7 +47,7 @@ class LiteSATACONTInserter(Module):
             Record.connect(sink, source),
             If(sink.stb,
                 If(~change,
-                    counter.ce.eq(sink.ack & (counter.value !=2)),
+                    counter.ce.eq(sink.ack & (counter.value != 2)),
                     # insert CONT
                     If(counter.value == 1,
                         source.charisk.eq(0b0001),

diff --git a/misoclib/mem/litesata/example_designs/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py
index 57edf15ae9abe234a62b59a4cb96f7b887b8e83f..40cf51770f85b8747519aa980d3705e1be0ad52e 100644 (file)
--- a/misoclib/mem/litesata/example_designs/test/bist.py
+++ b/misoclib/mem/litesata/example_designs/test/bist.py
@@ -30,7 +30,7 @@ class LiteSATABISTUnitDriver:
         self.frequency = regs.identifier_frequency.read()
         self.time = 0
         for s in ["start", "sector", "count", "loops", "random", "done", "aborted", "errors", "cycles"]:
-            setattr(self, s, getattr(regs, name + "_"+ s))
+            setattr(self, s, getattr(regs, name + "_" + s))
 
     def run(self, sector, count, loops, random, blocking=True, hw_timer=True):
         self.sector.write(sector)
@@ -73,7 +73,7 @@ class LiteSATABISTIdentifyDriver:
         self.regs = regs
         self.name = name
         for s in ["start", "done", "source_stb", "source_ack", "source_data"]:
-            setattr(self, s, getattr(regs, name + "_identify_"+ s))
+            setattr(self, s, getattr(regs, name + "_identify_" + s))
         self.data = []
 
     def read_fifo(self):
@@ -123,7 +123,7 @@ class LiteSATABISTIdentifyDriver:
         info = "Serial Number: " + self.serial_number + "\n"
         info += "Firmware Revision: " + self.firmware_revision + "\n"
         info += "Model Number: " + self.model_number + "\n"
-        info += "Capacity: %3.2f GB\n" %((self.total_sectors*logical_sector_size)/GB)
+        info += "Capacity: {:3.2f} GB\n".format((self.total_sectors*logical_sector_size)/GB)
         for k, v in self.capabilities.items():
             info += k + ": " + str(v) + "\n"
         print(info, end="")
@@ -189,9 +189,9 @@ if __name__ == "__main__":
                     if not read_done:
                         retry += 1
 
-                print("sector=%d(%dMB) wr_speed=%4.2fMB/s rd_speed=%4.2fMB/s errors=%d retry=%d" %(
+                print("sector={:d}({:d}MB) wr_speed={:4.2f}MB/s rd_speed={:4.2f}MB/s errors={:d} retry={:d}".format(
                     sector,
-                     run_sectors*logical_sector_size/MB,
+                    run_sectors*logical_sector_size/MB,
                     write_speed/MB,
                     read_speed/MB,
                     write_errors + read_errors,

diff --git a/misoclib/mem/litesata/example_designs/test/tools.py b/misoclib/mem/litesata/example_designs/test/tools.py
index 6afd3df5979327e78498fd1ba5fbd7a4d89ca281..546d2bea9bee643c0b78dc9bda4d9833b8274ee0 100644 (file)
--- a/misoclib/mem/litesata/example_designs/test/tools.py
+++ b/misoclib/mem/litesata/example_designs/test/tools.py
@@ -37,11 +37,11 @@ def link_trace(mila, tx_data_name, rx_data_name):
             rx_data = var.values
 
     for i in range(len(tx_data)):
-        tx = "%08x " %tx_data[i]
+        tx = "{:08x} ".format(tx_data[i])
         tx += decode_primitive(tx_data[i])
         tx += " "*(16-len(tx))
 
-        rx = "%08x " %rx_data[i]
+        rx = "{:08x} ".format(rx_data[i])
         rx += decode_primitive(rx_data[i])
         rx += " "*(16-len(rx))
 

diff --git a/misoclib/mem/litesata/test/command_tb.py b/misoclib/mem/litesata/test/command_tb.py
index bc474493b2d53c36e06baa088fd58e0e85fd4f5b..4dd67709a63b7953ee8c4160f6206b10cc9c091f 100644 (file)
--- a/misoclib/mem/litesata/test/command_tb.py
+++ b/misoclib/mem/litesata/test/command_tb.py
@@ -93,7 +93,7 @@ class TB(Module):
 
         # check results
         s, l, e = check(write_data, read_data)
-        print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
+        print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
 
 if __name__ == "__main__":
     run_simulation(TB(), ncycles=2048, vcd_name="my.vcd", keep_files=True)

diff --git a/misoclib/mem/litesata/test/common.py b/misoclib/mem/litesata/test/common.py
index 4f66961762b2f0fb1c272d6eec25cbaf9a034fea..6472b97dfdf5ebe061ff13787fddd130efaf9a8d 100644 (file)
--- a/misoclib/mem/litesata/test/common.py
+++ b/misoclib/mem/litesata/test/common.py
@@ -24,7 +24,7 @@ def check(p1, p2):
         else:
             ref, res = p2, p1
         shift = 0
-        while((ref[0] != res[0]) and (len(res)>1)):
+        while((ref[0] != res[0]) and (len(res) > 1)):
             res.pop(0)
             shift += 1
         length = min(len(ref), len(res))

diff --git a/misoclib/mem/litesata/test/cont_tb.py b/misoclib/mem/litesata/test/cont_tb.py
index 7010fe356780cbfd8fdad485ab075a152a6f2e7b..e0fd614d981194b4c09da54b5b9e69125fee3636 100644 (file)
--- a/misoclib/mem/litesata/test/cont_tb.py
+++ b/misoclib/mem/litesata/test/cont_tb.py
@@ -92,7 +92,7 @@ class TB(Module):
 
         # check results
         s, l, e = check(streamer_packet, self.logger.packet)
-        print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
+        print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
 
 
 if __name__ == "__main__":

diff --git a/misoclib/mem/litesata/test/crc_tb.py b/misoclib/mem/litesata/test/crc_tb.py
index 51fe7a9d2b1e56b577e3bb5379d4a00395e9bbe5..feccf565a2f4f5713e7ec6906fcc912b50e07088 100644 (file)
--- a/misoclib/mem/litesata/test/crc_tb.py
+++ b/misoclib/mem/litesata/test/crc_tb.py
@@ -15,7 +15,7 @@ class TB(Module):
     def get_c_crc(self, datas):
         stdin = ""
         for data in datas:
-            stdin += "0x%08x " %data
+            stdin += "0x{:08x} ".format(data)
         stdin += "exit"
         with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
@@ -52,7 +52,7 @@ class TB(Module):
 
         # check results
         s, l, e = check(c_crc, sim_crc)
-        print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
+        print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
 
 if __name__ == "__main__":
     from migen.sim.generic import run_simulation

diff --git a/misoclib/mem/litesata/test/hdd.py b/misoclib/mem/litesata/test/hdd.py
index 50663442766182331de66f6ca088724628885fd0..c1b9c3d4601f7a3f00119ef0af2738929f586f11 100644 (file)
--- a/misoclib/mem/litesata/test/hdd.py
+++ b/misoclib/mem/litesata/test/hdd.py
@@ -75,11 +75,11 @@ class PHYLayer(Module):
         yield from self.rx.receive()
 
     def __repr__(self):
-        receiving = "%08x " %self.rx.dword.dat
+        receiving = "{:08x} ".format(self.rx.dword.dat)
         receiving += decode_primitive(self.rx.dword.dat)
         receiving += " "*(16-len(receiving))
 
-        sending = "%08x " %self.tx.dword.dat
+        sending = "{:08x} ".format(self.tx.dword.dat)
         sending += decode_primitive(self.tx.dword.dat)
         sending += " "*(16-len(sending))
 
@@ -115,7 +115,7 @@ class LinkRXPacket(LinkPacket):
     def check_crc(self):
         stdin = ""
         for v in self[:-1]:
-            stdin += "0x%08x " %v
+            stdin += "0x{:08x} ".format(v)
         stdin += "exit"
         with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
@@ -134,7 +134,7 @@ class LinkTXPacket(LinkPacket):
     def insert_crc(self):
         stdin = ""
         for v in self:
-            stdin += "0x%08x " %v
+            stdin += "0x{:08x} ".foramt(v)
         stdin += "exit"
         with subprocess.Popen("./crc", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
@@ -313,7 +313,7 @@ class FIS:
         else:
             r = "<<<<<<<<\n"
         for k in sorted(self.description.keys()):
-            r += k + " : 0x%x" %getattr(self, k) + "\n"
+            r += k + " : 0x{:x}".format(getattr(self, k)) + "\n"
         return r
 
 
@@ -362,7 +362,7 @@ class FIS_DATA(FIS):
         r = "FIS_DATA\n"
         r += FIS.__repr__(self)
         for data in self.packet[1:]:
-            r += "%08x\n" %data
+            r += "{:08x}\n".format(data)
         return r
 
 
@@ -377,7 +377,7 @@ class FIS_UNKNOWN(FIS):
         else:
             r += "<<<<<<<<\n"
         for dword in self.packet:
-            r += "%08x\n" %dword
+            r += "{:08x}\n".format(dword)
         return r
 
 

diff --git a/misoclib/mem/litesata/test/link_tb.py b/misoclib/mem/litesata/test/link_tb.py
index 51142fb1a4c2bac6fd63b64ee00c1c63ea2d2f08..0790a0f457c589c788fa010ea9965ff4f75403ee 100644 (file)
--- a/misoclib/mem/litesata/test/link_tb.py
+++ b/misoclib/mem/litesata/test/link_tb.py
@@ -44,7 +44,7 @@ class TB(Module):
 
             # check results
             s, l, e = check(streamer_packet, self.logger.packet)
-            print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
+            print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
 
 
 if __name__ == "__main__":

diff --git a/misoclib/mem/litesata/test/phy_datapath_tb.py b/misoclib/mem/litesata/test/phy_datapath_tb.py
index 265570023aae1a87cbe91f423e77a149cdb5260d..9b96d033fb49b7bae2334aa730dac19d2c99519c 100644 (file)
--- a/misoclib/mem/litesata/test/phy_datapath_tb.py
+++ b/misoclib/mem/litesata/test/phy_datapath_tb.py
@@ -81,13 +81,13 @@ class TB(Module):
         yield from self.streamer.send(streamer_packet)
         yield from self.logger.receive(512)
         for d in self.logger.packet:
-            r = "%08x " %d
-            r +=decode_primitive(d)
+            r = "{:08x} ".format(d)
+            r += decode_primitive(d)
             print(r)
 
         # check results
         #s, l, e = check(streamer_packet, self.logger.packet)
-        #print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
+        #print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
 
 
 if __name__ == "__main__":

diff --git a/misoclib/mem/litesata/test/scrambler_tb.py b/misoclib/mem/litesata/test/scrambler_tb.py
index 806c3e25cd932a08450762c795c3ecd82f814abf..049ba353587729b187280d3111a87a259b5437a8 100644 (file)
--- a/misoclib/mem/litesata/test/scrambler_tb.py
+++ b/misoclib/mem/litesata/test/scrambler_tb.py
@@ -12,7 +12,7 @@ class TB(Module):
         self.length = length
 
     def get_c_values(self, length):
-        stdin = "0x%08x" %length
+        stdin = "0x{:08x}".format(length)
         with subprocess.Popen("./scrambler", stdin=subprocess.PIPE, stdout=subprocess.PIPE) as process:
             process.stdin.write(stdin.encode("ASCII"))
             out, err = process.communicate()
@@ -42,7 +42,7 @@ class TB(Module):
 
         # check results
         s, l, e = check(c_values, sim_values)
-        print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
+        print("shift " + str(s) + " / length " + str(l) + " / errors " + str(e))
 
 if __name__ == "__main__":
     from migen.sim.generic import run_simulation