Make branches work by repopulating the predecoder every time through. This is probabl...

--HG--
extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0

diff --git a/src/arch/alpha/predecoder.hh b/src/arch/alpha/predecoder.hh
index 0407ce99b4e02b66c3e086bf3db38f8a97fc635e..4887de8568bbc3501ee5aa47a286994f7025dfda 100644 (file)
--- a/src/arch/alpha/predecoder.hh
+++ b/src/arch/alpha/predecoder.hh
@@ -44,8 +44,6 @@ namespace AlphaISA
     {
       protected:
         ThreadContext * tc;
-        //The pc of the current instruction
-        Addr fetchPC;
         //The extended machine instruction being generated
         ExtMachInst ext_inst;
 
@@ -69,10 +67,8 @@ namespace AlphaISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr pc, Addr _fetchPC, Addr off, MachInst inst)
+        void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
         {
-            fetchPC = _fetchPC;
-            assert(off == 0);
             ext_inst = inst;
 #if FULL_SYSTEM
             if (pc && 0x1)

diff --git a/src/arch/mips/predecoder.hh b/src/arch/mips/predecoder.hh
index 90f768d7355f3e236c828ac694b901c29ffe82ad..e310dded4b62c58e1751f3699cce0e435bfd630b 100644 (file)
--- a/src/arch/mips/predecoder.hh
+++ b/src/arch/mips/predecoder.hh
@@ -66,9 +66,8 @@ namespace MipsISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
+        void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
         {
-            assert(off == 0);
             emi = inst;
         }
 

diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index 38d8fd1a2bb24a9c2e05dbef111c7de309315c17..d990c32560c32042a07fca23e523468cd657784c 100644 (file)
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -67,10 +67,8 @@ namespace SparcISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst inst)
+        void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
         {
-            assert(off == 0);
-
             emi = inst;
             //The I bit, bit 13, is used to figure out where the ASI
             //should come from. Use that in the ExtMachInst. This is

diff --git a/src/arch/x86/predecoder.hh b/src/arch/x86/predecoder.hh
index 3c858f061cbed9a811e20e497e9984b5a6209813..f34b663640209811c080ee82c0060e56abc77616 100644 (file)
--- a/src/arch/x86/predecoder.hh
+++ b/src/arch/x86/predecoder.hh
@@ -195,12 +195,12 @@ namespace X86ISA
 
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr pc, Addr fetchPC, Addr off, MachInst data)
+        void moreBytes(Addr pc, Addr fetchPC, MachInst data)
         {
+            DPRINTF(Predecoder, "Getting more bytes.\n");
             basePC = fetchPC;
-            offset = off;
+            offset = (fetchPC >= pc) ? 0 : pc - fetchPC;
             fetchChunk = data;
-            assert(off < sizeof(MachInst));
             outOfBytes = false;
             process();
         }

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index ab55ec7444e9ce5ea46f074e98981c472223ac3f..1ce5bd20f9a929a7c9fdf6b317718e7dcf772dae 100644 (file)
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                         (&cacheData[tid][offset]));
 
             predecoder.setTC(cpu->thread[tid]->getTC());
-            predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
+            predecoder.moreBytes(fetch_PC, fetch_PC, inst);
 
             ext_inst = predecoder.getExtMachInst();
 

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ea1c7d87f2736ca9048026cbfb91f48ab45dca54..03ff1282bef147faa6c16ed07baff814bc05d981 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -521,15 +521,15 @@ AtomicSimpleCPU::tick()
             dcache_access = false; // assume no dcache access
 
             //Fetch more instruction memory if necessary
-            if(predecoder.needMoreBytes())
-            {
+            //if(predecoder.needMoreBytes())
+            //{
                 icache_access = true;
                 ifetch_pkt->reinitFromRequest();
 
                 icache_latency = icachePort.sendAtomic(ifetch_pkt);
                 // ifetch_req is initialized to read the instruction directly
                 // into the CPU object's inst field.
-            }
+            //}
 
             preExecute();
 

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b7f60522fc6618e962bc282339fa83bfb1473535..9285aa7b5ff532c07ec7f8bd207adce945e68eb6 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -379,11 +379,11 @@ BaseSimpleCPU::preExecute()
         //This should go away once the constructor can be set up properly
         predecoder.setTC(thread->getTC());
         //If more fetch data is needed, pass it in.
-        if(predecoder.needMoreBytes())
-            predecoder.moreBytes(thread->readPC(),
-                    (thread->readPC() & PCMask) + fetchOffset, 0, inst);
-        else
-            predecoder.process();
+        Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
+        //if(predecoder.needMoreBytes())
+            predecoder.moreBytes(thread->readPC(), fetchPC, inst);
+        //else
+        //    predecoder.process();
 
         //If an instruction is ready, decode it. Otherwise, we'll have to
         //fetch beyond the MachInst at the current pc.