doc: remove IP

diff --git a/README b/README
index b849cefe29832f201c2f75fbc5ea665fd2bcc040..8faed188f5b62da435f5950b00be5ed4badcdcb7 100644 (file)
--- a/README
+++ b/README
@@ -18,7 +18,7 @@ PDF  : www.enjoy-digital.fr/litex/litesata.pdf
 LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
 
 LiteSATA is part of LiteX libraries whose aims are to lower entry level of complex
-FPGA IP cores by providing simple, elegant and efficient implementations of
+FPGA cores by providing simple, elegant and efficient implementations of
 components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
 The core uses simple and specific streaming buses and will provides in the future

diff --git a/doc/source/docs/intro/about.rst b/doc/source/docs/intro/about.rst
index e27d930c9b8be0c239e57c9494368fbf6add7308..838658680fc51123b5e3e84de7efb95f1b0db3d1 100644 (file)
--- a/doc/source/docs/intro/about.rst
+++ b/doc/source/docs/intro/about.rst
@@ -7,7 +7,7 @@ About LiteSATA
 LiteSATA provides a small footprint and configurable SATA gen1/2/3 core.
 
 LiteSATA is part of LiteX libraries whose aims is to lower entry level of complex
-FPGA IP cores by providing simple, elegant and efficient implementations of
+FPGA cores by providing simple, elegant and efficient implementations of
 components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
 The core uses simple and specific streaming buses and will provides in the future