env = conf.Finish()
# Define the universe of supported ISAs
-env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips']
+env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips', 'x86']
# Define the universe of supported CPU models
env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU',
--- /dev/null
+TARGET_ISA = 'x86'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
+FULL_SYSTEM = 0
self.etherdump = EtherDump(file=dumpfile)
self.etherlink.dump = Parent.etherdump
- self.clock = '1THz'
return self
if options.maxtick:
maxtick = options.maxtick
elif options.maxtime:
- simtime = int(options.maxtime * root.clock.value)
+ simtime = m5.ticks.seconds(simtime)
print "simulating for: ", simtime
maxtick = simtime
else:
drive_sys.cpu.connectMemPorts(drive_sys.membus)
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
- root = Root(clock = '1THz', system = test_sys)
+ root = Root(system=test_sys)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
#define __ARCH_ISA_SPECIFIC_HH__
//This file provides a mechanism for other source code to bring in
-//files from the ISA being compiled with
+//files from the ISA being compiled in.
-//These are constants so you can selective compile code based on the isa
-//To use them, do something like
+//These are constants so you can selectively compile code based on the isa.
+//To use them, do something like:
//
//#if THE_ISA == YOUR_FAVORITE_ISA
// conditional_code
//#endif
//
-//Note that this is how this file sets up the other isa "hooks"
+//Note that this is how this file sets up the TheISA macro.
//These macros have numerical values because otherwise the preprocessor
//would treat them as 0 in comparisons.
#define ALPHA_ISA 21064
#define SPARC_ISA 42
#define MIPS_ISA 34000
+#define X86_ISA 8086
//These tell the preprocessor where to find the files of a particular
//ISA, and set the "TheISA" macro for use elsewhere.
#define TheISA SparcISA
#elif THE_ISA == MIPS_ISA
#define TheISA MipsISA
+#elif THE_ISA == X86_ISA
+ #define TheISA X86ISA
#else
#error "THE_ISA not set"
#endif
#include <string>
+class Checkpoint;
+
namespace SparcISA
{
//These functions map register indices to names
* Authors: Nathan Binkert
*/
-#ifndef __ARCH_ALPHA_REMOTE_GDB_HH__
-#define __ARCH_ALPHA_REMOTE_GDB_HH__
+#ifndef __ARCH_SPARC_REMOTE_GDB_HH__
+#define __ARCH_SPARC_REMOTE_GDB_HH__
#include <map>
-#include "arch/types.hh"
+#include "arch/sparc/types.hh"
#include "base/remote_gdb.hh"
#include "cpu/pc_event.hh"
#include "base/pollevent.hh"
};
}
-#endif /* __ARCH_ALPHA_REMOTE_GDB_H__ */
+#endif /* __ARCH_SPARC_REMOTE_GDB_H__ */
--- /dev/null
+# -*- mode:python -*-
+
+# Copyright (c) 2005-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+# Copyright (c) 2007 The Hewlett-Packard Development Company
+# All rights reserved.
+#
+# Redistribution and use of this software in source and binary forms,
+# with or without modification, are permitted provided that the
+# following conditions are met:
+#
+# The software must be used only for Non-Commercial Use which means any
+# use which is NOT directed to receiving any direct monetary
+# compensation for, or commercial advantage from such use. Illustrative
+# examples of non-commercial use are academic research, personal study,
+# teaching, education and corporate research & development.
+# Illustrative examples of commercial use are distributing products for
+# commercial advantage and providing services using the software for
+# commercial advantage.
+#
+# If you wish to use this software or functionality therein that may be
+# covered by patents for commercial use, please contact:
+# Director of Intellectual Property Licensing
+# Office of Strategy and Technology
+# Hewlett-Packard Company
+# 1501 Page Mill Road
+# Palo Alto, California 94304
+#
+# Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer. Redistributions
+# in binary form must reproduce the above copyright notice, this list of
+# conditions and the following disclaimer in the documentation and/or
+# other materials provided with the distribution. Neither the name of
+# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission. No right of
+# sublicense is granted herewith. Derivatives of the software and
+# output created using the software may be prepared, but only for
+# Non-Commercial Uses. Derivatives of the software may be shared with
+# others provided: (i) the others agree to abide by the list of
+# conditions herein which includes the Non-Commercial Use restrictions;
+# and (ii) such Derivatives of the software include the above copyright
+# notice to acknowledge the contribution from this software where
+# applicable, this list of conditions and the disclaimer below.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+import os
+import sys
+from os.path import isdir
+
+# Import build environment variable from SConstruct.
+Import('env')
+
+###################################################
+#
+# Define needed sources.
+#
+###################################################
+
+# Base sources used by all configurations.
+base_sources = Split('''
+ floatregfile.cc
+ intregfile.cc
+ miscregfile.cc
+ regfile.cc
+ remote_gdb.cc
+ ''')
+
+# Full-system sources
+full_system_sources = Split('''
+ ''')
+
+# Syscall emulation (non-full-system) sources
+syscall_emulation_sources = Split('''
+ linux/linux.cc
+ linux/process.cc
+ linux/syscalls.cc
+ process.cc
+ ''')
+
+sources = base_sources
+
+if env['FULL_SYSTEM']:
+ sources += full_system_sources
+else:
+ sources += syscall_emulation_sources
+
+# Convert file names to SCons File objects. This takes care of the
+# path relative to the top of the directory tree.
+sources = [File(s) for s in sources]
+
+# Add in files generated by the ISA description.
+isa_desc_files = env.ISADesc('isa/main.isa')
+# Only non-header files need to be compiled.
+isa_desc_sources = [f for f in isa_desc_files if not f.path.endswith('.hh')]
+sources += isa_desc_sources
+
+Return('sources')
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_ARGUMENTS_HH__
+#define __ARCH_X86_ARGUMENTS_HH__
+
+#error X86 is not yet supported!
+
+namespace X86ISA
+{
+};
+
+#endif // __ARCH_X86_ARGUMENTS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_FAULTS_HH__
+#define __ARCH_X86_FAULTS_HH__
+
+#include "base/misc.hh"
+#include "sim/faults.hh"
+
+namespace X86ISA
+{
+ class X86Fault : public FaultBase
+ {
+ void invoke(ThreadContext * tc)
+ {
+ panic("X86 faults are not implemented!");
+ }
+ };
+
+ static inline Fault genPageTableFault(Addr va)
+ {
+ panic("Page table fault not implemented in x86!\n");
+ }
+
+ static inline Fault genMachineCheckFault()
+ {
+ panic("Machine check fault not implemented in x86!\n");
+ }
+
+ static inline Fault genAlignmentFault()
+ {
+ panic("Alignment fault not implemented (or for the most part existant) in x86!\n");
+ }
+};
+
+#endif // __ARCH_X86_FAULTS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2003-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/floatregfile.hh"
+#include "sim/serialize.hh"
+
+#include <string.h>
+
+using namespace X86ISA;
+using namespace std;
+
+class Checkpoint;
+
+string X86ISA::getFloatRegName(RegIndex index)
+{
+ static std::string floatRegName[NumFloatRegs] =
+ {"mmx0", "mmx1", "mmx2", "mmx3", "mmx4", "mmx5", "mmx6", "mmx7",
+ "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
+ "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"};
+ return floatRegName[index];
+}
+
+void FloatRegFile::clear()
+{
+ memset(q, 0, sizeof(FloatReg) * NumFloatRegs);
+}
+
+FloatReg FloatRegFile::readReg(int floatReg, int width)
+{
+ panic("Floating point not implemented for x86!\n");
+}
+
+FloatRegBits FloatRegFile::readRegBits(int floatReg, int width)
+{
+ panic("Floating point not implemented for x86!\n");
+}
+
+Fault FloatRegFile::setReg(int floatReg, const FloatReg &val, int width)
+{
+ panic("Floating point not implemented for x86!\n");
+}
+
+Fault FloatRegFile::setRegBits(int floatReg, const FloatRegBits &val, int width)
+{
+ panic("Floating point not implemented for x86!\n");
+}
+
+void FloatRegFile::serialize(std::ostream &os)
+{
+ SERIALIZE_ARRAY(q, NumFloatRegs);
+}
+
+void FloatRegFile::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ UNSERIALIZE_ARRAY(q, NumFloatRegs);
+}
+
--- /dev/null
+/*
+ * Copyright (c) 2003-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_FLOATREGFILE_HH__
+#define __ARCH_X86_FLOATREGFILE_HH__
+
+#include <string>
+
+#include "arch/x86/faults.hh"
+#include "arch/x86/types.hh"
+#include "arch/x86/x86_traits.hh"
+
+class Checkpoint;
+
+namespace X86ISA
+{
+ std::string getFloatRegName(RegIndex);
+
+ const int NumFloatArchRegs = NumMMXRegs + NumXMMRegs;
+ const int NumFloatRegs = NumFloatArchRegs;
+
+ class FloatRegFile
+ {
+ public:
+ static const int SingleWidth = 32;
+ static const int DoubleWidth = 64;
+ static const int QuadWidth = 128;
+
+ protected:
+ union
+ {
+ uint64_t q[NumFloatRegs];
+ double d[NumFloatRegs];
+ };
+
+ public:
+ void clear();
+
+ FloatReg readReg(int floatReg, int width);
+
+ FloatRegBits readRegBits(int floatReg, int width);
+
+ Fault setReg(int floatReg, const FloatReg &val, int width);
+
+ Fault setRegBits(int floatReg, const FloatRegBits &val, int width);
+
+ void serialize(std::ostream &os);
+
+ void unserialize(Checkpoint *cp, const std::string §ion);
+ };
+}
+
+#endif //__ARCH_X86_FLOATREGFILE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_INTERRUPTS_HH__
+#define __ARCH_X86_INTERRUPTS_HH__
+
+#error X86 is not yet supported!
+
+namespace X86ISA
+{
+};
+
+#endif // __ARCH_X86_INTERRUPTS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2003-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/intregfile.hh"
+#include "base/misc.hh"
+#include "sim/serialize.hh"
+
+#include <string.h>
+
+using namespace X86ISA;
+using namespace std;
+
+class Checkpoint;
+
+string X86ISA::getIntRegName(RegIndex index)
+{
+ //These might appear to be out of order, but they match
+ //the encoding for the registers. Who knows why the indexes
+ //are out of order
+ static std::string intRegName[NumIntArchRegs] =
+ {"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
+ return intRegName[index];
+}
+
+int IntRegFile::flattenIndex(int reg)
+{
+ return reg;
+}
+
+void IntRegFile::clear()
+{
+ memset(regs, 0, sizeof(IntReg) * NumIntRegs);
+}
+
+IntReg IntRegFile::readReg(int intReg)
+{
+ return regs[intReg];
+}
+
+void IntRegFile::setReg(int intReg, const IntReg &val)
+{
+ regs[intReg] = val;
+}
+
+void IntRegFile::serialize(std::ostream &os)
+{
+ SERIALIZE_ARRAY(regs, NumIntRegs);
+}
+
+void IntRegFile::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ UNSERIALIZE_ARRAY(regs, NumIntRegs);
+}
--- /dev/null
+/*
+ * Copyright (c) 2003-2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_INTREGFILE_HH__
+#define __ARCH_X86_INTREGFILE_HH__
+
+#include "arch/x86/x86_traits.hh"
+#include "arch/x86/types.hh"
+
+#include <string>
+
+class Checkpoint;
+
+namespace X86ISA
+{
+ class Regfile;
+
+ //This function translates integer register file indices into names
+ std::string getIntRegName(RegIndex);
+
+ const int NumIntArchRegs = 16;
+ const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
+
+ class IntRegFile
+ {
+ protected:
+ IntReg regs[NumIntRegs];
+
+ public:
+
+ int flattenIndex(int reg);
+
+ void clear();
+
+ IntReg readReg(int intReg);
+
+ void setReg(int intReg, const IntReg &val);
+
+ void serialize(std::ostream &os);
+
+ void unserialize(Checkpoint *cp, const std::string §ion);
+ };
+}
+
+#endif //__ARCH_X86_INTREGFILE__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_INTREGS_HH__
+#define __ARCH_X86_INTREGS_HH__
+
+namespace X86ISA
+{
+ enum IntRegIndex
+ {
+ INTREG_RAX,
+ INTREG_RCX,
+ INTREG_RDX,
+ INTREG_RBX,
+ INTREG_RSP,
+ INTREG_RBP,
+ INTREG_RSI,
+ INTREG_RDI,
+ INTREG_R8W,
+ INTREG_R9W,
+ INTREG_R10W,
+ INTREG_R11W,
+ INTREG_R12W,
+ INTREG_R13W,
+ INTREG_R14W,
+ INTREG_R15W
+ };
+};
+
+#endif // __ARCH_X86_INTERRUPTS_HH__
--- /dev/null
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+def bitfield EXAMPLE <24>;
+
--- /dev/null
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// The actual decoder specification
+//
+
+decode EXAMPLE default Unknown::unknown()
+{
+ 0x0: Unknown::unknown2();
+}
--- /dev/null
+// Copyright (c) 2007 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+// Declarations for execute() methods.
+def template BasicExecDeclare {{
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+// Definitions of execute methods that panic.
+def template BasicExecPanic {{
+ Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ {
+ panic("Execute method called when it shouldn't!");
+ M5_DUMMY_RETURN
+ }
+}};
+
+// Basic instruction class declaration template.
+def template BasicDeclare {{
+ /**
+ * Static instruction class for "%(mnemonic)s".
+ */
+ class %(class_name)s : public %(base_class)s
+ {
+ public:
+ // Constructor.
+ %(class_name)s(ExtMachInst machInst);
+ %(BasicExecDeclare)s
+ };
+}};
+
+// Basic instruction class constructor template.
+def template BasicConstructor {{
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
+ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ {
+ %(constructor)s;
+ }
+}};
+
+// Basic instruction class execute method template.
+def template BasicExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(fp_enable_check)s;
+ %(op_decl)s;
+ %(op_rd)s;
+ %(code)s;
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+
+// Basic decode template.
+def template BasicDecode {{
+ return new %(class_name)s(machInst);
+}};
+
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+ return new %(class_name)s("%(mnemonic)s", machInst);
+}};
--- /dev/null
+// Copyright (c) 2007 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+//Include the basic format
+//Templates from this format are used later
+##include "basic.isa"
+
+//Include the "unknown" format
+##include "unknown.isa"
--- /dev/null
+// Copyright (c) 2007 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instructions
+//
+
+output header {{
+ /**
+ * Class for Unknown/Illegal instructions
+ */
+ class Unknown : public StaticInst
+ {
+ public:
+
+ // Constructor
+ Unknown(ExtMachInst _machInst) :
+ StaticInst("unknown", _machInst, No_OpClass)
+ {
+ }
+
+ %(BasicExecDeclare)s
+
+ std::string generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const;
+
+ };
+}};
+
+output decoder {{
+ std::string Unknown::generateDisassembly(Addr pc,
+ const SymbolTable *symtab) const
+ {
+ return "Unknown instruction";
+ }
+}};
+
+output exec {{
+ Fault Unknown::execute(%(CPU_exec_context)s *xc,
+ Trace::InstRecord *traceData) const
+ {
+ panic("No instructions are implemented for X86!\n");
+ }
+}};
+
+def format Unknown() {{
+ decode_block = 'return new Unknown(machInst);\n'
+}};
--- /dev/null
+// Copyright (c) 2007 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
+
+output header {{
+#include <cstring>
+#include <sstream>
+#include <iostream>
+
+#include "arch/x86/faults.hh"
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/regfile.hh"
+#include "base/misc.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+#include "mem/request.hh" // some constructors use MemReq flags
+}};
+
+output decoder {{
+#include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/thread_context.hh" // for Jump::branchTarget()
+#include "mem/packet.hh"
+
+#if defined(linux) || defined(__APPLE__)
+#include <fenv.h>
+#endif
+#include <algorithm>
+
+using namespace X86ISA;
+}};
+
+output exec {{
+#if defined(linux) || defined(__APPLE__)
+#include <fenv.h>
+#endif
+
+#if defined(__sun) || defined (__OpenBSD__)
+#include <ieeefp.h>
+#endif
+
+#if FULL_SYSTEM
+#include "sim/pseudo_inst.hh"
+#endif
+
+#include <limits>
+
+#include <cmath>
+#include "base/bigint.hh"
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "sim/sim_exit.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+
+using namespace X86ISA;
+using namespace std;
+}};
+
--- /dev/null
+// -*- mode:c++ -*-
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+////////////////////////////////////////////////////////////////////
+//
+// X86 ISA description file.
+//
+////////////////////////////////////////////////////////////////////
+
+//Include the C++ include directives
+##include "includes.isa"
+
+////////////////////////////////////////////////////////////////////
+//
+// Namespace statement. Everything below this line will be in the
+// SparcISAInst namespace.
+//
+
+namespace X86ISA;
+
+//Include the bitfield definitions
+##include "bitfields.isa"
+
+//Include the operand_types and operand definitions
+##include "operands.isa"
+
+//Include the base class for x86 instructions, and some support code
+//##include "base.isa"
+
+//Include the definitions for the instruction formats
+##include "formats/formats.isa"
+
+//Include the decoder definition
+##include "decoder.isa"
--- /dev/null
+// Copyright (c) 2007 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+def operand_types {{
+ 'sb' : ('signed int', 8),
+ 'ub' : ('unsigned int', 8),
+ 'sw' : ('signed int', 16),
+ 'uw' : ('unsigned int', 16),
+ 'sdw' : ('signed int', 32),
+ 'udw' : ('unsigned int', 32),
+ 'sqw' : ('signed int', 64),
+ 'uqw' : ('unsigned int', 64),
+ 'sf' : ('float', 32),
+ 'df' : ('float', 64),
+ 'qf' : ('float', 128)
+}};
+
+def operands {{
+}};
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_ISATRAITS_HH__
+#define __ARCH_X86_ISATRAITS_HH__
+
+#include "arch/x86/intregs.hh"
+#include "arch/x86/types.hh"
+#include "arch/x86/x86_traits.hh"
+
+class StaticInstPtr;
+
+namespace LittleEndianGuest {}
+
+namespace X86ISA
+{
+ //This makes sure the little endian version of certain functions
+ //are used.
+ using namespace LittleEndianGuest;
+
+ // X86 does not have a delay slot
+#define ISA_HAS_DELAY_SLOT 0
+
+ // X86 NOP (XCHG rAX, rAX)
+ //XXX This needs to be set to an intermediate instruction struct
+ //which encodes this instruction
+
+ // These enumerate all the registers for dependence tracking.
+ enum DependenceTags {
+ //The number of microcode registers needs to be added to this
+ FP_Base_DepTag = 16,
+ Ctrl_Base_DepTag =
+ FP_Base_DepTag +
+ //mmx/x87 registers
+ 8 +
+ //xmm registers
+ 16
+ };
+
+ // semantically meaningful register indices
+ //There is no such register in X86
+ const int ZeroReg = 0;
+ const int StackPointerReg = INTREG_RSP;
+ //X86 doesn't seem to have a link register
+ const int ReturnAddressReg = 0;
+ const int ReturnValueReg = INTREG_RAX;
+ const int FramePointerReg = INTREG_RBP;
+ const int ArgumentReg0 = INTREG_RDI;
+ const int ArgumentReg1 = INTREG_RSI;
+ const int ArgumentReg2 = INTREG_RDX;
+ const int ArgumentReg3 = INTREG_RCX;
+ const int ArgumentReg4 = INTREG_R8W;
+ const int ArgumentReg5 = INTREG_R9W;
+
+ // Some OS syscalls use a second register (rdx) to return a second
+ // value
+ const int SyscallPseudoReturnReg = INTREG_RDX;
+
+ //XXX These numbers are bogus
+ const int MaxInstSrcRegs = 10;
+ const int MaxInstDestRegs = 10;
+
+ //4k. This value is not constant on x86.
+ const int LogVMPageSize = 12;
+ const int VMPageSize = (1 << LogVMPageSize);
+
+ const int PageShift = 13;
+ const int PageBytes = 1ULL << PageShift;
+
+ const int BranchPredAddrShiftAmt = 0;
+
+ StaticInstPtr decodeInst(ExtMachInst);
+};
+
+#endif // __ARCH_X86_ISATRAITS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_KERNELSTATS_HH__
+#define __ARCH_X86_KERNELSTATS_HH__
+
+#error X86 is not yet supported!
+
+namespace X86ISA
+{
+};
+
+#endif // __ARCH_X86_KERNELSTATS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/linux/linux.hh"
+#include <fcntl.h>
+
+// open(2) flags translation table
+OpenFlagTransTable X86Linux::openFlagTable[] = {
+#ifdef _MSC_VER
+ { TGT_O_RDONLY, _O_RDONLY },
+ { TGT_O_WRONLY, _O_WRONLY },
+ { TGT_O_RDWR, _O_RDWR },
+ { TGT_O_APPEND, _O_APPEND },
+ { TGT_O_CREAT, _O_CREAT },
+ { TGT_O_TRUNC, _O_TRUNC },
+ { TGT_O_EXCL, _O_EXCL },
+#ifdef _O_NONBLOCK
+ { TGT_O_NONBLOCK, _O_NONBLOCK },
+#endif
+#ifdef _O_NOCTTY
+ { TGT_O_NOCTTY, _O_NOCTTY },
+#endif
+#ifdef _O_SYNC
+ { TGT_O_SYNC, _O_SYNC },
+#endif
+#else /* !_MSC_VER */
+ { TGT_O_RDONLY, O_RDONLY },
+ { TGT_O_WRONLY, O_WRONLY },
+ { TGT_O_RDWR, O_RDWR },
+ { TGT_O_APPEND, O_APPEND },
+ { TGT_O_CREAT, O_CREAT },
+ { TGT_O_TRUNC, O_TRUNC },
+ { TGT_O_EXCL, O_EXCL },
+ { TGT_O_NONBLOCK, O_NONBLOCK },
+ { TGT_O_NOCTTY, O_NOCTTY },
+#ifdef O_SYNC
+ { TGT_O_SYNC, O_SYNC },
+#endif
+#endif /* _MSC_VER */
+};
+
+const int X86Linux::NUM_OPEN_FLAGS =
+ (sizeof(X86Linux::openFlagTable)/sizeof(X86Linux::openFlagTable[0]));
+
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_LINUX_LINUX_HH__
+#define __ARCH_X86_LINUX_LINUX_HH__
+
+#include "kern/linux/linux.hh"
+
+class X86Linux : public Linux
+{
+ public:
+
+ typedef struct {
+ uint32_t st_dev;
+ char __pad1[4];
+ uint64_t st_ino;
+ uint32_t st_mode;
+ uint16_t st_nlink;
+ uint32_t st_uid;
+ uint32_t st_gid;
+ uint32_t st_rdev;
+ char __pad2[4];
+ int64_t st_size;
+ int64_t st_atimeX;
+ int64_t st_mtimeX;
+ int64_t st_ctimeX;
+ int64_t st_blksize;
+ int64_t st_blocks;
+ uint64_t __unused4[2];
+ } tgt_stat;
+
+ static OpenFlagTransTable openFlagTable[];
+
+ static const int TGT_O_RDONLY = 0x00000000; //!< O_RDONLY
+ static const int TGT_O_WRONLY = 0x00000001; //!< O_WRONLY
+ static const int TGT_O_RDWR = 0x00000002; //!< O_RDWR
+ static const int TGT_O_NONBLOCK = 0x00004000; //!< O_NONBLOCK
+ static const int TGT_O_APPEND = 0x00000008; //!< O_APPEND
+ static const int TGT_O_CREAT = 0x00000200; //!< O_CREAT
+ static const int TGT_O_TRUNC = 0x00000400; //!< O_TRUNC
+ static const int TGT_O_EXCL = 0x00000800; //!< O_EXCL
+ static const int TGT_O_NOCTTY = 0x00008000; //!< O_NOCTTY
+ static const int TGT_O_SYNC = 0x00002000; //!< O_SYNC
+// static const int TGT_O_DRD = 0x00010000; //!< O_DRD
+// static const int TGT_O_DIRECTIO = 0x00020000; //!< O_DIRECTIO
+// static const int TGT_O_CACHE = 0x00002000; //!< O_CACHE
+// static const int TGT_O_DSYNC = 0x00008000; //!< O_DSYNC
+// static const int TGT_O_RSYNC = 0x00040000; //!< O_RSYNC
+
+ static const int NUM_OPEN_FLAGS;
+
+ static const unsigned TGT_MAP_ANONYMOUS = 0x20;
+};
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/linux/process.hh"
+#include "arch/x86/regfile.hh"
+
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "kern/linux/linux.hh"
+
+#include "sim/process.hh"
+#include "sim/syscall_emul.hh"
+
+using namespace std;
+using namespace X86ISA;
+
+SyscallDesc*
+X86LinuxProcess::getDesc(int callnum)
+{
+ if (callnum < 0 || callnum > Num_Syscall_Descs)
+ return NULL;
+ return &syscallDescs[callnum];
+}
+
+X86LinuxProcess::X86LinuxProcess(const std::string &name,
+ ObjectFile *objFile,
+ System * system,
+ int stdin_fd,
+ int stdout_fd,
+ int stderr_fd,
+ std::vector<std::string> &argv,
+ std::vector<std::string> &envp,
+ const std::string &cwd,
+ uint64_t _uid, uint64_t _euid,
+ uint64_t _gid, uint64_t _egid,
+ uint64_t _pid, uint64_t _ppid)
+ : X86LiveProcess(name, objFile, system,
+ stdin_fd, stdout_fd, stderr_fd, argv, envp, cwd,
+ _uid, _euid, _gid, _egid, _pid, _ppid),
+ Num_Syscall_Descs(273)
+{}
+
+void X86LinuxProcess::handleTrap(int trapNum, ThreadContext *tc)
+{
+ switch(trapNum)
+ {
+ //This implementation is from SPARC
+ case 0x10: //Linux 32 bit syscall trap
+ tc->syscall(tc->readIntReg(1));
+ break;
+ default:
+ X86LiveProcess::handleTrap(trapNum, tc);
+ }
+}
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __X86_LINUX_PROCESS_HH__
+#define __X86_LINUX_PROCESS_HH__
+
+#include "sim/process.hh"
+#include "arch/x86/linux/linux.hh"
+#include "arch/x86/syscallreturn.hh"
+#include "arch/x86/process.hh"
+
+namespace X86ISA {
+
+/// A process with emulated x86/Linux syscalls.
+class X86LinuxProcess : public X86LiveProcess
+{
+ public:
+ /// Constructor.
+ X86LinuxProcess(const std::string &name,
+ ObjectFile *objFile,
+ System * system,
+ int stdin_fd, int stdout_fd, int stderr_fd,
+ std::vector<std::string> &argv,
+ std::vector<std::string> &envp,
+ const std::string &cwd,
+ uint64_t _uid, uint64_t _euid,
+ uint64_t _gid, uint64_t _egid,
+ uint64_t _pid, uint64_t _ppid);
+
+ /// Array of syscall descriptors, indexed by call number.
+ static SyscallDesc syscallDescs[];
+
+ SyscallDesc* getDesc(int callnum);
+
+ const int Num_Syscall_Descs;
+
+ void handleTrap(int trapNum, ThreadContext *tc);
+};
+
+} // namespace X86ISA
+#endif // __X86_LINUX_PROCESS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/linux/process.hh"
+#include "kern/linux/linux.hh"
+#include "sim/syscall_emul.hh"
+
+using namespace X86ISA;
+
+/// Target uname() handler.
+static SyscallReturn
+unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
+ ThreadContext *tc)
+{
+ TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
+
+ strcpy(name->sysname, "Linux");
+ strcpy(name->nodename, "m5.eecs.umich.edu");
+ strcpy(name->release, "2.6.12");
+ strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
+ strcpy(name->machine, "x86_64");
+
+ name.copyOut(tc->getMemPort());
+
+ return 0;
+}
+
+SyscallDesc X86LinuxProcess::syscallDescs[] = {
+ /* 0 */ SyscallDesc("read", unimplementedFunc),
+ /* 1 */ SyscallDesc("write", unimplementedFunc),
+ /* 2 */ SyscallDesc("open", unimplementedFunc),
+ /* 3 */ SyscallDesc("close", unimplementedFunc),
+ /* 4 */ SyscallDesc("stat", unimplementedFunc),
+ /* 5 */ SyscallDesc("fstat", unimplementedFunc),
+ /* 6 */ SyscallDesc("lstat", unimplementedFunc),
+ /* 7 */ SyscallDesc("poll", unimplementedFunc),
+ /* 8 */ SyscallDesc("lseek", unimplementedFunc),
+ /* 9 */ SyscallDesc("mmap", unimplementedFunc),
+ /* 10 */ SyscallDesc("mprotect", unimplementedFunc),
+ /* 11 */ SyscallDesc("munmap", unimplementedFunc),
+ /* 12 */ SyscallDesc("brk", unimplementedFunc),
+ /* 13 */ SyscallDesc("rt_sigaction", unimplementedFunc),
+ /* 14 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
+ /* 15 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
+ /* 16 */ SyscallDesc("ioctl", unimplementedFunc),
+ /* 17 */ SyscallDesc("pread64", unimplementedFunc),
+ /* 18 */ SyscallDesc("pwrite64", unimplementedFunc),
+ /* 19 */ SyscallDesc("readv", unimplementedFunc),
+ /* 20 */ SyscallDesc("writev", unimplementedFunc),
+ /* 21 */ SyscallDesc("access", unimplementedFunc),
+ /* 22 */ SyscallDesc("pipe", unimplementedFunc),
+ /* 23 */ SyscallDesc("select", unimplementedFunc),
+ /* 24 */ SyscallDesc("sched_yield", unimplementedFunc),
+ /* 25 */ SyscallDesc("mremap", unimplementedFunc),
+ /* 26 */ SyscallDesc("msync", unimplementedFunc),
+ /* 27 */ SyscallDesc("mincore", unimplementedFunc),
+ /* 28 */ SyscallDesc("madvise", unimplementedFunc),
+ /* 29 */ SyscallDesc("shmget", unimplementedFunc),
+ /* 30 */ SyscallDesc("shmat", unimplementedFunc),
+ /* 31 */ SyscallDesc("shmctl", unimplementedFunc),
+ /* 32 */ SyscallDesc("dup", unimplementedFunc),
+ /* 33 */ SyscallDesc("dup2", unimplementedFunc),
+ /* 34 */ SyscallDesc("pause", unimplementedFunc),
+ /* 35 */ SyscallDesc("nanosleep", unimplementedFunc),
+ /* 36 */ SyscallDesc("getitimer", unimplementedFunc),
+ /* 37 */ SyscallDesc("alarm", unimplementedFunc),
+ /* 38 */ SyscallDesc("setitimer", unimplementedFunc),
+ /* 39 */ SyscallDesc("getpid", unimplementedFunc),
+ /* 40 */ SyscallDesc("sendfile", unimplementedFunc),
+ /* 41 */ SyscallDesc("socket", unimplementedFunc),
+ /* 42 */ SyscallDesc("connect", unimplementedFunc),
+ /* 43 */ SyscallDesc("accept", unimplementedFunc),
+ /* 44 */ SyscallDesc("sendto", unimplementedFunc),
+ /* 45 */ SyscallDesc("recvfrom", unimplementedFunc),
+ /* 46 */ SyscallDesc("sendmsg", unimplementedFunc),
+ /* 47 */ SyscallDesc("recvmsg", unimplementedFunc),
+ /* 48 */ SyscallDesc("shutdown", unimplementedFunc),
+ /* 49 */ SyscallDesc("bind", unimplementedFunc),
+ /* 50 */ SyscallDesc("listen", unimplementedFunc),
+ /* 51 */ SyscallDesc("getsockname", unimplementedFunc),
+ /* 52 */ SyscallDesc("getpeername", unimplementedFunc),
+ /* 53 */ SyscallDesc("socketpair", unimplementedFunc),
+ /* 54 */ SyscallDesc("setsockopt", unimplementedFunc),
+ /* 55 */ SyscallDesc("getsockopt", unimplementedFunc),
+ /* 56 */ SyscallDesc("clone", unimplementedFunc),
+ /* 57 */ SyscallDesc("fork", unimplementedFunc),
+ /* 58 */ SyscallDesc("vfork", unimplementedFunc),
+ /* 59 */ SyscallDesc("execve", unimplementedFunc),
+ /* 60 */ SyscallDesc("exit", unimplementedFunc),
+ /* 61 */ SyscallDesc("wait4", unimplementedFunc),
+ /* 62 */ SyscallDesc("kill", unimplementedFunc),
+ /* 63 */ SyscallDesc("uname", unameFunc),
+ /* 64 */ SyscallDesc("semget", unimplementedFunc),
+ /* 65 */ SyscallDesc("semop", unimplementedFunc),
+ /* 66 */ SyscallDesc("semctl", unimplementedFunc),
+ /* 67 */ SyscallDesc("shmdt", unimplementedFunc),
+ /* 68 */ SyscallDesc("msgget", unimplementedFunc),
+ /* 69 */ SyscallDesc("msgsnd", unimplementedFunc),
+ /* 70 */ SyscallDesc("msgrcv", unimplementedFunc),
+ /* 71 */ SyscallDesc("msgctl", unimplementedFunc),
+ /* 72 */ SyscallDesc("fcntl", unimplementedFunc),
+ /* 73 */ SyscallDesc("flock", unimplementedFunc),
+ /* 74 */ SyscallDesc("fsync", unimplementedFunc),
+ /* 75 */ SyscallDesc("fdatasync", unimplementedFunc),
+ /* 76 */ SyscallDesc("truncate", unimplementedFunc),
+ /* 77 */ SyscallDesc("ftruncate", unimplementedFunc),
+ /* 78 */ SyscallDesc("getdents", unimplementedFunc),
+ /* 79 */ SyscallDesc("getcwd", unimplementedFunc),
+ /* 80 */ SyscallDesc("chdir", unimplementedFunc),
+ /* 81 */ SyscallDesc("fchdir", unimplementedFunc),
+ /* 82 */ SyscallDesc("rename", unimplementedFunc),
+ /* 83 */ SyscallDesc("mkdir", unimplementedFunc),
+ /* 84 */ SyscallDesc("rmdir", unimplementedFunc),
+ /* 85 */ SyscallDesc("creat", unimplementedFunc),
+ /* 86 */ SyscallDesc("link", unimplementedFunc),
+ /* 87 */ SyscallDesc("unlink", unimplementedFunc),
+ /* 88 */ SyscallDesc("symlink", unimplementedFunc),
+ /* 89 */ SyscallDesc("readlink", unimplementedFunc),
+ /* 90 */ SyscallDesc("chmod", unimplementedFunc),
+ /* 91 */ SyscallDesc("fchmod", unimplementedFunc),
+ /* 92 */ SyscallDesc("chown", unimplementedFunc),
+ /* 93 */ SyscallDesc("fchown", unimplementedFunc),
+ /* 94 */ SyscallDesc("lchown", unimplementedFunc),
+ /* 95 */ SyscallDesc("umask", unimplementedFunc),
+ /* 96 */ SyscallDesc("gettimeofday", unimplementedFunc),
+ /* 97 */ SyscallDesc("getrlimit", unimplementedFunc),
+ /* 98 */ SyscallDesc("getrusage", unimplementedFunc),
+ /* 99 */ SyscallDesc("sysinfo", unimplementedFunc),
+ /* 100 */ SyscallDesc("times", unimplementedFunc),
+ /* 101 */ SyscallDesc("ptrace", unimplementedFunc),
+ /* 102 */ SyscallDesc("getuid", unimplementedFunc),
+ /* 103 */ SyscallDesc("syslog", unimplementedFunc),
+ /* 104 */ SyscallDesc("getgid", unimplementedFunc),
+ /* 105 */ SyscallDesc("setuid", unimplementedFunc),
+ /* 106 */ SyscallDesc("setgid", unimplementedFunc),
+ /* 107 */ SyscallDesc("geteuid", unimplementedFunc),
+ /* 108 */ SyscallDesc("getegid", unimplementedFunc),
+ /* 109 */ SyscallDesc("setpgid", unimplementedFunc),
+ /* 110 */ SyscallDesc("getppid", unimplementedFunc),
+ /* 111 */ SyscallDesc("getpgrp", unimplementedFunc),
+ /* 112 */ SyscallDesc("setsid", unimplementedFunc),
+ /* 113 */ SyscallDesc("setreuid", unimplementedFunc),
+ /* 114 */ SyscallDesc("setregid", unimplementedFunc),
+ /* 115 */ SyscallDesc("getgroups", unimplementedFunc),
+ /* 116 */ SyscallDesc("setgroups", unimplementedFunc),
+ /* 117 */ SyscallDesc("setresuid", unimplementedFunc),
+ /* 118 */ SyscallDesc("getresuid", unimplementedFunc),
+ /* 119 */ SyscallDesc("setresgid", unimplementedFunc),
+ /* 120 */ SyscallDesc("getresgid", unimplementedFunc),
+ /* 121 */ SyscallDesc("getpgid", unimplementedFunc),
+ /* 122 */ SyscallDesc("setfsuid", unimplementedFunc),
+ /* 123 */ SyscallDesc("setfsgid", unimplementedFunc),
+ /* 124 */ SyscallDesc("getsid", unimplementedFunc),
+ /* 125 */ SyscallDesc("capget", unimplementedFunc),
+ /* 126 */ SyscallDesc("capset", unimplementedFunc),
+ /* 127 */ SyscallDesc("rt_sigpending", unimplementedFunc),
+ /* 128 */ SyscallDesc("rt_sigtimedwait", unimplementedFunc),
+ /* 129 */ SyscallDesc("rt_sigqueueinfo", unimplementedFunc),
+ /* 130 */ SyscallDesc("rt_sigsuspend", unimplementedFunc),
+ /* 131 */ SyscallDesc("sigaltstack", unimplementedFunc),
+ /* 132 */ SyscallDesc("utime", unimplementedFunc),
+ /* 133 */ SyscallDesc("mknod", unimplementedFunc),
+ /* 134 */ SyscallDesc("uselib", unimplementedFunc),
+ /* 135 */ SyscallDesc("personality", unimplementedFunc),
+ /* 136 */ SyscallDesc("ustat", unimplementedFunc),
+ /* 137 */ SyscallDesc("statfs", unimplementedFunc),
+ /* 138 */ SyscallDesc("fstatfs", unimplementedFunc),
+ /* 139 */ SyscallDesc("sysfs", unimplementedFunc),
+ /* 140 */ SyscallDesc("getpriority", unimplementedFunc),
+ /* 141 */ SyscallDesc("setpriority", unimplementedFunc),
+ /* 142 */ SyscallDesc("sched_setparam", unimplementedFunc),
+ /* 143 */ SyscallDesc("sched_getparam", unimplementedFunc),
+ /* 144 */ SyscallDesc("sched_setscheduler", unimplementedFunc),
+ /* 145 */ SyscallDesc("sched_getscheduler", unimplementedFunc),
+ /* 146 */ SyscallDesc("sched_get_priority_max", unimplementedFunc),
+ /* 147 */ SyscallDesc("sched_get_priority_min", unimplementedFunc),
+ /* 148 */ SyscallDesc("sched_rr_get_interval", unimplementedFunc),
+ /* 149 */ SyscallDesc("mlock", unimplementedFunc),
+ /* 150 */ SyscallDesc("munlock", unimplementedFunc),
+ /* 151 */ SyscallDesc("mlockall", unimplementedFunc),
+ /* 152 */ SyscallDesc("munlockall", unimplementedFunc),
+ /* 153 */ SyscallDesc("vhangup", unimplementedFunc),
+ /* 154 */ SyscallDesc("modify_ldt", unimplementedFunc),
+ /* 155 */ SyscallDesc("pivot_root", unimplementedFunc),
+ /* 156 */ SyscallDesc("_sysctl", unimplementedFunc),
+ /* 157 */ SyscallDesc("prctl", unimplementedFunc),
+ /* 158 */ SyscallDesc("arch_prctl", unimplementedFunc),
+ /* 159 */ SyscallDesc("adjtimex", unimplementedFunc),
+ /* 160 */ SyscallDesc("setrlimit", unimplementedFunc),
+ /* 161 */ SyscallDesc("chroot", unimplementedFunc),
+ /* 162 */ SyscallDesc("sync", unimplementedFunc),
+ /* 163 */ SyscallDesc("acct", unimplementedFunc),
+ /* 164 */ SyscallDesc("settimeofday", unimplementedFunc),
+ /* 165 */ SyscallDesc("mount", unimplementedFunc),
+ /* 166 */ SyscallDesc("umount2", unimplementedFunc),
+ /* 167 */ SyscallDesc("swapon", unimplementedFunc),
+ /* 168 */ SyscallDesc("swapoff", unimplementedFunc),
+ /* 169 */ SyscallDesc("reboot", unimplementedFunc),
+ /* 170 */ SyscallDesc("sethostname", unimplementedFunc),
+ /* 171 */ SyscallDesc("setdomainname", unimplementedFunc),
+ /* 172 */ SyscallDesc("iopl", unimplementedFunc),
+ /* 173 */ SyscallDesc("ioperm", unimplementedFunc),
+ /* 174 */ SyscallDesc("create_module", unimplementedFunc),
+ /* 175 */ SyscallDesc("init_module", unimplementedFunc),
+ /* 176 */ SyscallDesc("delete_module", unimplementedFunc),
+ /* 177 */ SyscallDesc("get_kernel_syms", unimplementedFunc),
+ /* 178 */ SyscallDesc("query_module", unimplementedFunc),
+ /* 179 */ SyscallDesc("quotactl", unimplementedFunc),
+ /* 180 */ SyscallDesc("nfsservctl", unimplementedFunc),
+ /* 181 */ SyscallDesc("getpmsg", unimplementedFunc),
+ /* 182 */ SyscallDesc("putpmsg", unimplementedFunc),
+ /* 183 */ SyscallDesc("afs_syscall", unimplementedFunc),
+ /* 184 */ SyscallDesc("tuxcall", unimplementedFunc),
+ /* 185 */ SyscallDesc("security", unimplementedFunc),
+ /* 186 */ SyscallDesc("gettid", unimplementedFunc),
+ /* 187 */ SyscallDesc("readahead", unimplementedFunc),
+ /* 188 */ SyscallDesc("setxattr", unimplementedFunc),
+ /* 189 */ SyscallDesc("lsetxattr", unimplementedFunc),
+ /* 190 */ SyscallDesc("fsetxattr", unimplementedFunc),
+ /* 191 */ SyscallDesc("getxattr", unimplementedFunc),
+ /* 192 */ SyscallDesc("lgetxattr", unimplementedFunc),
+ /* 193 */ SyscallDesc("fgetxattr", unimplementedFunc),
+ /* 194 */ SyscallDesc("listxattr", unimplementedFunc),
+ /* 195 */ SyscallDesc("llistxattr", unimplementedFunc),
+ /* 196 */ SyscallDesc("flistxattr", unimplementedFunc),
+ /* 197 */ SyscallDesc("removexattr", unimplementedFunc),
+ /* 198 */ SyscallDesc("lremovexattr", unimplementedFunc),
+ /* 199 */ SyscallDesc("fremovexattr", unimplementedFunc),
+ /* 200 */ SyscallDesc("tkill", unimplementedFunc),
+ /* 201 */ SyscallDesc("time", unimplementedFunc),
+ /* 202 */ SyscallDesc("futex", unimplementedFunc),
+ /* 203 */ SyscallDesc("sched_setaffinity", unimplementedFunc),
+ /* 204 */ SyscallDesc("sched_getaffinity", unimplementedFunc),
+ /* 205 */ SyscallDesc("set_thread_area", unimplementedFunc),
+ /* 206 */ SyscallDesc("io_setup", unimplementedFunc),
+ /* 207 */ SyscallDesc("io_destroy", unimplementedFunc),
+ /* 208 */ SyscallDesc("io_getevents", unimplementedFunc),
+ /* 209 */ SyscallDesc("io_submit", unimplementedFunc),
+ /* 210 */ SyscallDesc("io_cancel", unimplementedFunc),
+ /* 211 */ SyscallDesc("get_thread_area", unimplementedFunc),
+ /* 212 */ SyscallDesc("lookup_dcookie", unimplementedFunc),
+ /* 213 */ SyscallDesc("epoll_create", unimplementedFunc),
+ /* 214 */ SyscallDesc("epoll_ctl_old", unimplementedFunc),
+ /* 215 */ SyscallDesc("epoll_wait_old", unimplementedFunc),
+ /* 216 */ SyscallDesc("remap_file_pages", unimplementedFunc),
+ /* 217 */ SyscallDesc("getdents64", unimplementedFunc),
+ /* 218 */ SyscallDesc("set_tid_address", unimplementedFunc),
+ /* 219 */ SyscallDesc("restart_syscall", unimplementedFunc),
+ /* 220 */ SyscallDesc("semtimedop", unimplementedFunc),
+ /* 221 */ SyscallDesc("fadvise64", unimplementedFunc),
+ /* 222 */ SyscallDesc("timer_create", unimplementedFunc),
+ /* 223 */ SyscallDesc("timer_settime", unimplementedFunc),
+ /* 224 */ SyscallDesc("timer_gettime", unimplementedFunc),
+ /* 225 */ SyscallDesc("timer_getoverrun", unimplementedFunc),
+ /* 226 */ SyscallDesc("timer_delete", unimplementedFunc),
+ /* 227 */ SyscallDesc("clock_settime", unimplementedFunc),
+ /* 228 */ SyscallDesc("clock_gettime", unimplementedFunc),
+ /* 229 */ SyscallDesc("clock_getres", unimplementedFunc),
+ /* 230 */ SyscallDesc("clock_nanosleep", unimplementedFunc),
+ /* 231 */ SyscallDesc("exit_group", unimplementedFunc),
+ /* 232 */ SyscallDesc("epoll_wait", unimplementedFunc),
+ /* 233 */ SyscallDesc("epoll_ctl", unimplementedFunc),
+ /* 234 */ SyscallDesc("tgkill", unimplementedFunc),
+ /* 235 */ SyscallDesc("utimes", unimplementedFunc),
+ /* 236 */ SyscallDesc("vserver", unimplementedFunc),
+ /* 237 */ SyscallDesc("mbind", unimplementedFunc),
+ /* 238 */ SyscallDesc("set_mempolicy", unimplementedFunc),
+ /* 239 */ SyscallDesc("get_mempolicy", unimplementedFunc),
+ /* 240 */ SyscallDesc("mq_open", unimplementedFunc),
+ /* 241 */ SyscallDesc("mq_unlink", unimplementedFunc),
+ /* 242 */ SyscallDesc("mq_timedsend", unimplementedFunc),
+ /* 243 */ SyscallDesc("mq_timedreceive", unimplementedFunc),
+ /* 244 */ SyscallDesc("mq_notify", unimplementedFunc),
+ /* 245 */ SyscallDesc("mq_getsetattr", unimplementedFunc),
+ /* 246 */ SyscallDesc("kexec_load", unimplementedFunc),
+ /* 247 */ SyscallDesc("waitid", unimplementedFunc),
+ /* 248 */ SyscallDesc("add_key", unimplementedFunc),
+ /* 249 */ SyscallDesc("request_key", unimplementedFunc),
+ /* 250 */ SyscallDesc("keyctl", unimplementedFunc),
+ /* 251 */ SyscallDesc("ioprio_set", unimplementedFunc),
+ /* 252 */ SyscallDesc("ioprio_get", unimplementedFunc),
+ /* 253 */ SyscallDesc("inotify_init", unimplementedFunc),
+ /* 254 */ SyscallDesc("inotify_add_watch", unimplementedFunc),
+ /* 255 */ SyscallDesc("inotify_rm_watch", unimplementedFunc),
+ /* 256 */ SyscallDesc("migrate_pages", unimplementedFunc),
+ /* 257 */ SyscallDesc("openat", unimplementedFunc),
+ /* 258 */ SyscallDesc("mkdirat", unimplementedFunc),
+ /* 259 */ SyscallDesc("mknodat", unimplementedFunc),
+ /* 260 */ SyscallDesc("fchownat", unimplementedFunc),
+ /* 261 */ SyscallDesc("futimesat", unimplementedFunc),
+ /* 262 */ SyscallDesc("newfstatat", unimplementedFunc),
+ /* 263 */ SyscallDesc("unlinkat", unimplementedFunc),
+ /* 264 */ SyscallDesc("renameat", unimplementedFunc),
+ /* 265 */ SyscallDesc("linkat", unimplementedFunc),
+ /* 266 */ SyscallDesc("symlinkat", unimplementedFunc),
+ /* 267 */ SyscallDesc("readlinkat", unimplementedFunc),
+ /* 268 */ SyscallDesc("fchmodat", unimplementedFunc),
+ /* 269 */ SyscallDesc("faccessat", unimplementedFunc),
+ /* 270 */ SyscallDesc("pselect6", unimplementedFunc),
+ /* 271 */ SyscallDesc("ppoll", unimplementedFunc),
+ /* 272 */ SyscallDesc("unshare", unimplementedFunc)
+};
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Steve Reinhardt
+ */
+
+#ifndef __ARCH_X86_LOCKEDMEM_HH__
+#define __ARCH_X86_LOCKEDMEM_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for locked memory accesses.
+ */
+
+#include "mem/request.hh"
+
+namespace X86ISA
+{
+ template <class XC>
+ inline void
+ handleLockedRead(XC *xc, Request *req)
+ {
+ }
+
+ template <class XC>
+ inline bool
+ handleLockedWrite(XC *xc, Request *req)
+ {
+ return true;
+ }
+};
+
+#endif // __ARCH_X86_LOCKEDMEM_HH__
--- /dev/null
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/miscregfile.hh"
+
+using namespace X86ISA;
+using namespace std;
+
+class Checkpoint;
+
+//These functions map register indices to names
+string X86ISA::getMiscRegName(RegIndex index)
+{
+ panic("No misc registers in x86 yet!\n");
+}
+
+void MiscRegFile::clear()
+{
+ //When there are actually misc regs implemented, this will clear them
+}
+
+MiscReg MiscRegFile::readReg(int miscReg)
+{
+ panic("No misc registers in x86 yet!\n");
+}
+
+MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
+{
+ panic("No misc registers in x86 yet!\n");
+}
+
+void MiscRegFile::setReg(int miscReg, const MiscReg &val)
+{
+ panic("No misc registers in x86 yet!\n");
+}
+
+void MiscRegFile::setRegWithEffect(int miscReg,
+ const MiscReg &val, ThreadContext * tc)
+{
+ panic("No misc registers in x86 yet!\n");
+}
+
+void MiscRegFile::serialize(std::ostream & os)
+{
+ panic("No misc registers in x86 yet!\n");
+}
+
+void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
+{
+ panic("No misc registers in x86 yet!\n");
+}
--- /dev/null
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_MISCREGFILE_HH__
+#define __ARCH_X86_MISCREGFILE_HH__
+
+#include "arch/x86/faults.hh"
+#include "arch/x86/types.hh"
+
+#include <string>
+
+class Checkpoint;
+
+namespace X86ISA
+{
+ std::string getMiscRegName(RegIndex);
+
+ //These will have to be updated in the future.
+ const int NumMiscArchRegs = 0;
+ const int NumMiscRegs = 0;
+
+ class MiscRegFile
+ {
+ public:
+ void clear();
+
+ MiscRegFile()
+ {
+ clear();
+ }
+
+ MiscReg readReg(int miscReg);
+
+ MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
+
+ void setReg(int miscReg, const MiscReg &val);
+
+ void setRegWithEffect(int miscReg,
+ const MiscReg &val, ThreadContext *tc);
+
+ void serialize(std::ostream & os);
+
+ void unserialize(Checkpoint * cp, const std::string §ion);
+
+ void copyMiscRegs(ThreadContext * tc);
+ };
+}
+
+#endif //__ARCH_X86_MISCREGFILE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_MMAPEDIPR_HH__
+#define __ARCH_X86_MMAPEDIPR_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for memory mapped IPR accesses.
+ */
+
+#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
+#include "mem/packet.hh"
+
+namespace X86ISA
+{
+ inline Tick
+ handleIprRead(ThreadContext *xc, Packet *pkt)
+ {
+#if !FULL_SYSTEM
+ panic("Shouldn't have a memory mapped register in SE\n");
+#endif
+ }
+
+ inline Tick
+ handleIprWrite(ThreadContext *xc, Packet *pkt)
+ {
+#if !FULL_SYSTEM
+ panic("Shouldn't have a memory mapped register in SE\n");
+#endif
+ }
+};
+
+#endif // __ARCH_X86_MMAPEDIPR_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_PAGETABLE_HH__
+#define __ARCH_X86_PAGETABLE_HH__
+
+#include "sim/host.hh"
+#include "base/misc.hh"
+
+namespace X86ISA
+{
+ struct VAddr
+ {
+ VAddr(Addr a) { panic("not implemented yet."); }
+ };
+
+ class PageTableEntry
+ {
+ };
+}
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ * Ali Saidi
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/process.hh"
+#include "arch/x86/types.hh"
+#include "base/loader/object_file.hh"
+#include "base/loader/elf_object.hh"
+#include "base/misc.hh"
+#include "cpu/thread_context.hh"
+#include "mem/page_table.hh"
+#include "mem/translating_port.hh"
+#include "sim/system.hh"
+
+using namespace std;
+using namespace X86ISA;
+
+M5_64_auxv_t::M5_64_auxv_t(int64_t type, int64_t val)
+{
+ a_type = TheISA::htog(type);
+ a_val = TheISA::htog(val);
+}
+
+X86LiveProcess::X86LiveProcess(const std::string &nm, ObjectFile *objFile,
+ System *_system, int stdin_fd, int stdout_fd, int stderr_fd,
+ std::vector<std::string> &argv, std::vector<std::string> &envp,
+ const std::string &cwd,
+ uint64_t _uid, uint64_t _euid, uint64_t _gid, uint64_t _egid,
+ uint64_t _pid, uint64_t _ppid)
+ : LiveProcess(nm, objFile, _system, stdin_fd, stdout_fd, stderr_fd,
+ argv, envp, cwd, _uid, _euid, _gid, _egid, _pid, _ppid)
+{
+ brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
+ brk_point = roundUp(brk_point, VMPageSize);
+
+ // Set pointer for next thread stack. Reserve 8M for main stack.
+ next_thread_stack_base = stack_base - (8 * 1024 * 1024);
+
+ // Set up stack. On SPARC Linux, stack goes from the top of memory
+ // downward, less the hole for the kernel address space.
+ stack_base = (Addr)0x80000000000ULL;
+
+ // Set up region for mmaps. Tru64 seems to start just above 0 and
+ // grow up from there.
+ mmap_start = mmap_end = 0xfffff80000000000ULL;
+}
+
+void X86LiveProcess::handleTrap(int trapNum, ThreadContext *tc)
+{
+ switch(trapNum)
+ {
+ default:
+ panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum);
+ }
+}
+
+void
+X86LiveProcess::startup()
+{
+ argsInit(sizeof(IntReg), VMPageSize);
+
+ //The AMD64 abi says that only rsp and rdx are defined at process
+ //startup. rsp will be set by argsInit, and I don't understand what
+ //rdx should be set to. The other floating point and integer registers
+ //will be zeroed by the register file constructors, but control registers
+ //should be initialized here. Since none of those are implemented, there
+ //isn't anything here.
+}
+
+void
+X86LiveProcess::argsInit(int intSize, int pageSize)
+{
+ typedef M5_64_auxv_t auxv_t;
+ Process::startup();
+
+ string filename;
+ if(argv.size() < 1)
+ filename = "";
+ else
+ filename = argv[0];
+
+ Addr alignmentMask = ~(intSize - 1);
+
+ // load object file into target memory
+ objFile->loadSections(initVirtMem);
+
+ //These are the auxilliary vector types
+ enum auxTypes
+ {
+ X86_AT_NULL = 0,
+ X86_AT_IGNORE = 1,
+ X86_AT_EXECFD = 2,
+ X86_AT_PHDR = 3,
+ X86_AT_PHENT = 4,
+ X86_AT_PHNUM = 5,
+ X86_AT_PAGESZ = 6,
+ X86_AT_BASE = 7,
+ X86_AT_FLAGS = 8,
+ X86_AT_ENTRY = 9,
+ X86_AT_NOTELF = 10,
+ X86_AT_UID = 11,
+ X86_AT_EUID = 12,
+ X86_AT_GID = 13,
+ X86_AT_EGID = 14
+ };
+
+ //Setup the auxilliary vectors. These will already have endian conversion.
+ //Auxilliary vectors are loaded only for elf formatted executables.
+ ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
+ if(elfObject)
+ {
+ /*
+ //Bits which describe the system hardware capabilities
+ auxv.push_back(auxv_t(SPARC_AT_HWCAP, hwcap));
+ //The system page size
+ auxv.push_back(auxv_t(SPARC_AT_PAGESZ, SparcISA::VMPageSize));
+ //Defined to be 100 in the kernel source.
+ //Frequency at which times() increments
+ auxv.push_back(auxv_t(SPARC_AT_CLKTCK, 100));
+ // For statically linked executables, this is the virtual address of the
+ // program header tables if they appear in the executable image
+ auxv.push_back(auxv_t(SPARC_AT_PHDR, elfObject->programHeaderTable()));
+ // This is the size of a program header entry from the elf file.
+ auxv.push_back(auxv_t(SPARC_AT_PHENT, elfObject->programHeaderSize()));
+ // This is the number of program headers from the original elf file.
+ auxv.push_back(auxv_t(SPARC_AT_PHNUM, elfObject->programHeaderCount()));
+ //This is the address of the elf "interpreter", It should be set
+ //to 0 for regular executables. It should be something else
+ //(not sure what) for dynamic libraries.
+ auxv.push_back(auxv_t(SPARC_AT_BASE, 0));
+ //This is hardwired to 0 in the elf loading code in the kernel
+ auxv.push_back(auxv_t(SPARC_AT_FLAGS, 0));
+ //The entry point to the program
+ auxv.push_back(auxv_t(SPARC_AT_ENTRY, objFile->entryPoint()));
+ //Different user and group IDs
+ auxv.push_back(auxv_t(SPARC_AT_UID, uid()));
+ auxv.push_back(auxv_t(SPARC_AT_EUID, euid()));
+ auxv.push_back(auxv_t(SPARC_AT_GID, gid()));
+ auxv.push_back(auxv_t(SPARC_AT_EGID, egid()));
+ //Whether to enable "secure mode" in the executable
+ auxv.push_back(auxv_t(SPARC_AT_SECURE, 0));*/
+ }
+
+ //Figure out how big the initial stack needs to be
+
+ // The unaccounted for 0 at the top of the stack
+ int mysterious_size = intSize;
+
+ //This is the name of the file which is present on the initial stack
+ //It's purpose is to let the user space linker examine the original file.
+ int file_name_size = filename.size() + 1;
+
+ int env_data_size = 0;
+ for (int i = 0; i < envp.size(); ++i) {
+ env_data_size += envp[i].size() + 1;
+ }
+ int arg_data_size = 0;
+ for (int i = 0; i < argv.size(); ++i) {
+ arg_data_size += argv[i].size() + 1;
+ }
+
+ //The info_block needs to be padded so it's size is a multiple of the
+ //alignment mask. Also, it appears that there needs to be at least some
+ //padding, so if the size is already a multiple, we need to increase it
+ //anyway.
+ int info_block_size =
+ (file_name_size +
+ env_data_size +
+ arg_data_size +
+ intSize) & alignmentMask;
+
+ int info_block_padding =
+ info_block_size -
+ file_name_size -
+ env_data_size -
+ arg_data_size;
+
+ //Each auxilliary vector is two 8 byte words
+ int aux_array_size = intSize * 2 * (auxv.size() + 1);
+
+ int envp_array_size = intSize * (envp.size() + 1);
+ int argv_array_size = intSize * (argv.size() + 1);
+
+ int argc_size = intSize;
+ int window_save_size = intSize * 16;
+
+ int space_needed =
+ mysterious_size +
+ info_block_size +
+ aux_array_size +
+ envp_array_size +
+ argv_array_size +
+ argc_size +
+ window_save_size;
+
+ stack_min = stack_base - space_needed;
+ stack_min &= alignmentMask;
+ stack_size = stack_base - stack_min;
+
+ // map memory
+ pTable->allocate(roundDown(stack_min, pageSize),
+ roundUp(stack_size, pageSize));
+
+ // map out initial stack contents
+ Addr mysterious_base = stack_base - mysterious_size;
+ Addr file_name_base = mysterious_base - file_name_size;
+ Addr env_data_base = file_name_base - env_data_size;
+ Addr arg_data_base = env_data_base - arg_data_size;
+ Addr auxv_array_base = arg_data_base - aux_array_size - info_block_padding;
+ Addr envp_array_base = auxv_array_base - envp_array_size;
+ Addr argv_array_base = envp_array_base - argv_array_size;
+ Addr argc_base = argv_array_base - argc_size;
+#ifndef NDEBUG
+ // only used in DPRINTF
+ Addr window_save_base = argc_base - window_save_size;
+#endif
+
+ DPRINTF(X86, "The addresses of items on the initial stack:\n");
+ DPRINTF(X86, "0x%x - file name\n", file_name_base);
+ DPRINTF(X86, "0x%x - env data\n", env_data_base);
+ DPRINTF(X86, "0x%x - arg data\n", arg_data_base);
+ DPRINTF(X86, "0x%x - auxv array\n", auxv_array_base);
+ DPRINTF(X86, "0x%x - envp array\n", envp_array_base);
+ DPRINTF(X86, "0x%x - argv array\n", argv_array_base);
+ DPRINTF(X86, "0x%x - argc \n", argc_base);
+ DPRINTF(X86, "0x%x - window save\n", window_save_base);
+ DPRINTF(X86, "0x%x - stack min\n", stack_min);
+
+ // write contents to stack
+
+ // figure out argc
+ uint64_t argc = argv.size();
+ uint64_t guestArgc = TheISA::htog(argc);
+
+ //Write out the mysterious 0
+ uint64_t mysterious_zero = 0;
+ initVirtMem->writeBlob(mysterious_base,
+ (uint8_t*)&mysterious_zero, mysterious_size);
+
+ //Write the file name
+ initVirtMem->writeString(file_name_base, filename.c_str());
+
+ //Copy the aux stuff
+ for(int x = 0; x < auxv.size(); x++)
+ {
+ initVirtMem->writeBlob(auxv_array_base + x * 2 * intSize,
+ (uint8_t*)&(auxv[x].a_type), intSize);
+ initVirtMem->writeBlob(auxv_array_base + (x * 2 + 1) * intSize,
+ (uint8_t*)&(auxv[x].a_val), intSize);
+ }
+ //Write out the terminating zeroed auxilliary vector
+ const uint64_t zero = 0;
+ initVirtMem->writeBlob(auxv_array_base + 2 * intSize * auxv.size(),
+ (uint8_t*)&zero, 2 * intSize);
+
+ copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
+ copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
+
+ initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
+
+ //Set up the thread context to start running the process
+ threadContexts[0]->setIntReg(ArgumentReg0, argc);
+ threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+ threadContexts[0]->setIntReg(StackPointerReg, stack_min);
+
+ Addr prog_entry = objFile->entryPoint();
+ threadContexts[0]->setPC(prog_entry);
+ threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
+
+ //Align the "stack_min" to a page boundary.
+ stack_min = roundDown(stack_min, pageSize);
+
+// num_processes++;
+}
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_PROCESS_HH__
+#define __ARCH_X86_PROCESS_HH__
+
+#include <string>
+#include <vector>
+#include "sim/process.hh"
+
+namespace X86ISA
+{
+ struct M5_64_auxv_t
+ {
+ int64_t a_type;
+ union {
+ int64_t a_val;
+ int64_t a_ptr;
+ int64_t a_fcn;
+ };
+
+ M5_64_auxv_t()
+ {}
+
+ M5_64_auxv_t(int64_t type, int64_t val);
+ };
+
+ class X86LiveProcess : public LiveProcess
+ {
+ protected:
+ std::vector<M5_64_auxv_t> auxv;
+
+ X86LiveProcess(const std::string &nm, ObjectFile *objFile,
+ System *_system,
+ int stdin_fd, int stdout_fd, int stderr_fd,
+ std::vector<std::string> &argv,
+ std::vector<std::string> &envp,
+ const std::string &cwd,
+ uint64_t _uid, uint64_t _euid,
+ uint64_t _gid, uint64_t _egid,
+ uint64_t _pid, uint64_t _ppid);
+
+ void startup();
+
+ public:
+
+ //Handles traps which request services from the operating system
+ virtual void handleTrap(int trapNum, ThreadContext *tc);
+
+ void argsInit(int intSize, int pageSize);
+ };
+}
+
+#endif // __ARCH_X86_PROCESS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2003-2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/regfile.hh"
+#include "sim/serialize.hh"
+#include "cpu/thread_context.hh"
+
+class Checkpoint;
+
+using namespace X86ISA;
+using namespace std;
+
+//RegFile class methods
+Addr RegFile::readPC()
+{
+ return rip;
+}
+
+void RegFile::setPC(Addr val)
+{
+ rip = val;
+}
+
+Addr RegFile::readNextPC()
+{
+ return nextRip;
+}
+
+void RegFile::setNextPC(Addr val)
+{
+ nextRip = val;
+}
+
+Addr RegFile::readNextNPC()
+{
+ return nextRip + sizeof(MachInst);
+}
+
+void RegFile::setNextNPC(Addr val)
+{ }
+
+void RegFile::clear()
+{
+ floatRegFile.clear();
+ intRegFile.clear();
+ miscRegFile.clear();
+}
+
+MiscReg RegFile::readMiscReg(int miscReg)
+{
+ return miscRegFile.readReg(miscReg);
+}
+
+MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
+{
+ return miscRegFile.readRegWithEffect(miscReg, tc);
+}
+
+void RegFile::setMiscReg(int miscReg, const MiscReg &val)
+{
+ miscRegFile.setReg(miscReg, val);
+}
+
+void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ ThreadContext * tc)
+{
+ miscRegFile.setRegWithEffect(miscReg, val, tc);
+}
+
+FloatReg RegFile::readFloatReg(int floatReg, int width)
+{
+ return floatRegFile.readReg(floatReg, width);
+}
+
+FloatReg RegFile::readFloatReg(int floatReg)
+{
+ //Use the "natural" width of a single float
+ return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
+}
+
+FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
+{
+ return floatRegFile.readRegBits(floatReg, width);
+}
+
+FloatRegBits RegFile::readFloatRegBits(int floatReg)
+{
+ //Use the "natural width of a single float
+ return floatRegFile.readRegBits(floatReg,
+ FloatRegFile::SingleWidth);
+}
+
+void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
+{
+ floatRegFile.setReg(floatReg, val, width);
+}
+
+void RegFile::setFloatReg(int floatReg, const FloatReg &val)
+{
+ //Use the "natural" width of a single float
+ setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
+}
+
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
+{
+ floatRegFile.setRegBits(floatReg, val, width);
+}
+
+void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
+{
+ //Use the "natural" width of a single float
+ floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
+}
+
+IntReg RegFile::readIntReg(int intReg)
+{
+ return intRegFile.readReg(intReg);
+}
+
+void RegFile::setIntReg(int intReg, const IntReg &val)
+{
+ intRegFile.setReg(intReg, val);
+}
+
+int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
+{
+ //For right now, don't do any flattening
+ return reg;
+}
+
+void RegFile::serialize(std::ostream &os)
+{
+ intRegFile.serialize(os);
+ floatRegFile.serialize(os);
+ miscRegFile.serialize(os);
+ SERIALIZE_SCALAR(rip);
+ SERIALIZE_SCALAR(nextRip);
+}
+
+void RegFile::unserialize(Checkpoint *cp, const std::string §ion)
+{
+ intRegFile.unserialize(cp, section);
+ floatRegFile.unserialize(cp, section);
+ miscRegFile.unserialize(cp, section);
+ UNSERIALIZE_SCALAR(rip);
+ UNSERIALIZE_SCALAR(nextRip);
+}
+
+void RegFile::changeContext(RegContextParam param, RegContextVal val)
+{
+ panic("changeContext not implemented for x86!\n");
+}
+
+void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("copyMiscRegs not implemented for x86!\n");
+}
+
+void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
+{
+ panic("copyRegs not implemented for x86!\n");
+ //copy int regs
+ //copy float regs
+ copyMiscRegs(src, dest);
+
+ dest->setPC(src->readPC());
+ dest->setNextPC(src->readNextPC());
+}
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_REGFILE_HH__
+#define __ARCH_X86_REGFILE_HH__
+
+#include "arch/x86/floatregfile.hh"
+#include "arch/x86/intregfile.hh"
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/miscregfile.hh"
+#include "arch/x86/types.hh"
+#include "sim/host.hh"
+
+#include <string>
+
+class Checkpoint;
+
+namespace X86ISA
+{
+ class RegFile
+ {
+ protected:
+ Addr rip; //Program Counter
+ Addr nextRip; //Next Program Counter
+
+ public:
+ Addr readPC();
+ void setPC(Addr val);
+
+ Addr readNextPC();
+ void setNextPC(Addr val);
+
+ Addr readNextNPC();
+ void setNextNPC(Addr val);
+
+ protected:
+ IntRegFile intRegFile; // integer register file
+ FloatRegFile floatRegFile; // floating point register file
+ MiscRegFile miscRegFile; // control register file
+
+ public:
+
+ void clear();
+
+ int FlattenIntIndex(int reg);
+
+ MiscReg readMiscReg(int miscReg);
+
+ MiscReg readMiscRegWithEffect(int miscReg, ThreadContext *tc);
+
+ void setMiscReg(int miscReg, const MiscReg &val);
+
+ void setMiscRegWithEffect(int miscReg, const MiscReg &val,
+ ThreadContext * tc);
+
+ int instAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ int dataAsid()
+ {
+ //XXX This doesn't make sense in x86
+ return 0;
+ }
+
+ FloatReg readFloatReg(int floatReg, int width);
+
+ FloatReg readFloatReg(int floatReg);
+
+ FloatRegBits readFloatRegBits(int floatReg, int width);
+
+ FloatRegBits readFloatRegBits(int floatReg);
+
+ void setFloatReg(int floatReg, const FloatReg &val, int width);
+
+ void setFloatReg(int floatReg, const FloatReg &val);
+
+ void setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
+
+ void setFloatRegBits(int floatReg, const FloatRegBits &val);
+
+ IntReg readIntReg(int intReg);
+
+ void setIntReg(int intReg, const IntReg &val);
+
+ void serialize(std::ostream &os);
+ void unserialize(Checkpoint *cp, const std::string §ion);
+
+ public:
+
+ void changeContext(RegContextParam param, RegContextVal val);
+ };
+
+ int flattenIntIndex(ThreadContext * tc, int reg);
+
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+ int InterruptLevel(uint64_t softint);
+
+}; // namespace X86ISA
+
+#endif // __ARCH_X86_REGFILE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+/*
+ * Copyright (c) 1990, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This software was developed by the Computer Systems Engineering group
+ * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
+ * contributed to Berkeley.
+ *
+ * All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Lawrence Berkeley Laboratories.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)kgdb_stub.c 8.4 (Berkeley) 1/12/94
+ */
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the NetBSD
+ * Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * $NetBSD: kgdb_stub.c,v 1.8 2001/07/07 22:58:00 wdk Exp $
+ *
+ * Taken from NetBSD
+ *
+ * "Stub" to allow remote cpu to debug over a serial line using gdb.
+ */
+
+#include <sys/signal.h>
+
+#include <string>
+#include <unistd.h>
+
+#include "arch/vtophys.hh"
+#include "arch/x86/remote_gdb.hh"
+#include "base/remote_gdb.hh"
+#include "base/socket.hh"
+#include "base/trace.hh"
+#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
+
+using namespace std;
+using namespace TheISA;
+
+RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
+ : BaseRemoteGDB(_system, c, NumGDBRegs)
+{}
+
+bool RemoteGDB::acc(Addr va, size_t len)
+{
+ panic("Remote gdb acc not implemented in x86!\n");
+}
+
+void RemoteGDB::getregs()
+{
+ panic("Remote gdb getregs not implemented in x86!\n");
+}
+
+void RemoteGDB::setregs()
+{
+ panic("Remote gdb setregs not implemented in x86!\n");
+}
+
+void RemoteGDB::clearSingleStep()
+{
+ panic("Remote gdb clearSingleStep not implemented in x86!\n");
+}
+
+void RemoteGDB::setSingleStep()
+{
+ panic("Remoge gdb setSingleStep not implemented in x86!\n");
+}
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_REMOTEGDB_HH__
+#define __ARCH_X86_REMOTEGDB_HH__
+
+#include "arch/x86/types.hh"
+#include "base/remote_gdb.hh"
+
+class System;
+class ThreadContext;
+
+namespace X86ISA
+{
+ class RemoteGDB : public BaseRemoteGDB
+ {
+ protected:
+ enum RegisterContants
+ {
+ NumGDBRegs
+ //XXX fill this in
+ };
+
+ public:
+ RemoteGDB(System *system, ThreadContext *context);
+
+ bool acc(Addr addr, size_t len);
+
+ protected:
+ void getregs();
+ void setregs();
+
+ void clearSingleStep();
+ void setSingleStep();
+
+ Addr nextBkpt;
+ };
+}
+
+#endif // __ARCH_X86_REMOTEGDB_HH__
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#ifndef __ARCH_X86_STACKTRACE_HH__
+#define __ARCH_X86_STACKTRACE_HH__
+
+#include "base/trace.hh"
+#include "cpu/static_inst.hh"
+
+class ThreadContext;
+namespace X86ISA
+{
+ class StackTrace;
+
+ class ProcessInfo
+ {
+ private:
+ ThreadContext *tc;
+
+ int thread_info_size;
+ int task_struct_size;
+ int task_off;
+ int pid_off;
+ int name_off;
+
+ public:
+ ProcessInfo(ThreadContext *_tc);
+
+ Addr task(Addr ksp) const;
+ int pid(Addr ksp) const;
+ std::string name(Addr ksp) const;
+ };
+
+ class StackTrace
+ {
+ private:
+ ThreadContext *tc;
+ std::vector<Addr> stack;
+
+ private:
+ bool isEntry(Addr addr);
+ bool decodePrologue(Addr sp, Addr callpc, Addr func, int &size, Addr &ra);
+ bool decodeSave(MachInst inst, int ®, int &disp);
+ bool decodeStack(MachInst inst, int &disp);
+
+ void trace(ThreadContext *tc, bool is_call);
+
+ public:
+ StackTrace();
+ StackTrace(ThreadContext *tc, StaticInstPtr inst);
+ ~StackTrace();
+
+ void clear()
+ {
+ tc = 0;
+ stack.clear();
+ }
+
+ bool valid() const { return tc != NULL; }
+ bool trace(ThreadContext *tc, StaticInstPtr inst);
+
+ public:
+ const std::vector<Addr> &getstack() const { return stack; }
+
+ static const int user = 1;
+ static const int console = 2;
+ static const int unknown = 3;
+
+#if TRACING_ON
+ private:
+ void dump();
+
+ public:
+ void dprintf() { if (DTRACE(Stack)) dump(); }
+#else
+ public:
+ void dprintf() {}
+#endif
+ };
+
+ inline bool
+ StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
+ {
+ if (!inst->isCall() && !inst->isReturn())
+ return false;
+
+ if (valid())
+ clear();
+
+ trace(tc, !inst->isReturn());
+ return true;
+ }
+}
+
+#endif // __ARCH_X86_STACKTRACE_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_SYSCALLRETURN_HH__
+#define __ARCH_X86_SYSCALLRETURN_HH__
+
+#include "base/misc.hh"
+#include "sim/syscallreturn.hh"
+
+class ThreadContext;
+
+namespace X86ISA
+{
+ static inline void setSyscallReturn(SyscallReturn return_value,
+ ThreadContext * tc)
+ {
+ panic("setSyscallReturn not implemented!\n");
+ }
+};
+
+#endif // __ARCH_X86_SYSCALLRETURN_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_TLB_HH__
+#define __ARCH_X86_TLB_HH__
+
+#error X86 is not yet supported!
+
+namespace X86ISA
+{
+};
+
+#endif // __ARCH_X86_TLB_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_TYPES_HH__
+#define __ARCH_X86_TYPES_HH__
+
+#include <inttypes.h>
+
+namespace X86ISA
+{
+ //XXX This won't work
+ typedef uint32_t MachInst;
+ //XXX This won't work either
+ typedef uint64_t ExtMachInst;
+
+ typedef uint64_t IntReg;
+ //XXX Should this be a 128 bit structure for XMM memory ops?
+ typedef uint64_t LargestRead;
+ typedef uint64_t MiscReg;
+
+ //These floating point types are correct for mmx, but not
+ //technically for x87 (80 bits) or at all for xmm (128 bits)
+ typedef double FloatReg;
+ typedef uint64_t FloatRegBits;
+ typedef union
+ {
+ IntReg intReg;
+ FloatReg fpReg;
+ MiscReg ctrlReg;
+ } AnyReg;
+
+ //XXX This is very hypothetical. X87 instructions would need to
+ //change their "context" constantly. It's also not clear how
+ //this would be handled as far as out of order execution.
+ //Maybe x87 instructions are in order?
+ enum RegContextParam
+ {
+ CONTEXT_X87_TOP
+ };
+
+ typedef int RegContextVal;
+
+ typedef uint8_t RegIndex;
+};
+
+#endif // __ARCH_X86_TYPES_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_UTILITY_HH__
+#define __ARCH_X86_UTILITY_HH__
+
+#include "arch/x86/types.hh"
+#include "base/misc.hh"
+#include "sim/host.hh"
+
+class ThreadContext;
+
+namespace X86ISA
+{
+ static inline bool
+ inUserMode(ThreadContext *tc)
+ {
+ return false;
+ }
+
+ inline ExtMachInst
+ makeExtMI(MachInst inst, ThreadContext * xc) {
+ return inst;
+ }
+
+ inline bool isCallerSaveIntegerRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCallerSaveFloatRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ inline bool isCalleeSaveFloatRegister(unsigned int reg) {
+ panic("register classification not implemented");
+ return false;
+ }
+
+ // Instruction address compression hooks
+ inline Addr realPCToFetchPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ inline Addr fetchPCToRealPC(const Addr &addr)
+ {
+ return addr;
+ }
+
+ // the size of "fetched" instructions (not necessarily the size
+ // of real instructions for PISA)
+ inline size_t fetchInstSize()
+ {
+ return sizeof(MachInst);
+ }
+
+ /**
+ * Function to insure ISA semantics about 0 registers.
+ * @param tc The thread context.
+ */
+ template <class TC>
+ void zeroRegisters(TC *tc);
+
+ inline void initCPU(ThreadContext *tc, int cpuId)
+ {
+ panic("initCPU not implemented!\n");
+ }
+};
+
+#endif // __ARCH_X86_UTILITY_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_VTOPHYS_HH__
+#define __ARCH_X86_VTOPHYS_HH__
+
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/pagetable.hh"
+#include "sim/host.hh"
+
+class ThreadContext;
+class FunctionalPort;
+
+namespace X86ISA
+{
+
+PageTableEntry
+kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, X86ISA::VAddr vaddr);
+
+Addr vtophys(Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
+
+};
+
+#endif // __ARCH_X86_VTOPHYS_HH__
--- /dev/null
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use. Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ * Director of Intellectual Property Licensing
+ * Office of Strategy and Technology
+ * Hewlett-Packard Company
+ * 1501 Page Mill Road
+ * Palo Alto, California 94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer. Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution. Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission. No right of
+ * sublicense is granted herewith. Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses. Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_X86TRAITS_HH__
+#define __ARCH_X86_X86TRAITS_HH__
+
+namespace X86ISA
+{
+ //XXX This will definitely need to be something larger in the future.
+ const int NumMicroIntRegs = 0;
+
+ const int NumMMXRegs = 8;
+ const int NumXMMRegs = 16;
+}
+
+#endif //__ARCH_X86_X86TRAITS_HH__
#include "base/callback.hh"
#include "base/output.hh"
#include "base/trace.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
} else if (ehdr.e_machine == EM_MIPS
&& ehdr.e_ident[EI_CLASS] == ELFCLASS32) {
arch = ObjectFile::Mips;
+ } else if (ehdr.e_machine == EM_X86_64 &&
+ ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
+ //In the future, we might want to differentiate between 32 bit
+ //and 64 bit x86 processes in case there are differences in their
+ //initial stack frame.
+ arch = ObjectFile::X86;
} else if (ehdr.e_ident[EI_CLASS] == ELFCLASS64) {
arch = ObjectFile::Alpha;
} else {
Alpha,
SPARC64,
SPARC32,
- Mips
+ Mips,
+ X86
};
enum OpSys {
#include "base/trace.hh"
#include "base/varargs.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "sim/host.hh"
#include "base/misc.hh"
#include "base/pollevent.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/serialize.hh"
using namespace std;
#include <vector>
#include <poll.h>
-#include "sim/root.hh"
+#include "sim/core.hh"
class Checkpoint;
class PollQueue;
#include "base/match.hh"
#include "base/traceflags.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
namespace Trace {
'VtoPhys',
'WriteBarrier',
'Writeback',
+ 'X86',
]
#
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/cpu.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/stat_control.hh"
#if USE_CHECKER
template <class Impl> class SparcDynInst;
struct SparcSimpleImpl;
typedef SparcDynInst<SparcSimpleImpl> O3DynInst;
+#elif THE_ISA == X86_ISA
+ template <class Impl> class X86DynInst;
+ struct X86SimpleImpl;
+ typedef X86DynInst<X86SimpleImpl> O3DynInst;
#else
#error "O3DynInst not defined for this ISA"
#endif
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#if FULL_SYSTEM
#include "arch/tlb.hh"
#include <limits>
#include <vector>
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
#include <vector>
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "cpu/ozone/inst_queue.hh"
#if 0
#include "cpu/thread_context.hh"
#include "cpu/pc_event.hh"
#include "sim/debug.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/system.hh"
using namespace std;
StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
#elif THE_ISA == SPARC_ISA
StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
+#elif THE_ISA == X86_ISA
+ StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
#elif THE_ISA == MIPS_ISA
//Mips doesn't do anything in it's MakeExtMI function right now,
//so it won't be called.
#include <iostream>
#include "cpu/static_inst.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
StaticInstPtr StaticInst::nullStaticInstPtr;
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "sim/builder.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "base/output.hh"
#include "dev/etherdump.hh"
#include "sim/builder.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using std::string;
#include "sim/builder.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "dev/alpha/tsunami_pchip.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "arch/isa_traits.hh"
using namespace std;
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/param.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include <unistd.h>
#include "cpu/base.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/syscall_emul.hh"
typedef struct stat global_stat;
#include <list>
-#include "sim/root.hh" // for Tick
+#include "sim/core.hh" // for Tick
#include "arch/isa_traits.hh" // for Addr
#include "mem/request.hh"
#include <vector>
#include "mem/cache/miss/mshr.hh"
-#include "sim/root.hh" // for curTick
+#include "sim/core.hh" // for curTick
#include "sim/host.hh"
#include "base/misc.hh"
#include "mem/cache/cache.hh"
#include "mem/cache/base_cache.hh"
#include "mem/cache/tags/iic.hh"
#include "base/intmath.hh"
-#include "sim/root.hh" // for curTick
+#include "sim/core.hh" // for curTick
#include "base/trace.hh" // for DPRINTF
#include "mem/cache/base_cache.hh"
#include "base/intmath.hh"
#include "mem/cache/tags/lru.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "mem/cache/base_cache.hh"
#include "base/intmath.hh"
#include "mem/cache/tags/split_lifo.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "base/trace.hh"
using namespace std;
#include "mem/cache/base_cache.hh"
#include "base/intmath.hh"
#include "mem/cache/tags/split_lru.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "base/misc.hh"
#include "mem/request.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
struct Packet;
#define __MEM_REQUEST_HH__
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include <cassert>
# import a few SWIG-wrapped items (those that are likely to be used
# directly by user scripts) completely into this module for
# convenience
-from internal.event import SimLoopExitEvent
+import event
# import the m5 compile options
import defines
# The final hook to generate .ini files. Called from the user script
# once the config is built.
def instantiate(root):
- params.ticks_per_sec = float(root.clock.frequency)
+ # we need to fix the global frequency
+ ticks.fixGlobalFrequency()
+
root.unproxy_all()
# ugly temporary hack to get output to config.ini
sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
# Initialize the global statistics
internal.stats.initSimStats()
+ # Create the C++ sim objects and connect ports
root.createCCObject()
root.connectPorts()
# Export curTick to user script.
def curTick():
- return internal.event.cvar.curTick
+ return internal.core.cvar.curTick
+
+# Python exit handlers happen in reverse order. We want to dump stats last.
+atexit.register(internal.stats.dump)
# register our C++ exit callback function with Python
atexit.register(internal.core.doExitCleanup)
-atexit.register(internal.stats.dump)
# This loops until all objects have been fully drained.
def doDrain(root):
need_resume.append(root)
def changeToAtomic(system):
- if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
- raise TypeError, "Object is not a root or system object. Checkpoint must be "
- "called on a root object."
+ if not isinstance(system, (objects.Root, objects.System)):
+ raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
+ (type(system), objects.Root, objects.System)
doDrain(system)
print "Changing memory mode to atomic"
system.changeTiming(internal.sim_object.SimObject.Atomic)
def changeToTiming(system):
- if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
- raise TypeError, "Object is not a root or system object. Checkpoint must be "
- "called on a root object."
+ if not isinstance(system, (objects.Root, objects.System)):
+ raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
+ (type(system), objects.Root, objects.System)
doDrain(system)
print "Changing memory mode to timing"
system.changeTiming(internal.sim_object.SimObject.Timing)
new_cpu._ccObject.resume()
index += 1
-def dumpStats():
- print 'Dumping stats'
- internal.stats.dump()
-
-def resetStats():
- print 'Resetting stats'
- internal.stats.reset()
-
# Since we have so many mutual imports in this package, we should:
# 1. Put all intra-package imports at the *bottom* of the file, unless
# they're absolutely needed before that (for top-level statements
raise ValueError, "cannot convert '%s' to latency" % value
-def toClockPeriod(value):
+def anyToLatency(value):
"""result is a clock period"""
if not isinstance(value, str):
raise ValueError, "cannot convert '%s' to clock period" % value
+def anyToFrequency(value):
+ """result is a clock period"""
+
+ if not isinstance(value, str):
+ raise TypeError, "wrong type '%s' should be str" % type(value)
+
+ try:
+ val = toFrequency(value)
+ return val
+ except ValueError:
+ pass
+
+ try:
+ val = toLatency(value)
+ if val != 0:
+ val = 1 / val
+ return val
+ except ValueError:
+ pass
+
+ raise ValueError, "cannot convert '%s' to clock period" % value
def toNetworkBandwidth(value):
if not isinstance(value, str):
--- /dev/null
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from internal.event import create
+from internal.event import SimLoopExitEvent as SimExit
+
+class ProgressEvent(object):
+ def __init__(self, period):
+ self.period = int(period)
+ self.schedule()
+
+ def schedule(self):
+ create(self, m5.curTick() + self.period)
+
+ def __call__(self):
+ print "Progress! Time now %fs" % (m5.curTick()/1e12)
+ self.schedule()
def main():
import defines
+ import event
import info
import internal
if options.trace_start:
def enable_trace():
internal.trace.cvar.enabled = True
- internal.event.create(enable_trace, int(options.trace_start))
+ event.create(enable_trace, int(options.trace_start))
else:
internal.trace.cvar.enabled = True
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
- clock = Param.Clock(Parent.clock, "clock speed")
- phase = Param.Latency("0ns", "clock phase")
+ clock = Param.Clock('1t', "clock speed")
+ phase = Param.Latency('0ns', "clock phase")
_mem_ports = []
functional = Port("Functional Access Port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
- latency = Param.Latency(Parent.clock, "latency of an access")
+ latency = Param.Latency('1t', "latency of an access")
zero = Param.Bool(False, "zero initialize memory")
class DRAMMemory(PhysicalMemory):
class Root(SimObject):
type = 'Root'
- clock = Param.RootClock('1THz', "tick frequency")
- max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
- progress_interval = Param.Tick('0',
- "print a progress message every n ticks (0 = never)")
- output_file = Param.String('cout', "file to dump simulator output to")
- checkpoint = Param.String('', "checkpoint file to load")
+ dummy = Param.Int(0, "We don't support objects without params")
import time
import convert
+import ticks
from util import *
# Dummy base class to identify types that are legitimate for SimObject
self._check()
class MemorySize32(CheckedInt):
+ cxx_type = 'uint32_t'
size = 32
unsigned = True
def __init__(self, value):
def __str__(self):
return self.value
-ticks_per_sec = None
-
# how big does a rounding error need to be before we warn about it?
frequency_tolerance = 0.001 # 0.1%
-# convert a floting-point # of ticks to integer, and warn if rounding
-# discards too much precision
-def tick_check(float_ticks):
- if float_ticks == 0:
- return 0
- int_ticks = int(round(float_ticks))
- err = (float_ticks - int_ticks) / float_ticks
- if err > frequency_tolerance:
- print >> sys.stderr, "Warning: rounding error > tolerance"
- print >> sys.stderr, " %f rounded to %d" % (float_ticks, int_ticks)
- #raise ValueError
- return int_ticks
-
-def getLatency(value):
- if isinstance(value, Latency) or isinstance(value, Clock):
- return value.value
- elif isinstance(value, Frequency) or isinstance(value, RootClock):
- return 1 / value.value
- elif isinstance(value, str):
- try:
- return convert.toLatency(value)
- except ValueError:
- try:
- return 1 / convert.toFrequency(value)
- except ValueError:
- pass # fall through
- raise ValueError, "Invalid Frequency/Latency value '%s'" % value
-
-
-class Latency(NumericParamValue):
+class TickParamValue(NumericParamValue):
cxx_type = 'Tick'
cxx_predecls = ['#include "sim/host.hh"']
swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
'%import "sim/host.hh"']
+
+class Latency(TickParamValue):
def __init__(self, value):
- self.value = getLatency(value)
+ if isinstance(value, (Latency, Clock)):
+ self.ticks = value.ticks
+ self.value = value.value
+ elif isinstance(value, Frequency):
+ self.ticks = value.ticks
+ self.value = 1.0 / value.value
+ elif value.endswith('t'):
+ self.ticks = True
+ self.value = int(value[:-1])
+ else:
+ self.ticks = False
+ self.value = convert.toLatency(value)
def __getattr__(self, attr):
if attr in ('latency', 'period'):
# convert latency to ticks
def ini_str(self):
- return str(tick_check(self.value * ticks_per_sec))
+ if self.ticks or self.value == 0:
+ return '%d' % self.value
+ else:
+ return '%d' % (ticks.fromSeconds(self.value))
-class Frequency(NumericParamValue):
- cxx_type = 'Tick'
- cxx_predecls = ['#include "sim/host.hh"']
- swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
- '%import "sim/host.hh"']
+class Frequency(TickParamValue):
def __init__(self, value):
- self.value = 1 / getLatency(value)
+ if isinstance(value, (Latency, Clock)):
+ if value.value == 0:
+ self.value = 0
+ else:
+ self.value = 1.0 / value.value
+ self.ticks = value.ticks
+ elif isinstance(value, Frequency):
+ self.value = value.value
+ self.ticks = value.ticks
+ else:
+ self.ticks = False
+ self.value = convert.toFrequency(value)
def __getattr__(self, attr):
if attr == 'frequency':
return Latency(self)
raise AttributeError, "Frequency object has no attribute '%s'" % attr
- # convert frequency to ticks per period
- def ini_str(self):
- return self.period.ini_str()
-
-# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz).
-# We can't inherit from Frequency because we don't want it to be directly
-# assignable to a regular Frequency parameter.
-class RootClock(ParamValue):
- cxx_type = 'Tick'
- cxx_predecls = ['#include "sim/host.hh"']
- swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
- '%import "sim/host.hh"']
- def __init__(self, value):
- self.value = 1 / getLatency(value)
-
- def __getattr__(self, attr):
- if attr == 'frequency':
- return Frequency(self)
- if attr in ('latency', 'period'):
- return Latency(self)
- raise AttributeError, "Frequency object has no attribute '%s'" % attr
-
+ # convert latency to ticks
def ini_str(self):
- return str(tick_check(self.value))
+ if self.ticks or self.value == 0:
+ return '%d' % self.value
+ else:
+ return '%d' % (ticks.fromSeconds(1.0 / self.value))
# A generic frequency and/or Latency value. Value is stored as a latency,
# but to avoid ambiguity this object does not support numeric ops (* or /).
swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
'%import "sim/host.hh"']
def __init__(self, value):
- self.value = getLatency(value)
+ if isinstance(value, (Latency, Clock)):
+ self.ticks = value.ticks
+ self.value = value.value
+ elif isinstance(value, Frequency):
+ self.ticks = value.ticks
+ self.value = 1.0 / value.value
+ elif value.endswith('t'):
+ self.ticks = True
+ self.value = int(value[:-1])
+ else:
+ self.ticks = False
+ self.value = convert.anyToLatency(value)
def __getattr__(self, attr):
if attr == 'frequency':
class NetworkBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(cls, value):
- val = convert.toNetworkBandwidth(value) / 8.0
+ # convert to bits per second
+ val = convert.toNetworkBandwidth(value)
return super(cls, NetworkBandwidth).__new__(cls, val)
def __str__(self):
return str(self.val)
def ini_str(self):
- return '%f' % (ticks_per_sec / float(self))
+ # convert to seconds per byte
+ value = 8.0 / float(self)
+ # convert to ticks per byte
+ return '%f' % (ticks.fromSeconds(value))
class MemoryBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(self, value):
+ # we want the number of ticks per byte of data
val = convert.toMemoryBandwidth(value)
return super(cls, MemoryBandwidth).__new__(cls, val)
return str(self.val)
def ini_str(self):
- return '%f' % (ticks_per_sec / float(self))
+ # convert to seconds per byte
+ value = 1.0 / float(self)
+ # convert to ticks per byte
+ return '%f' % (ticks.fromSeconds(value))
#
# "Constants"... handy aliases for various values.
'Counter', 'Addr', 'Tick', 'Percent',
'TcpPort', 'UdpPort', 'EthernetAddr',
'MemorySize', 'MemorySize32',
- 'Latency', 'Frequency', 'RootClock', 'Clock',
+ 'Latency', 'Frequency', 'Clock',
'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'TickRange',
'MaxAddr', 'MaxTick', 'AllMemory',
--- /dev/null
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import sys
+
+import convert
+import internal
+
+tps = 1.0e12 # default to 1 THz (1 Tick == 1 ps)
+tps_fixed = False # once set to true, can't be changed
+
+# fix the global frequency and tell C++ about it
+def fixGlobalFrequency():
+ global tps, tps_fixed
+ if not tps_fixed:
+ tps_fixed = True
+ internal.core.setClockFrequency(int(tps))
+ print "Global frequency set at %d ticks per second" % int(tps)
+
+def setGlobalFrequency(ticksPerSecond):
+ global tps, tps_fixed
+
+ if tps_fixed:
+ raise AttributeError, \
+ "Global frequency already fixed at %f ticks/s." % tps
+
+ if isinstance(ticksPerSecond, (int, long)):
+ tps = ticksPerSecond
+ elif isinstance(ticksPerSecond, float):
+ tps = ticksPerSecond
+ elif isinstance(ticksPerSecond, str):
+ tps = round(convert.anyToFrequency(ticksPerSecond))
+ else:
+ raise TypeError, \
+ "wrong type '%s' for ticksPerSecond" % type(ticksPerSecond)
+
+# how big does a rounding error need to be before we warn about it?
+frequency_tolerance = 0.001 # 0.1%
+
+def fromSeconds(value):
+ if not isinstance(value, float):
+ raise TypeError, "can't convert '%s' to type tick" % type(value)
+
+ # once someone needs to convert to seconds, the global frequency
+ # had better be fixed
+ if not tps_fixed:
+ raise AttributeError, \
+ "In order to do conversions, the global frequency must be fixed"
+
+ if value == 0:
+ return 0
+
+ # convert the value from time to ticks
+ value *= tps
+
+ int_value = int(round(value))
+ err = (value - int_value) / value
+ if err > frequency_tolerance:
+ print >>sys.stderr, "Warning: rounding error > tolerance"
+ print >>sys.stderr, " %f rounded to %d" % (value, int_value)
+ return int_value
+
+__all__ = [ 'setGlobalFrequency', 'fixGlobalFrequency', 'fromSeconds',
+ 'frequency_tolerance' ]
extern const char *compileDate;
%}
+%include "stdint.i"
%include "std_string.i"
+%include "sim/host.hh"
void setOutputDir(const std::string &dir);
+void setOutputFile(const std::string &file);
void loadIniFile(PyObject *);
void SimStartup();
void doExitCleanup();
char *compileDate;
+void setClockFrequency(Tick ticksPerSecond);
+
+%immutable curTick;
+Tick curTick;
+
%wrapper %{
// fix up module name to reflect the fact that it's inside the m5 package
#undef SWIG_name
CountedDrainEvent *createCountedDrain();
void cleanupCountedDrain(Event *drain_event);
-%immutable curTick;
-Tick curTick;
-
// minimal definition of SimExitEvent interface to wrap
class SimLoopExitEvent {
public:
SimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
void exitSimLoop(const std::string &message, int exit_code);
-Tick curTick;
-
%wrapper %{
// fix up module name to reflect the fact that it's inside the m5 package
#undef SWIG_name
#include "sim/builder.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "base/callback.hh"
#include "base/output.hh"
+#include "sim/core.hh"
using namespace std;
+Tick curTick = 0;
+
+namespace Clock {
+/// The simulated frequency of curTick. (In ticks per second)
+Tick Frequency;
+
+namespace Float {
+double s;
+double ms;
+double us;
+double ns;
+double ps;
+
+double Hz;
+double kHz;
+double MHz;
+double GHZ;
+/* namespace Float */ }
+
+namespace Int {
+Tick s;
+Tick ms;
+Tick us;
+Tick ns;
+Tick ps;
+/* namespace Float */ }
+
+/* namespace Clock */ }
+
+void
+setClockFrequency(Tick ticksPerSecond)
+{
+ using namespace Clock;
+ Frequency = ticksPerSecond;
+ Float::s = static_cast<double>(Frequency);
+ Float::ms = Float::s / 1.0e3;
+ Float::us = Float::s / 1.0e6;
+ Float::ns = Float::s / 1.0e9;
+ Float::ps = Float::s / 1.0e12;
+
+ Float::Hz = 1.0 / Float::s;
+ Float::kHz = 1.0 / Float::ms;
+ Float::MHz = 1.0 / Float::us;
+ Float::GHZ = 1.0 / Float::ns;
+
+ Int::s = Frequency;
+ Int::ms = Int::s / 1000;
+ Int::us = Int::ms / 1000;
+ Int::ns = Int::us / 1000;
+ Int::ps = Int::ns / 1000;
+
+}
+
void
setOutputDir(const string &dir)
{
simout.setDirectory(dir);
}
+ostream *outputStream;
+ostream *configStream;
+
+void
+setOutputFile(const string &file)
+{
+ outputStream = simout.find(file);
+}
+
/**
* Queue of C++ callbacks to invoke on simulator exit.
*/
cout.flush();
}
+
* Steve Reinhardt
*/
-#include <Python.h>
+#ifndef __SIM_CORE_HH__
+#define __SIM_CORE_HH__
+
#include <string>
-#include "base/callback.hh"
+#include "sim/host.hh"
+
+/// The universal simulation clock.
+extern Tick curTick;
+const Tick retryTime = 1000;
+
+namespace Clock {
+/// The simulated frequency of curTick.
+extern Tick Frequency;
+
+namespace Float {
+extern double s;
+extern double ms;
+extern double us;
+extern double ns;
+extern double ps;
+
+extern double Hz;
+extern double kHz;
+extern double MHz;
+extern double GHZ;
+/* namespace Float */ }
+namespace Int {
+extern Tick s;
+extern Tick ms;
+extern Tick us;
+extern Tick ns;
+extern Tick ps;
+/* namespace Int */ }
+/* namespace Clock */ }
+
+void setClockFrequency(Tick ticksPerSecond);
+
+/// Output stream for simulator messages (e.g., cprintf()). Also used
+/// as default stream for tracing and DPRINTF() messages (unless
+/// overridden with trace:file option).
+extern std::ostream *outputStream;
+void setOutputFile(const std::string &file);
void setOutputDir(const std::string &dir);
+/// Output stream for configuration dump.
+extern std::ostream *configStream;
+
+struct Callback;
void registerExitCallback(Callback *callback);
void doExitCleanup();
+
+#endif /* __SIM_CORE_HH__ */
#include "sim/eventq.hh"
#include "base/trace.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "python/swig/init.hh"
#include "sim/async.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
using namespace std;
#include "arch/sparc/solaris/process.hh"
#elif THE_ISA == MIPS_ISA
#include "arch/mips/linux/process.hh"
+#elif THE_ISA == X86_ISA
+#include "arch/x86/linux/process.hh"
#else
#error "THE_ISA not set"
#endif
default:
fatal("Unknown/unsupported operating system.");
}
+#elif THE_ISA == X86_ISA
+ if (objFile->getArch() != ObjectFile::X86)
+ fatal("Object file architecture does not match compiled ISA (x86).");
+ switch (objFile->getOpSys()) {
+ case ObjectFile::Linux:
+ process = new X86LinuxProcess(nm, objFile, system,
+ stdin_fd, stdout_fd, stderr_fd,
+ argv, envp, cwd,
+ _uid, _euid, _gid,
+ _egid, _pid, _ppid);
+ break;
+ default:
+ fatal("Unknown/unsupported operating system.");
+ }
#elif THE_ISA == MIPS_ISA
if (objFile->getArch() != ObjectFile::Mips)
fatal("Object file architecture does not match compiled ISA (MIPS).");
#include <vector>
#include "base/misc.hh"
-#include "base/output.hh"
#include "sim/builder.hh"
-#include "sim/host.hh"
-#include "sim/sim_events.hh"
-#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
-#include "sim/root.hh"
-
-using namespace std;
-
-Tick curTick = 0;
-ostream *outputStream;
-ostream *configStream;
-
-/// The simulated frequency of curTick. (This is only here for a short time)
-Tick ticksPerSecond;
-
-namespace Clock {
-/// The simulated frequency of curTick. (In ticks per second)
-Tick Frequency;
-
-namespace Float {
-double s;
-double ms;
-double us;
-double ns;
-double ps;
-
-double Hz;
-double kHz;
-double MHz;
-double GHZ;
-/* namespace Float */ }
-
-namespace Int {
-Tick s;
-Tick ms;
-Tick us;
-Tick ns;
-Tick ps;
-/* namespace Float */ }
-
-/* namespace Clock */ }
-
// Dummy Object
-class Root : public SimObject
+struct Root : public SimObject
{
- private:
- Tick max_tick;
- Tick progress_interval;
-
- public:
- Root(const std::string &name, Tick maxtick, Tick pi)
- : SimObject(name), max_tick(maxtick), progress_interval(pi)
- {}
-
- virtual void startup();
+ Root(const std::string &name) : SimObject(name) {}
};
-void
-Root::startup()
-{
- if (max_tick != 0)
- schedExitSimLoop("reached maximum cycle count", curTick + max_tick);
-
- if (progress_interval != 0)
- new ProgressEvent(&mainEventQueue, progress_interval);
-}
-
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root)
- Param<Tick> clock;
- Param<Tick> max_tick;
- Param<Tick> progress_interval;
- Param<string> output_file;
+ Param<int> dummy; // needed below
END_DECLARE_SIM_OBJECT_PARAMS(Root)
BEGIN_INIT_SIM_OBJECT_PARAMS(Root)
- INIT_PARAM(clock, "tick frequency"),
- INIT_PARAM(max_tick, "maximum simulation time"),
- INIT_PARAM(progress_interval, "print a progress message"),
- INIT_PARAM(output_file, "file to dump simulator output to")
+ INIT_PARAM(dummy, "") // All SimObjects must have params
END_INIT_SIM_OBJECT_PARAMS(Root)
created = true;
- outputStream = simout.find(output_file);
- Root *root = new Root(getInstanceName(), max_tick, progress_interval);
-
- using namespace Clock;
- Frequency = clock;
- Float::s = static_cast<double>(Frequency);
- Float::ms = Float::s / 1.0e3;
- Float::us = Float::s / 1.0e6;
- Float::ns = Float::s / 1.0e9;
- Float::ps = Float::s / 1.0e12;
-
- Float::Hz = 1.0 / Float::s;
- Float::kHz = 1.0 / Float::ms;
- Float::MHz = 1.0 / Float::us;
- Float::GHZ = 1.0 / Float::ns;
-
- Int::s = Frequency;
- Int::ms = Int::s / 1000;
- Int::us = Int::ms / 1000;
- Int::ns = Int::us / 1000;
- Int::ps = Int::ns / 1000;
-
- return root;
+ return new Root(getInstanceName());
}
REGISTER_SIM_OBJECT("Root", Root)
{
return "check swap";
}
-
-//
-// handle progress event: print message and reschedule
-//
-void
-ProgressEvent::process()
-{
- DPRINTFN("ProgressEvent\n");
- // reschedule for next interval
- schedule(curTick + interval);
-}
-
-
-const char *
-ProgressEvent::description()
-{
- return "progress message";
-}
virtual const char *description();
};
-//
-// Progress event: print out cycle every so often so we know we're
-// making forward progress.
-//
-class ProgressEvent : public Event
-{
- protected:
- Tick interval;
-
- public:
- ProgressEvent(EventQueue *q, Tick ival)
- : Event(q), interval(ival)
- { schedule(curTick + interval); }
-
- void process(); // process event
-
- virtual const char *description();
-};
-
#endif // __SIM_SIM_EVENTS_HH__
system.cpu = cpu
cpu.connectMemPorts(system.membus)
-root = Root(clock = '2GHz', system = system)
+root = Root(system=system)
+
+m5.ticks.setGlobalFrequency('2GHz')
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
for c in cpus:
c.connectMemPorts(system.membus)
-root = Root(clock = '2GHz', system = system)
+root = Root(system=system)
+
+m5.ticks.setGlobalFrequency('2GHz')
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
system.cpu = cpu
cpu.connectMemPorts(system.membus)
-root = Root(clock = '2GHz', system = system)
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('2GHz')
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
for c in cpus:
c.connectMemPorts(system.membus)
-root = Root(clock = '2GHz', system = system)
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('2GHz')
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
system.cpu = cpu
cpu.connectMemPorts(system.membus)
-root = Root(clock = '2GHz', system = system)
+root = Root(system=system)
+m5.ticks.setGlobalFrequency('2GHz')
output_file=cout
progress_interval=0
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
[system]
type=System
children=cpu membus physmem
egid=100
env=
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
output=cout
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
input=cin
output=cout
env=
width=64
responder_set=false
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 12030516 # Number of BTB hits
-global.BPredUnit.BTBLookups 15440177 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1230 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 2016046 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 13150093 # Number of conditional branches predicted
-global.BPredUnit.lookups 17791196 # Number of BP lookups
-global.BPredUnit.usedRAS 1688779 # Number of times the RAS was used to get a target.
-host_inst_rate 79686 # Simulator instruction rate (inst/s)
-host_mem_usage 157864 # Number of bytes of host memory used
-host_seconds 1056.39 # Real time elapsed on the host
-host_tick_rate 100832 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 10465878 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 3573806 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 29942981 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 9492949 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 11848811 # Number of BTB hits
+global.BPredUnit.BTBLookups 15227898 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1227 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 2015952 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 12943595 # Number of conditional branches predicted
+global.BPredUnit.lookups 17560137 # Number of BP lookups
+global.BPredUnit.usedRAS 1685355 # Number of times the RAS was used to get a target.
+host_inst_rate 110871 # Simulator instruction rate (inst/s)
+host_mem_usage 184176 # Number of bytes of host memory used
+host_seconds 759.26 # Real time elapsed on the host
+host_tick_rate 138735 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 9867030 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 3328836 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 29553768 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 9396457 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 84179641 # Number of instructions simulated
-sim_seconds 0.000107 # Number of seconds simulated
-sim_ticks 106518101 # Number of ticks simulated
-system.cpu.commit.COM:branches 10240671 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3286550 # number cycles where commit BW limit reached
+sim_insts 84179709 # Number of instructions simulated
+sim_seconds 0.000105 # Number of seconds simulated
+sim_ticks 105335101 # Number of ticks simulated
+system.cpu.commit.COM:branches 10240685 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 3300349 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 66541371
+system.cpu.commit.COM:committed_per_cycle.samples 65617496
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 32590645 4897.80%
- 1 14052557 2111.85%
- 2 7925597 1191.08%
- 3 3833922 576.17%
- 4 2055997 308.98%
- 5 1406670 211.40%
- 6 778313 116.97%
- 7 611120 91.84%
- 8 3286550 493.91%
+ 0 32041205 4883.03%
+ 1 13628356 2076.94%
+ 2 7878182 1200.62%
+ 3 3859920 588.25%
+ 4 2040157 310.92%
+ 5 1456623 221.99%
+ 6 796888 121.44%
+ 7 615816 93.85%
+ 8 3300349 502.97%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
-system.cpu.commit.COM:count 91902973 # Number of instructions committed
-system.cpu.commit.COM:loads 20034401 # Number of loads committed
+system.cpu.commit.COM:count 91903055 # Number of instructions committed
+system.cpu.commit.COM:loads 20034413 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
-system.cpu.commit.COM:refs 26537088 # Number of memory references committed
+system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2003600 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 91902973 # The number of committed instructions
+system.cpu.commit.branchMispredicts 2003468 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 40960562 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 84179641 # Number of Instructions Simulated
-system.cpu.committedInsts_total 84179641 # Number of Instructions Simulated
-system.cpu.cpi 1.265367 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.265367 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 23044516 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5485.308046 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4904.691383 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 23043646 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4772218 # number of ReadReq miss cycles
+system.cpu.commit.commitSquashedInsts 39205061 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 84179709 # Number of Instructions Simulated
+system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
+system.cpu.cpi 1.251312 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.251312 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 23022109 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5495.207331 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4910.485944 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23021236 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4797316 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 870 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 371 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2447441 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 873 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 375 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2445422 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 499 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses 6501095 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4881.036474 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.310702 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6495173 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 28905498 # number of WriteReq miss cycles
+system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 4880.722363 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.932720 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6495178 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 28918280 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5922 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 4184 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 7957104 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses 5925 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 4186 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 7962764 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1738 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3119.926690 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13204.657577 # Average number of references to valid blocks.
+system.cpu.dcache.avg_blocked_cycles_no_targets 3125.260571 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13194.641931 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 873 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 875 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 2723696 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 2734603 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29545611 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4958.438751 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4651.115333 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29538819 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 33677716 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses 29523212 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 4959.634598 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29516414 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 33715596 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 6792 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 4555 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10404545 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 6798 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 4561 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 10408186 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 29545611 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4958.438751 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4651.115333 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 29523212 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 4959.634598 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29538819 # number of overall hits
-system.cpu.dcache.overall_miss_latency 33677716 # number of overall miss cycles
+system.cpu.dcache.overall_hits 29516414 # number of overall hits
+system.cpu.dcache.overall_miss_latency 33715596 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 6792 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 4555 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10404545 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 6798 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 4561 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 10408186 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 158 # number of replacements
system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1401.371234 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29538819 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1400.647488 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29516414 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 105 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 2237449 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12651 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 2840694 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 147924684 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 36686871 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 27530511 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 6274304 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 45170 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 86541 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 17791196 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 17777552 # Number of cache lines fetched
-system.cpu.fetch.Cycles 46222210 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 487538 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 152510640 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2057778 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.244332 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 17777552 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 13719295 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.094475 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:BlockedCycles 2047370 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12661 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 2829477 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 146297095 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 36266329 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 27223403 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 6075840 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 45354 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 80395 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 17560137 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 17576948 # Number of cache lines fetched
+system.cpu.fetch.Cycles 45711428 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 479088 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 150837354 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2061309 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.244934 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 17576948 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 13534166 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.103924 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 72815676
+system.cpu.fetch.rateDist.samples 71693337
system.cpu.fetch.rateDist.min_value 0
- 0 44371798 6093.72%
- 1 2823722 387.79%
- 2 2124290 291.74%
- 3 3251818 446.58%
- 4 4141832 568.81%
- 5 1395626 191.67%
- 6 1928347 264.83%
- 7 1658600 227.78%
- 8 11119643 1527.09%
+ 0 43559639 6075.83%
+ 1 2788432 388.94%
+ 2 2133609 297.60%
+ 3 3200202 446.37%
+ 4 4098889 571.73%
+ 5 1363717 190.22%
+ 6 1885995 263.06%
+ 7 1651845 230.40%
+ 8 11011009 1535.85%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 17777552 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3389.584594 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2497.747914 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 17763934 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 46159363 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000766 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 13618 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 3550 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 25147326 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000566 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10068 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 3002.121212 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1764.395511 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 17576948 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3407.568545 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2506.978423 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 17563424 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 46083957 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000769 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 13524 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25212682 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10057 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets 3513.269231 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1746.387988 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 33 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 26 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 99070 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 91345 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 17777552 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3389.584594 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2497.747914 # average overall mshr miss latency
-system.cpu.icache.demand_hits 17763934 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 46159363 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000766 # miss rate for demand accesses
-system.cpu.icache.demand_misses 13618 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 3550 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 25147326 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000566 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10068 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 17576948 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3407.568545 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
+system.cpu.icache.demand_hits 17563424 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 46083957 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000769 # miss rate for demand accesses
+system.cpu.icache.demand_misses 13524 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 3467 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25212682 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10057 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 17777552 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3389.584594 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2497.747914 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 17763934 # number of overall hits
-system.cpu.icache.overall_miss_latency 46159363 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000766 # miss rate for overall accesses
-system.cpu.icache.overall_misses 13618 # number of overall misses
-system.cpu.icache.overall_mshr_hits 3550 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 25147326 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000566 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10068 # number of overall MSHR misses
+system.cpu.icache.overall_accesses 17576948 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3407.568545 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 17563424 # number of overall hits
+system.cpu.icache.overall_miss_latency 46083957 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000769 # miss rate for overall accesses
+system.cpu.icache.overall_misses 13524 # number of overall misses
+system.cpu.icache.overall_mshr_hits 3467 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25212682 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10057 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 8155 # number of replacements
-system.cpu.icache.sampled_refs 10068 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8145 # number of replacements
+system.cpu.icache.sampled_refs 10057 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1487.917031 # Cycle average of tags in use
-system.cpu.icache.total_refs 17763934 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1487.085502 # Cycle average of tags in use
+system.cpu.icache.total_refs 17563424 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 33702426 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12615755 # Number of branches executed
-system.cpu.iew.EXEC:nop 11674396 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.372220 # Inst execution rate
-system.cpu.iew.EXEC:refs 31504897 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7134544 # Number of stores executed
+system.cpu.idleCycles 33641765 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12581618 # Number of branches executed
+system.cpu.iew.EXEC:nop 11617565 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.388001 # Inst execution rate
+system.cpu.iew.EXEC:refs 31473535 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7134398 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 88896181 # num instructions consuming a value
-system.cpu.iew.WB:count 98303270 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.728803 # average fanout of values written-back
+system.cpu.iew.WB:consumers 88408054 # num instructions consuming a value
+system.cpu.iew.WB:count 97920299 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.731090 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 64787760 # num instructions producing a value
-system.cpu.iew.WB:rate 1.350029 # insts written-back per cycle
-system.cpu.iew.WB:sent 98915294 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2149664 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 135882 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 29942981 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 64634219 # num instructions producing a value
+system.cpu.iew.WB:rate 1.365821 # insts written-back per cycle
+system.cpu.iew.WB:sent 98494929 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2154192 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 104376 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 29553768 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 2170747 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 9492949 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 132862510 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 24370353 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2140113 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 99919134 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 28304 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 2191495 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 9396457 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 131107086 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24339137 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2193063 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 99510422 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 16363 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 875 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 6274304 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 51812 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 9931 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 36041 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 935951 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 2991 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 879 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 6075840 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 34734 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 9915 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 36009 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 941599 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 3004 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 19407 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9931 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 9908580 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 2990262 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 19407 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 196546 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1953118 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.790285 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.790285 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 102059247 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 23070 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9915 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 9519355 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 2893762 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 23070 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 196104 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1958088 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.799161 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.799161 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 101703485 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 7 0.00% # Type of FU issued
- IntAlu 62946758 61.68% # Type of FU issued
- IntMult 472934 0.46% # Type of FU issued
+ IntAlu 62578225 61.53% # Type of FU issued
+ IntMult 472394 0.46% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2777268 2.72% # Type of FU issued
- FloatCmp 115533 0.11% # Type of FU issued
- FloatCvt 2374854 2.33% # Type of FU issued
- FloatMult 302376 0.30% # Type of FU issued
- FloatDiv 755012 0.74% # Type of FU issued
+ FloatAdd 2776755 2.73% # Type of FU issued
+ FloatCmp 115486 0.11% # Type of FU issued
+ FloatCvt 2376016 2.34% # Type of FU issued
+ FloatMult 302348 0.30% # Type of FU issued
+ FloatDiv 754954 0.74% # Type of FU issued
FloatSqrt 321 0.00% # Type of FU issued
- MemRead 24997637 24.49% # Type of FU issued
- MemWrite 7316547 7.17% # Type of FU issued
+ MemRead 25019338 24.60% # Type of FU issued
+ MemWrite 7307641 7.19% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1380880 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013530 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1392706 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013694 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
- (null) 0 0.00% # attempts to use FU when none available
- IntAlu 203697 14.75% # attempts to use FU when none available
- IntMult 0 0.00% # attempts to use FU when none available
- IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 1158 0.08% # attempts to use FU when none available
- FloatCmp 74 0.01% # attempts to use FU when none available
- FloatCvt 3812 0.28% # attempts to use FU when none available
- FloatMult 2483 0.18% # attempts to use FU when none available
- FloatDiv 669323 48.47% # attempts to use FU when none available
- FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 447537 32.41% # attempts to use FU when none available
- MemWrite 52796 3.82% # attempts to use FU when none available
- IprAccess 0 0.00% # attempts to use FU when none available
- InstPrefetch 0 0.00% # attempts to use FU when none available
+(null) 0 0.00% # attempts to use FU when none available
+IntAlu 193189 13.87% # attempts to use FU when none available
+IntMult 0 0.00% # attempts to use FU when none available
+IntDiv 0 0.00% # attempts to use FU when none available
+FloatAdd 1883 0.14% # attempts to use FU when none available
+FloatCmp 96 0.01% # attempts to use FU when none available
+FloatCvt 2836 0.20% # attempts to use FU when none available
+FloatMult 2464 0.18% # attempts to use FU when none available
+FloatDiv 659899 47.38% # attempts to use FU when none available
+FloatSqrt 0 0.00% # attempts to use FU when none available
+MemRead 465101 33.40% # attempts to use FU when none available
+MemWrite 67238 4.83% # attempts to use FU when none available
+IprAccess 0 0.00% # attempts to use FU when none available
+InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 72815676
+system.cpu.iq.ISSUE:issued_per_cycle.samples 71693337
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 28801052 3955.34%
- 1 15640626 2147.98%
- 2 12881779 1769.09%
- 3 7065095 970.27%
- 4 4538706 623.31%
- 5 2449165 336.35%
- 6 1089108 149.57%
- 7 276679 38.00%
- 8 73466 10.09%
+ 0 27977053 3902.32%
+ 1 15408153 2149.18%
+ 2 12854527 1792.99%
+ 3 7056557 984.27%
+ 4 4494209 626.87%
+ 5 2427532 338.60%
+ 6 1097338 153.06%
+ 7 305661 42.63%
+ 8 72307 10.09%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.401611 # Inst issue rate
-system.cpu.iq.iqInstsAdded 121187678 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 102059247 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 1.418590 # Inst issue rate
+system.cpu.iq.iqInstsAdded 119489085 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 101703485 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 36185843 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 120363 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 34413373 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 132312 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 30311914 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 12304 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3854.841711 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2070.473487 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7231 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19555612 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.412305 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 5073 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 10503512 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412305 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 5073 # number of ReadReq MSHR misses
+system.cpu.iq.iqSquashedOperandsExamined 28441004 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 12293 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 3855.809345 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2071.040418 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 19556665 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.412593 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 5072 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 10504317 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412593 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 5072 # number of ReadReq MSHR misses
system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.446087 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.444401 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12304 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3854.841711 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2070.473487 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7231 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 19555612 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.412305 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5073 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 12293 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 3855.809345 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 19556665 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.412593 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5072 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 10503512 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.412305 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5073 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 10504317 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.412593 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5072 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 12409 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3854.841711 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2070.473487 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7336 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 19555612 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.408816 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5073 # number of overall misses
+system.cpu.l2cache.overall_accesses 12398 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 3855.809345 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 7326 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 19556665 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.409098 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5072 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 10503512 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.408816 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5073 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 10504317 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.409098 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5072 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 5073 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 5072 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3263.707979 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7336 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3261.872945 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7326 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 72815676 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 912182 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 68427307 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 427437 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 37674875 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 794086 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 131 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 185014418 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 143398786 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 105292951 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 26609827 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 6274304 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1283784 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 36865644 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 60704 # count of cycles rename stalled for serializing inst
+system.cpu.numCycles 71693337 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 812700 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 369396 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 37208342 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 772307 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 122 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 182866276 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 141908898 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 104156212 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 26334995 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 6075840 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1200845 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 35728851 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 60615 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 3136689 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 2896644 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed
-system.cpu.timesIdled 10449 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 10380 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
m5.AddToPath('../configs/common')
from cpu2000 import twolf
+import os
workload = twolf('alpha', 'tru64', 'smred')
root.system.cpu.workload = workload.makeLiveProcess()
+cwd = root.system.cpu.workload.cwd
+
+#Remove two files who's presence or absence affects execution
+sav_file = os.path.join(cwd, workload.input_set + '.sav')
+sv2_file = os.path.join(cwd, workload.input_set + '.sv2')
+os.unlink(sav_file)
+os.unlink(sv2_file)
--- /dev/null
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=insttest
+cwd=
+egid=100
+env=
+euid=100
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
--- /dev/null
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
+input=cin
+output=cout
+env=
+cwd=
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate 104057 # Simulator instruction rate (inst/s)
+host_mem_usage 179368 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
+host_tick_rate 103746 # Simulator tick rate (ticks/s)
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 10367 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 10366 # Number of ticks simulated
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.numCycles 10367 # number of cpu cycles simulated
+system.cpu.num_insts 10367 # Number of instructions executed
+system.cpu.num_refs 2607 # Number of memory references
+system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
+
+---------- End Simulation Statistics ----------
--- /dev/null
+warn: More than two loadable segments in ELF object.
+warn: Ignoring segment @ 0x0 length 0x0.
+0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
+warn: Entering event queue @ 0. Starting simulation...
--- /dev/null
+Begining test of difficult SPARC instructions...
+LDSTUB: Passed
+SWAP: Passed
+CAS FAIL: Passed
+CAS WORK: Passed
+CASX FAIL: Passed
+CASX WORK: Passed
+LDTX: Passed
+LDTW: Passed
+Done
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Mar 6 2007 15:43:35
+M5 started Tue Mar 6 15:52:39 2007
+M5 executing on zeep
+command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
+Exiting @ tick 10366 because target called exit()
--- /dev/null
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+
+root.system.cpu.workload = LiveProcess(cmd = 'insttest',
+ executable = binpath('insttest'))
/*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
bool SparcTraceChild::update(int pid)
{
- static const int stackBias = 2047;
memcpy(&oldregs, &theregs, sizeof(regs));
memcpy(&oldfpregs, &thefpregs, sizeof(fpu));
memcpy(oldLocals, locals, 8 * sizeof(uint64_t));
cerr << "Update failed" << endl;
return false;
}
- uint64_t StackPointer = getRegVal(O6);
+ uint64_t StackPointer = getSP();
+ const int stackBias = (StackPointer % 1) ? 2047 : 0;
for(unsigned int x = 0; x < 8; x++)
{
locals[x] = ptrace(PTRACE_PEEKTEXT, pid,
regDiffSinceUpdate[x] = false;
}
+int SparcTraceChild::getTargets(uint32_t inst, uint64_t pc, uint64_t npc,
+ uint64_t &target1, uint64_t &target2)
+{
+ //We can identify the instruction categories we care about using the top
+ //10 bits of the instruction, excluding the annul bit in the 3rd most
+ //significant bit position and the condition field. We'll call these
+ //bits the "sig" for signature.
+ uint32_t sig = (inst >> 22) & 0x307;
+ uint32_t cond = (inst >> 25) & 0xf;
+ bool annul = (inst & (1 << 29));
+
+ //Check if it's a ba...
+ bool ba = (cond == 0x8) &&
+ (sig == 0x1 || sig == 0x2 || sig == 0x5 || sig == 0x6);
+ //or a bn...
+ bool bn = (cond == 0x0) &&
+ (sig == 0x1 || sig == 0x2 || sig == 0x5 || sig == 0x6);
+ //or a bcc
+ bool bcc = (cond & 0x7) &&
+ (sig == 0x1 || sig == 0x2 || sig == 0x3 || sig == 0x5 || sig == 0x6);
+
+ if(annul)
+ {
+ if(bcc)
+ {
+ target1 = npc;
+ target2 = npc + 4;
+ return 2;
+ }
+ else if(ba)
+ {
+ //This branches immediately to the effective address of the branch
+ //which we'll have to calculate.
+ uint64_t disp = 0;
+ int64_t extender = 0;
+ //Figure out how big the displacement field is, and grab the bits
+ if(sig == 0x1 || sig == 0x5)
+ {
+ disp = inst & ((1 << 19) - 1);
+ extender = 1 << 18;
+ }
+ else
+ {
+ disp = inst & ((1 << 22) - 1);
+ extender = 1 << 21;
+ }
+ //This does sign extension, believe it or not.
+ disp = (disp ^ extender) - extender;
+ //Multiply the displacement by 4. I'm assuming the compiler is
+ //smart enough to turn this into a shift.
+ disp *= 4;
+ target1 = pc + disp;
+ }
+ else if(bn)
+ target1 = npc + 4;
+ else
+ target1 = npc;
+ return 1;
+ }
+ else
+ {
+ target1 = npc;
+ return 1;
+ }
+}
+
bool SparcTraceChild::step()
{
+ //Increment the count of the number of instructions executed
+ instructions++;
//Two important considerations are that the address of the instruction
//being breakpointed should be word (64bit) aligned, and that both the
//next instruction and the instruction after that need to be breakpointed
* Useful constants
*/
const static uint64_t breakInst = 0x91d02001;
+ const static uint64_t lowBreakInst = breakInst;
+ const static uint64_t highBreakInst = breakInst << 32;
const static uint64_t breakWord = breakInst | (breakInst << 32);
const static uint64_t lowMask = 0xFFFFFFFFULL;
const static uint64_t highMask = lowMask << 32;
bool unalignedNPC = nextPC & 7;
uint64_t alignedNPC = nextPC & (~7);
- /*
- * Store the original contents of the child process's memory
- */
- originalInst = ptrace(PTRACE_PEEKTEXT, pid, alignedNPC, 0);
- //Save a ptrace call if we can
- if(unalignedNPC)
- {
- originalAnnulInst = ptrace(PTRACE_PEEKTEXT, pid, alignedNPC+8, 0);
- }
+ //Get the current instruction
+ uint64_t curInst = ptrace(PTRACE_PEEKTEXT, pid, alignedPC);
+ curInst = unalignedPC ? (curInst & 0xffffffffULL) : (curInst >> 32);
- /*
- * Prepare breakpointed copies of child processes memory
- */
- uint64_t newInst, newAnnulInst;
- //If the current instruction is in the same word as the npc
- if(alignedPC == alignedNPC)
- {
- //Make sure we only replace the other part
- if(unalignedPC)
- newInst = (originalInst & lowMask) | (breakWord & highMask);
- else
- newInst = (originalInst & highMask) | (breakWord & lowMask);
- }
- else
- {
- //otherwise replace the whole thing
- newInst = breakWord;
- }
- //If the current instruction is in the same word as the word after
- //the npc
- if(alignedPC == alignedNPC+8)
- {
- //Make sure we only replace the other part
- if(unalignedPC)
- newAnnulInst = (originalAnnulInst & lowMask) | (breakWord & highMask);
- else
- newAnnulInst = (originalAnnulInst & highMask) | (breakWord & lowMask);
- }
- else
- {
- //otherwise replace the whole thing
- newAnnulInst = breakWord;
- }
+ uint64_t bp1, bp2;
+ int numTargets = getTargets(curInst, currentPC, nextPC, bp1, bp2);
+ assert(numTargets == 1 || numTargets == 2);
+
+ bool unalignedBp1 = bp1 & 7;
+ uint64_t alignedBp1 = bp1 & (~7);
+ bool unalignedBp2 = bp2 & 7;
+ uint64_t alignedBp2 = bp2 & (~7);
+ uint64_t origBp1, origBp2;
/*
- * Stuff the breakpoint instructions into the child's address space.
+ * Set the first breakpoint
*/
- //Replace the word at npc
- if(ptrace(PTRACE_POKETEXT, pid, alignedNPC, newInst) != 0)
+ origBp1 = ptrace(PTRACE_PEEKTEXT, pid, alignedBp1, 0);
+ uint64_t newBp1 = origBp1;
+ newBp1 &= unalignedBp1 ? highMask : lowMask;
+ newBp1 |= unalignedBp1 ? lowBreakInst : highBreakInst;
+ if(ptrace(PTRACE_POKETEXT, pid, alignedBp1, newBp1) != 0)
cerr << "Poke failed" << endl;
- //Replace the next word, if necessary
- if(unalignedNPC)
+ /*
+ * Set the second breakpoint if necessary
+ */
+ if(numTargets == 2)
{
- if(ptrace(PTRACE_POKETEXT, pid, alignedNPC+8, newAnnulInst) != 0)
+ origBp2 = ptrace(PTRACE_PEEKTEXT, pid, alignedBp2, 0);
+ uint64_t newBp2 = origBp2;
+ newBp2 &= unalignedBp2 ? highMask : lowMask;
+ newBp2 |= unalignedBp2 ? lowBreakInst : highBreakInst;
+ if(ptrace(PTRACE_POKETEXT, pid, alignedBp2, newBp2) != 0)
cerr << "Poke failed" << endl;
}
update(pid);
/*
- * Put back the original contents of the childs address space
+ * Put back the original contents of the childs address space in the
+ * reverse order.
*/
- if(ptrace(PTRACE_POKETEXT, pid, alignedNPC, originalInst) != 0)
- cerr << "Repoke failed" << endl;
- if(unalignedNPC)
+ if(numTargets == 2)
{
- if(ptrace(PTRACE_POKETEXT, pid, alignedNPC+8, originalAnnulInst) != 0)
- cerr << "Repoke failed" << endl;
+ if(ptrace(PTRACE_POKETEXT, pid, alignedBp2, origBp2) != 0)
+ cerr << "Poke failed" << endl;
}
- return true;
+ if(ptrace(PTRACE_POKETEXT, pid, alignedBp1, origBp1) != 0)
+ cerr << "Poke failed" << endl;
}
int64_t SparcTraceChild::getRegVal(int num)
ostream & SparcTraceChild::outputStartState(ostream & os)
{
+ bool v8 = false;
uint64_t sp = getSP();
+ if(sp % 1)
+ {
+ os << "Detected a 64 bit executable.\n";
+ v8 = false;
+ }
+ else
+ {
+ os << "Detected a 32 bit executable.\n";
+ v8 = true;
+ }
uint64_t pc = getPC();
char obuf[1024];
sprintf(obuf, "Initial stack pointer = 0x%016llx\n", sp);
os << obuf;
sprintf(obuf, "Initial program counter = 0x%016llx\n", pc);
os << obuf;
- //Take out the stack bias
- sp += 2047;
+ if(!v8)
+ {
+ //Take out the stack bias
+ sp += 2047;
+ }
//Output the window save area
for(unsigned int x = 0; x < 16; x++)
{
uint64_t regspot = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
+ if(v8) regspot = regspot >> 32;
sprintf(obuf, "0x%016llx: Window save %d = 0x%016llx\n",
sp, x+1, regspot);
os << obuf;
- sp += 8;
+ sp += v8 ? 4 : 8;
}
//Output the argument count
uint64_t cargc = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
+ if(v8) cargc = cargc >> 32;
sprintf(obuf, "0x%016llx: Argc = 0x%016llx\n", sp, cargc);
os << obuf;
- sp += 8;
+ sp += v8 ? 4 : 8;
//Output argv pointers
int argCount = 0;
uint64_t cargv;
do
{
cargv = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
+ if(v8) cargv = cargv >> 32;
sprintf(obuf, "0x%016llx: argv[%d] = 0x%016llx\n",
sp, argCount++, cargv);
os << obuf;
- sp += 8;
+ sp += v8 ? 4 : 8;
} while(cargv);
//Output the envp pointers
int envCount = 0;
do
{
cenvp = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
+ if(v8) cenvp = cenvp >> 32;
sprintf(obuf, "0x%016llx: envp[%d] = 0x%016llx\n",
sp, envCount++, cenvp);
os << obuf;
- sp += 8;
+ sp += v8 ? 4 : 8;
} while(cenvp);
uint64_t auxType, auxVal;
do
{
auxType = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
- sp += 8;
+ if(v8) auxType = auxType >> 32;
+ sp += (v8 ? 4 : 8);
auxVal = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
- sp += 8;
+ if(v8) auxVal = auxVal >> 32;
+ sp += (v8 ? 4 : 8);
sprintf(obuf, "0x%016llx: Auxiliary vector = {0x%016llx, 0x%016llx}\n",
- sp - 16, auxType, auxVal);
+ sp - 8, auxType, auxVal);
os << obuf;
} while(auxType != 0 || auxVal != 0);
//Print out the argument strings, environment strings, and file name.
{
buf = ptrace(PTRACE_PEEKDATA, pid, sp, 0);
char * cbuf = (char *)&buf;
- for(int x = 0; x < sizeof(uint64_t); x++)
+ for(int x = 0; x < sizeof(uint32_t); x++)
{
if(cbuf[x])
current += cbuf[x];
currentStart = sp + x + 1;
}
}
- sp += 8;
+ sp += (v8 ? 4 : 8);
clearedInitialPadding = clearedInitialPadding || buf != 0;
} while(!clearedInitialPadding || buf != 0);
return os;
/*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
int64_t oldInputs[8];
bool regDiffSinceUpdate[numregs];
+ //This calculates where the pc might go after the current instruction.
+ //while this equals npc for most instructions, it doesn't for all of
+ //them. The return value is the number of actual potential targets.
+ int getTargets(uint32_t inst, uint64_t pc, uint64_t npc,
+ uint64_t &target1, uint64_t &target2);
+
protected:
bool update(int pid);
/*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
return 1;
}
}
- for(unsigned int x = startProgramArgs; x < argc; x++)
- args += argv[x];
- if(!child->startTracing(argv[startProgramArgs], args.c_str()))
+ /*for(unsigned int x = startProgramArgs; x < argc; x++)
+ {
+ cout << "Adding argument " << argv[x];
+ args += string(" ") + argv[x];
+ }*/
+ if(!child->startTracing(argv[startProgramArgs],
+ argv + startProgramArgs))
{
cerr << "Couldn't start target program" << endl;
return 1;
/*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
using namespace std;
-bool TraceChild::startTracing(const char * pathToFile, const char * arg)
+bool TraceChild::startTracing(const char * pathToFile, char * const argv[])
{
+ instructions = 0;
pid = fork();
if(pid == -1)
{
ptrace(PTRACE_TRACEME, 0, 0, 0);
//Start the program to trace
- execl(pathToFile, arg);
+ execv(pathToFile, argv);
//We should never get here, so this is an error!
return false;
{
cerr << "Program exited! Exit status is "
<< WEXITSTATUS(wait_val) << endl;
+ cerr << "Executed " << instructions
+ << " instructions." << endl;
tracing = false;
return false;
}
if(WCOREDUMP(wait_val))
cerr << "Program core dumped!" << endl;
tracing = false;
+ cerr << "Executed " << instructions
+ << " instructions." << endl;
return false;
}
if(WIFSTOPPED(wait_val) && WSTOPSIG(wait_val) != SIGTRAP)
cerr << "Program stopped by signal "
<< WSTOPSIG(wait_val) << endl;
tracing = false;
+ cerr << "Executed " << instructions
+ << " instructions." << endl;
return false;
}
return true;
/*
- * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2006-2007 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
{
protected:
int pid;
+ uint64_t instructions;
bool tracing;
public:
- TraceChild() : tracing(false)
+ TraceChild() : tracing(false), instructions(0)
{;}
- virtual bool startTracing(const char * pathToFile, const char * arg);
+ virtual bool startTracing(const char * pathToFile,
+ char * const argv[]);
virtual bool stopTracing();
virtual bool step();
virtual uint64_t getPC() = 0;
projects / gem5.git / commitdiff