soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index fc4ec27f2fb2af405b96478c15fd1798cc0c7299..dd59143f7e2908d58107c34ec768c7385432a6ff 100644 (file)
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -272,7 +272,7 @@ class UARTCrossover(UART):
     def __init__(self, **kwargs):
         assert kwargs.get("phy", None) == None
         UART.__init__(self, **kwargs)
-        self.submodules.xover = UART(tx_fifo_depth=2, rx_fifo_depth=2, rx_fifo_rx_we=True)
+        self.submodules.xover = UART(tx_fifo_depth=1, rx_fifo_depth=1, rx_fifo_rx_we=True)
         self.comb += [
             self.source.connect(self.xover.sink),
             self.xover.source.connect(self.sink)