(no commit message)

diff --git a/openpower/sv/vector_ops/discussion.mdwn b/openpower/sv/vector_ops/discussion.mdwn
index 04763fc18ee5b0947152f6cde652b4ba7107ae8c..9cefacda96c8d486201a73c7bfe4b352a7b8a8b5 100644 (file)
--- a/openpower/sv/vector_ops/discussion.mdwn
+++ b/openpower/sv/vector_ops/discussion.mdwn
@@ -172,16 +172,17 @@ Idea 2: implement using outer loop on varying setvl Horizontal-First
 with `1<<r3` predicate mask for src2 as scalar, creates CR field vector, transfer into INT with mfcrweird then OR into the
 result.
 
-    li r3, 1
+```
+    li r3, target
     li result, 0
     for i in range(target):
         setvl target
+        addi r3, r3, -1 # shift 1<<r3 predicate down by one
         sv.addi/sm=1<<r3 t0, src1.v, 0 # copy src1[i]
         sv.cmpi src2.v, t0 # compare src2 vector to scalar
         sv.mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
-        srr t1, t1, i # shift up by i before ORing
         or result, result, t1
-        srr r3, r3, 1 # shift r3 predicate up by one
+```
 
 See [[sv/cr_int_predication]] for full details on the crweird instructions:
 the primary important aspect here is that a Vector of CR Field's EQ bits is