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diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index d5899001a2a90de45e0d648aad0d5d295d815a61..2de241756fde8d4054b48a686d79a9526783f4ec 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -158,10 +158,27 @@ In order of size, for bitmanip and A/V DSP purposes:
 
 * QTY 3of 2-bit XO: ternlogi, crternlogi, grevlogi
 * QTY 7of 3-bit XO: xpermi, binlut, grevlog, swizzle-mv/fmv, bitmask, bmrevi
-* QTY 8of 5/6-bit: xpermi, bincrflut, fmvis, fishmv, bmrev, Galois Field
-* 
+* QTY 8of 5/6-bit (A-Form): xpermi, bincrflut, bmask, fmvis, fishmv, bmrev, Galois Field
+* QTY 30of 10-bit (X-Form): cldiv/mul, av-min/max/diff, absdac, xperm
 
-Additionally
+**EXT004**
+
+For biginteger math, two instructions in the same space as "madd*" are to be proposed.
+They are both 3-in 2-out operations taking or producing a 64-bit "pair" (like RTp),
+and perform 128/64 mul and div/mod operations respectively.
+These are **not** the same as VSX operations
+which are 128/128, and they are **not** the same as existing Scalar mul/div/mod,
+all of which are 64/64 (or 64/32).
+
+**EXT059 and EXT063**
+
+Additionally for High-Performance Compute and Competitive 3D GPU, IEEE754 FP
+Transcendentals are required:
+
+* QTY 33of X-Form "1-argument" (fsin, fsins, fcos, fcoss)
+* QTY 15of X-Form "2-argument" (pow, atan2, fhypot)
+
+--
 
 [^extend]: Prefix opcode space **must** be reserved in advance to do so, in order to avoid the catastrophic binary-incompatibility mistake made by RISC-V RVV and ARM SVE/2
 [^likeext001]: SVP64-Single is remarkably similar to the "bit 1" of EXT001 being set to indicate that the 64-bits is to be allocated in full to a new encoding, but in fact it still embeds v3.0 Scalar operations.