i965: Switch mapping modes for non-explicit-flush blit-temporary maps.

On LLC, it should always be better to use a cached mapping than the GTT.
On non-LLC, it seems pretty silly to try to optimize read performance for
the INVALIDATE_RANGE_BIT case.  This will make the buffer_storage logic
easier.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index e6124dc115521a48493ab778a5a051200345e11f..5bf453326aaa7f10460f1e22f1b3772d868c222d 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -421,11 +421,11 @@ intel_bufferobj_map_range(struct gl_context * ctx,
                                                              "range map",
                                                              length + extra,
                                                              alignment);
-        if (!(access & GL_MAP_READ_BIT)) {
-           drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
-        } else {
+        if (brw->has_llc) {
            drm_intel_bo_map(intel_obj->range_map_bo[index],
                             (access & GL_MAP_WRITE_BIT) != 0);
+        } else {
+           drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]);
         }
         obj->Mappings[index].Pointer =
             intel_obj->range_map_bo[index]->virtual + extra;