ARM: Handle accesses to TLBTR.

diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index f4ff58a28660caea84761f065c322e58f44c249c..41382e5102e1431fe95834a0c122d912addf1abf 100644 (file)
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -131,6 +131,9 @@ namespace ArmISA
                 (0 << 0)     | //Revision
                 0;
 
+            // Separate Instruction and Data TLBs.
+            miscRegs[MISCREG_TLBTR] = 1;
+
             //XXX We need to initialize the rest of the state.
         }
 
@@ -269,6 +272,8 @@ namespace ArmISA
               case MISCREG_CSSELR:
                 warn("The csselr register isn't implemented.\n");
                 break;
+              case MISCREG_TLBTR:
+                return;
             }
             return setMiscRegNoEffect(misc_reg, newVal);
         }

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 6d8c3284528edcb5a748c5e16297b47debafbe73..eac84230753d60d7e28c1a1bba10b03951fb2d7a 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -108,10 +108,10 @@ namespace ArmISA
         MISCREG_MIDR,
         MISCREG_TTBR0,
         MISCREG_TTBR1,
+        MISCREG_TLBTR,
         MISCREG_DACR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
-        MISCREG_TLBTR,
         MISCREG_TCMTR,
         MISCREG_MPIDR,
         MISCREG_ID_PFR0,
@@ -198,7 +198,7 @@ namespace ArmISA
         "clidr", "ccsidr", "csselr",
         "icialluis", "iciallu", "icimvau",
         "bpimva", "bpiallis", "bpiall",
-        "midr", "ttbr0", "ttbr1", "dacr", "ctr", "tlbtr", "tcmtr", "mpidr",
+        "midr", "ttbr0", "ttbr1", "tlbtr", "dacr", "ctr", "tcmtr", "mpidr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",