projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
aa0c377
)
one bit enable signal
author
Miodrag Milanovic
<mmicko@gmail.com>
Sun, 11 Aug 2019 11:59:39 +0000
(13:59 +0200)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Sun, 11 Aug 2019 11:59:39 +0000
(13:59 +0200)
techlibs/efinix/brams_map.v
patch
|
blob
|
history
diff --git
a/techlibs/efinix/brams_map.v
b/techlibs/efinix/brams_map.v
index 3236f39a55c14699cf144545366db1281217ad27..6786ae76970bc886db9b68328b0615831f39b16c 100644
(file)
--- a/
techlibs/efinix/brams_map.v
+++ b/
techlibs/efinix/brams_map.v
@@
-1,7
+1,7
@@
module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 8;
parameter CFG_DBITS = 20;
- parameter CFG_ENABLE_A =
2
;
+ parameter CFG_ENABLE_A =
1
;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;