Use ID::keep more liberally too

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
index 97c88f423bc142e3abecfdaa97becd6da5e94740..c40c02acd51ac78accc252191ddc31d32d2f2e2b 100644 (file)
--- a/passes/opt/muxpack.cc
+++ b/passes/opt/muxpack.cc
@@ -135,7 +135,7 @@ struct MuxpackWorker
        {
                for (auto wire : module->wires())
                {
-                       if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
+                       if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
                                for (auto bit : sigmap(wire))
                                        sigbit_with_non_chain_users.insert(bit);
                        }
@@ -143,7 +143,7 @@ struct MuxpackWorker
 
                for (auto cell : module->cells())
                {
-                       if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID(keep)))
+                       if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
                        {
                                SigSpec a_sig = sigmap(cell->getPort(ID::A));
                                SigSpec b_sig;

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index bf75c7adc737d03c6cc11be6a7d9023f42cd1912..2f69b3d4c1b2d70b24165e3c831b42f53bf19c63 100644 (file)
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -52,7 +52,7 @@ struct keep_cache_t
                        return cache.at(module);
 
                cache[module] = true;
-               if (!module->get_bool_attribute(ID(keep))) {
+               if (!module->get_bool_attribute(ID::keep)) {
                        bool found_keep = false;
                        for (auto cell : module->cells())
                                if (query(cell)) found_keep = true;
@@ -122,7 +122,7 @@ void rmunused_module_cells(Module *module, bool verbose)
 
        for (auto &it : module->wires_) {
                Wire *wire = it.second;
-               if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
+               if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
                        for (auto bit : sigmap(wire))
                        for (auto c : wire2driver[bit])
                                queue.insert(c), unused.erase(c);
@@ -297,7 +297,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
                        if (!wire->port_input)
                                used_signals_nodrivers.add(sig);
                }
-               if (wire->get_bool_attribute(ID(keep))) {
+               if (wire->get_bool_attribute(ID::keep)) {
                        RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
                        assign_map.apply(sig);
                        used_signals.add(sig);
@@ -323,7 +323,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
                        if (wire->port_id == 0)
                                goto delete_this_wire;
                } else
-               if (wire->port_id != 0 || wire->get_bool_attribute(ID(keep)) || !initval.is_fully_undef()) {
+               if (wire->port_id != 0 || wire->get_bool_attribute(ID::keep) || !initval.is_fully_undef()) {
                        // do not delete anything with "keep" or module ports or initialized wires
                } else
                if (!purge_mode && check_public_name(wire->name) && (raw_used_signals.check_any(s1) || used_signals.check_any(s2) || s1 != s2)) {

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 85ec9a55a2247121187d1e6d9d325c11d9ac0a40..f7469853b29869df65ea3b388bbc29ed472c8ea6 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -61,7 +61,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
                }
                if (wire->port_input)
                        driven_signals.add(sigmap(wire));
-               if (wire->port_output || wire->get_bool_attribute(ID(keep)))
+               if (wire->port_output || wire->get_bool_attribute(ID::keep))
                        used_signals.add(sigmap(wire));
                all_signals.add(sigmap(wire));
        }

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 733bc547c28e0111f47ecdc70e473490af0c6a81..c4f2787061ac21a9aac16b71c2552b152c6473df 100644 (file)
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -104,7 +104,7 @@ struct OptLutWorker
                                if (cell->has_keep_attr())
                                        continue;
                                SigBit lut_output = cell->getPort(ID::Y);
-                               if (lut_output.wire->get_bool_attribute(ID(keep)))
+                               if (lut_output.wire->get_bool_attribute(ID::keep))
                                        continue;
 
                                int lut_width = cell->getParam(ID(WIDTH)).as_int();

diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 3d7e9cccb2217738fc975987fa36e12e5038ce9c..3c486bbccd93b90fd9d67e3b80594ba000301bc4 100644 (file)
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -137,7 +137,7 @@ struct OptMuxtreeWorker
                        }
                }
                for (auto wire : module->wires()) {
-                       if (wire->port_output || wire->get_bool_attribute(ID(keep)))
+                       if (wire->port_output || wire->get_bool_attribute(ID::keep))
                                for (int idx : sig2bits(RTLIL::SigSpec(wire)))
                                        bit2info[idx].seen_non_mux = true;
                }

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 792c69c55d9bb76a29263b228f54340bc042ef74..37de8cb61adb35281bc477deecfdf480f5748499 100644 (file)
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -398,7 +398,7 @@ struct WreduceWorker
                SigMap init_attr_sigmap = mi.sigmap;
 
                for (auto w : module->wires()) {
-                       if (w->get_bool_attribute(ID(keep)))
+                       if (w->get_bool_attribute(ID::keep))
                                for (auto bit : mi.sigmap(w))
                                        keep_bits.insert(bit);
                        if (w->attributes.count(ID(init))) {

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 205f05ab9739da90d64e9e8f750e1a63f4f15e4e..4e49b73bab1dc6051a58d5ba5a4f95bcbd4afd6d 100644 (file)
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -198,7 +198,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
                if (keepff)
                        for (auto &c : sig_q.chunks())
                                if (c.wire != NULL)
-                                       c.wire->attributes[ID(keep)] = 1;
+                                       c.wire->attributes[ID::keep] = 1;
 
                assign_map.apply(sig_d);
                assign_map.apply(sig_q);
@@ -787,7 +787,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
                extract_cell(c, keepff);
 
        for (auto &wire_it : module->wires_) {
-               if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID(keep)))
+               if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute(ID::keep))
                        mark_port(RTLIL::SigSpec(wire_it.second));
        }
 

diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 898cb77a45efc75bb822ec87389014955cf8958d..a2551316f42ac70d00e508d15c64a22edfb4cc76 100644 (file)
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -226,7 +226,7 @@ struct IopadmapPass : public Pass {
                                                        cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
                                                        cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
                                                        cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
-                                                       cell->attributes[ID(keep)] = RTLIL::Const(1);
+                                                       cell->attributes[ID::keep] = RTLIL::Const(1);
 
                                                        for (auto cn : tbuf_cache.second) {
                                                                auto c = module->cell(cn);
@@ -263,7 +263,7 @@ struct IopadmapPass : public Pass {
                                                        cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
                                                        cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
                                                        cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
-                                                       cell->attributes[ID(keep)] = RTLIL::Const(1);
+                                                       cell->attributes[ID::keep] = RTLIL::Const(1);
 
                                                        for (auto cn : tbuf_cache.second) {
                                                                auto c = module->cell(cn);
@@ -390,7 +390,7 @@ struct IopadmapPass : public Pass {
                                                        cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
                                                if (!nameparam.empty())
                                                        cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(stringf("%s[%d]", RTLIL::id2cstr(wire->name), i));
-                                               cell->attributes[ID(keep)] = RTLIL::Const(1);
+                                               cell->attributes[ID::keep] = RTLIL::Const(1);
                                        }
                                }
                                else
@@ -403,7 +403,7 @@ struct IopadmapPass : public Pass {
                                                cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
                                        if (!nameparam.empty())
                                                cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
-                                       cell->attributes[ID(keep)] = RTLIL::Const(1);
+                                       cell->attributes[ID::keep] = RTLIL::Const(1);
                                }
 
                                wire->port_id = 0;

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index cb877c2f4db7e863849e4183542b1de72403c38e..5e298d8dd40b0c6110d7334924b1758d80affab8 100644 (file)
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -263,7 +263,7 @@ struct ShregmapWorker
        {
                for (auto wire : module->wires())
                {
-                       if (wire->port_output || wire->get_bool_attribute(ID(keep))) {
+                       if (wire->port_output || wire->get_bool_attribute(ID::keep)) {
                                for (auto bit : sigmap(wire)) {
                                        sigbit_with_non_chain_users.insert(bit);
                                        if (opts.tech) opts.tech->non_chain_user(bit, nullptr, {});
@@ -283,7 +283,7 @@ struct ShregmapWorker
 
                for (auto cell : module->cells())
                {
-                       if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID(keep)))
+                       if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute(ID::keep))
                        {
                                IdString d_port = opts.ffcells.at(cell->type).first;
                                IdString q_port = opts.ffcells.at(cell->type).second;

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index fa038c1b93631a11a36ae14256c72c62ce5f04e7..b271c8781a4c13280a5179f9f263a47d9148caad 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -145,7 +145,7 @@ struct TechmapWorker
                                record.wire = it.second;
                                record.value = it.second;
                                result[p].push_back(record);
-                               it.second->attributes[ID(keep)] = RTLIL::Const(1);
+                               it.second->attributes[ID::keep] = RTLIL::Const(1);
                                it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
                        }
                }