comments for setvl were the wrong bit-position

not the actual fields (whew)

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 11994cf831011df1037999ec7839a1527557dc89..7cdaa4b5329ca507541a2682a061f52efb602ee3 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -199,9 +199,9 @@ class SVP64Asm:
             insn |= fields[0] << (31-10)  # RT       , bits 6-10
             insn |= fields[1] << (31-15)  # RA       , bits 11-15
             insn |= (fields[2]-1) << (31-22)  # SVi      , bits 16-22
-            insn |= fields[3] << (31-25)  # ms       , bit  25
+            insn |= fields[3] << (31-25)  # vf       , bit  25
             insn |= fields[4] << (31-24)  # vs       , bit  24
-            insn |= fields[5] << (31-23)  # vf       , bit  23
+            insn |= fields[5] << (31-23)  # ms       , bit  23
             insn |= 0b00000 << (31-30)  # XO       , bits 26..30
             if opcode == 'setvl.':
                 insn |= 1 << (31-31)     # Rc=1     , bit 31