//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:50
+// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:36
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
wire csrbank0_init_error0_r;
wire csrbank0_init_error0_we;
wire csrbank0_init_error0_w;
-reg csrbank0_sel = 1'd0;
+wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
wire [31:0] interface1_bank_bus_dat_w;
wire [1:0] csrbank1_dly_sel0_r;
wire csrbank1_dly_sel0_we;
wire [1:0] csrbank1_dly_sel0_w;
-reg csrbank1_sel = 1'd0;
+wire csrbank1_sel;
wire [13:0] interface2_bank_bus_adr;
wire interface2_bank_bus_we;
wire [31:0] interface2_bank_bus_dat_w;
wire [31:0] csrbank2_dfii_pi3_rddata_r;
wire csrbank2_dfii_pi3_rddata_we;
wire [31:0] csrbank2_dfii_pi3_rddata_w;
-reg csrbank2_sel = 1'd0;
+wire csrbank2_sel;
wire [13:0] adr;
wire we;
wire [31:0] dat_w;
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we <= litedramcore_wishbone_we;
+ litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
end
end
endcase
// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p2_we_n <= 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
+ end
+// synthesis translate_off
+ dummy_d_26 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_27;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+// synthesis translate_off
+ dummy_d_27 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_28;
+// synthesis translate_on
always @(*) begin
litedramcore_master_p2_cke <= 1'd0;
if (litedramcore_storage[0]) begin
litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
end
// synthesis translate_off
- dummy_d_26 = dummy_s;
+ dummy_d_28 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_27;
+reg dummy_d_29;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_odt <= 1'd0;
litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
end
// synthesis translate_off
- dummy_d_27 = dummy_s;
+ dummy_d_29 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_28;
+reg dummy_d_30;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_reset_n <= 1'd0;
litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
- dummy_d_28 = dummy_s;
+ dummy_d_30 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_29;
+reg dummy_d_31;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_act_n <= 1'd1;
litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
end
// synthesis translate_off
- dummy_d_29 = dummy_s;
+ dummy_d_31 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_30;
+reg dummy_d_32;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_wrdata <= 32'd0;
litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
end
// synthesis translate_off
- dummy_d_30 = dummy_s;
+ dummy_d_32 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_31;
+reg dummy_d_33;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_rddata <= 32'd0;
litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
end
// synthesis translate_off
- dummy_d_31 = dummy_s;
+ dummy_d_33 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_32;
+reg dummy_d_34;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_wrdata_en <= 1'd0;
litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
end
// synthesis translate_off
- dummy_d_32 = dummy_s;
+ dummy_d_34 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_33;
+reg dummy_d_35;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_rddata_valid <= 1'd0;
litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
- dummy_d_33 = dummy_s;
+ dummy_d_35 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_34;
+reg dummy_d_36;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_wrdata_mask <= 4'd0;
litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
end
// synthesis translate_off
- dummy_d_34 = dummy_s;
+ dummy_d_36 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_35;
+reg dummy_d_37;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_rddata_en <= 1'd0;
litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
- dummy_d_35 = dummy_s;
+ dummy_d_37 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_36;
+reg dummy_d_38;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_address <= 14'd0;
litedramcore_master_p3_address <= litedramcore_inti_p3_address;
end
// synthesis translate_off
- dummy_d_36 = dummy_s;
+ dummy_d_38 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_37;
+reg dummy_d_39;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_bank <= 3'd0;
litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
end
// synthesis translate_off
- dummy_d_37 = dummy_s;
+ dummy_d_39 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_38;
+reg dummy_d_40;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_cas_n <= 1'd1;
litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
- dummy_d_38 = dummy_s;
+ dummy_d_40 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_39;
+reg dummy_d_41;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_cs_n <= 1'd1;
litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
- dummy_d_39 = dummy_s;
+ dummy_d_41 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_40;
+reg dummy_d_42;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_ras_n <= 1'd1;
litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
end
// synthesis translate_off
- dummy_d_40 = dummy_s;
+ dummy_d_42 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_41;
+reg dummy_d_43;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p3_rddata <= 32'd0;
end else begin
end
// synthesis translate_off
- dummy_d_41 = dummy_s;
+ dummy_d_43 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_42;
+reg dummy_d_44;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_we_n <= 1'd1;
litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
end
// synthesis translate_off
- dummy_d_42 = dummy_s;
+ dummy_d_44 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_43;
+reg dummy_d_45;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p3_rddata_valid <= 1'd0;
end else begin
end
// synthesis translate_off
- dummy_d_43 = dummy_s;
+ dummy_d_45 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_44;
+reg dummy_d_46;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_cke <= 1'd0;
litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
end
// synthesis translate_off
- dummy_d_44 = dummy_s;
+ dummy_d_46 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_45;
+reg dummy_d_47;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_odt <= 1'd0;
litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
end
// synthesis translate_off
- dummy_d_45 = dummy_s;
+ dummy_d_47 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_46;
+reg dummy_d_48;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_reset_n <= 1'd0;
litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
end
// synthesis translate_off
- dummy_d_46 = dummy_s;
+ dummy_d_48 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_47;
+reg dummy_d_49;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_act_n <= 1'd1;
litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
end
// synthesis translate_off
- dummy_d_47 = dummy_s;
+ dummy_d_49 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_48;
+reg dummy_d_50;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_wrdata <= 32'd0;
litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
end
// synthesis translate_off
- dummy_d_48 = dummy_s;
+ dummy_d_50 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_49;
+reg dummy_d_51;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_rddata <= 32'd0;
litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
end
// synthesis translate_off
- dummy_d_49 = dummy_s;
+ dummy_d_51 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_50;
+reg dummy_d_52;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_wrdata_en <= 1'd0;
litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
end
// synthesis translate_off
- dummy_d_50 = dummy_s;
+ dummy_d_52 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_51;
+reg dummy_d_53;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_rddata_valid <= 1'd0;
litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end
// synthesis translate_off
- dummy_d_51 = dummy_s;
+ dummy_d_53 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_52;
+reg dummy_d_54;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_wrdata_mask <= 4'd0;
litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
end
// synthesis translate_off
- dummy_d_52 = dummy_s;
+ dummy_d_54 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_53;
+reg dummy_d_55;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_rddata_en <= 1'd0;
litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
end
// synthesis translate_off
- dummy_d_53 = dummy_s;
+ dummy_d_55 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_54;
+reg dummy_d_56;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_address <= 14'd0;
litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
- dummy_d_54 = dummy_s;
+ dummy_d_56 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_55;
+reg dummy_d_57;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_bank <= 3'd0;
litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
end
// synthesis translate_off
- dummy_d_55 = dummy_s;
+ dummy_d_57 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_56;
+reg dummy_d_58;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_cas_n <= 1'd1;
litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
- dummy_d_56 = dummy_s;
+ dummy_d_58 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_57;
+reg dummy_d_59;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_cs_n <= 1'd1;
litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
end
// synthesis translate_off
- dummy_d_57 = dummy_s;
+ dummy_d_59 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_58;
+reg dummy_d_60;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p0_rddata <= 32'd0;
end else begin
end
// synthesis translate_off
- dummy_d_58 = dummy_s;
+ dummy_d_60 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_59;
+reg dummy_d_61;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_ras_n <= 1'd1;
litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
end
// synthesis translate_off
- dummy_d_59 = dummy_s;
+ dummy_d_61 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_60;
+reg dummy_d_62;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
+ litedramcore_master_p0_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
end else begin
+ litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
end
// synthesis translate_off
- dummy_d_60 = dummy_s;
+ dummy_d_62 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_61;
+reg dummy_d_63;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end else begin
- litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
end
// synthesis translate_off
- dummy_d_61 = dummy_s;
+ dummy_d_63 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_62;
+reg dummy_d_64;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_cke <= 1'd0;
litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
end
// synthesis translate_off
- dummy_d_62 = dummy_s;
+ dummy_d_64 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_63;
+reg dummy_d_65;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_odt <= 1'd0;
litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
end
// synthesis translate_off
- dummy_d_63 = dummy_s;
+ dummy_d_65 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_64;
+reg dummy_d_66;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_reset_n <= 1'd0;
litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
end
// synthesis translate_off
- dummy_d_64 = dummy_s;
+ dummy_d_66 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_65;
+reg dummy_d_67;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_act_n <= 1'd1;
litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
end
// synthesis translate_off
- dummy_d_65 = dummy_s;
+ dummy_d_67 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_66;
+reg dummy_d_68;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_wrdata <= 32'd0;
litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
end
// synthesis translate_off
- dummy_d_66 = dummy_s;
+ dummy_d_68 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_67;
+reg dummy_d_69;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_rddata <= 32'd0;
litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
end
// synthesis translate_off
- dummy_d_67 = dummy_s;
+ dummy_d_69 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_68;
+reg dummy_d_70;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_wrdata_en <= 1'd0;
litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
end
// synthesis translate_off
- dummy_d_68 = dummy_s;
+ dummy_d_70 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_69;
+reg dummy_d_71;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_rddata_valid <= 1'd0;
litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end
// synthesis translate_off
- dummy_d_69 = dummy_s;
+ dummy_d_71 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_70;
+reg dummy_d_72;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_wrdata_mask <= 4'd0;
litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
end
// synthesis translate_off
- dummy_d_70 = dummy_s;
+ dummy_d_72 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_71;
+reg dummy_d_73;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_rddata_en <= 1'd0;
litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
- dummy_d_71 = dummy_s;
+ dummy_d_73 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_72;
+reg dummy_d_74;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_address <= 14'd0;
litedramcore_master_p1_address <= litedramcore_inti_p1_address;
end
// synthesis translate_off
- dummy_d_72 = dummy_s;
+ dummy_d_74 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_73;
+reg dummy_d_75;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_bank <= 3'd0;
litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
end
// synthesis translate_off
- dummy_d_73 = dummy_s;
+ dummy_d_75 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_74;
+reg dummy_d_76;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_cas_n <= 1'd1;
litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
- dummy_d_74 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_75;
-// synthesis translate_on
-always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
- end else begin
- end
-// synthesis translate_off
- dummy_d_75 = dummy_s;
+ dummy_d_76 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_76;
+reg dummy_d_77;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_cs_n <= 1'd1;
litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
- dummy_d_76 = dummy_s;
+ dummy_d_77 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_77;
+reg dummy_d_78;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_ras_n <= 1'd1;
litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
end
// synthesis translate_off
- dummy_d_77 = dummy_s;
+ dummy_d_78 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_78;
+reg dummy_d_79;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p1_rddata <= 32'd0;
end else begin
end
// synthesis translate_off
- dummy_d_78 = dummy_s;
+ dummy_d_79 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_79;
+reg dummy_d_80;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_we_n <= 1'd1;
litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
end
// synthesis translate_off
- dummy_d_79 = dummy_s;
+ dummy_d_80 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_80;
+reg dummy_d_81;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p1_rddata_valid <= 1'd0;
end else begin
end
// synthesis translate_off
- dummy_d_80 = dummy_s;
+ dummy_d_81 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_81;
+reg dummy_d_82;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_cke <= 1'd0;
litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
end
// synthesis translate_off
- dummy_d_81 = dummy_s;
+ dummy_d_82 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_82;
+reg dummy_d_83;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_odt <= 1'd0;
litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
end
// synthesis translate_off
- dummy_d_82 = dummy_s;
+ dummy_d_83 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_83;
+reg dummy_d_84;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
+ litedramcore_master_p1_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
- dummy_d_83 = dummy_s;
+ dummy_d_84 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_84;
+reg dummy_d_85;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
+ litedramcore_slave_p2_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
end else begin
- litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
- dummy_d_84 = dummy_s;
+ dummy_d_85 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_85;
+reg dummy_d_86;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_act_n <= 1'd1;
litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
end
// synthesis translate_off
- dummy_d_85 = dummy_s;
+ dummy_d_86 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_86;
+reg dummy_d_87;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_wrdata <= 32'd0;
litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
end
// synthesis translate_off
- dummy_d_86 = dummy_s;
+ dummy_d_87 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_87;
+reg dummy_d_88;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_rddata <= 32'd0;
litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
end
// synthesis translate_off
- dummy_d_87 = dummy_s;
+ dummy_d_88 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_88;
+reg dummy_d_89;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_wrdata_en <= 1'd0;
litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
end
// synthesis translate_off
- dummy_d_88 = dummy_s;
+ dummy_d_89 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_89;
+reg dummy_d_90;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_rddata_valid <= 1'd0;
litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
end
// synthesis translate_off
- dummy_d_89 = dummy_s;
+ dummy_d_90 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_90;
+reg dummy_d_91;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_wrdata_mask <= 4'd0;
litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
end
// synthesis translate_off
- dummy_d_90 = dummy_s;
+ dummy_d_91 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_91;
+reg dummy_d_92;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_rddata_en <= 1'd0;
litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
end
// synthesis translate_off
- dummy_d_91 = dummy_s;
+ dummy_d_92 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_92;
+reg dummy_d_93;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_address <= 14'd0;
litedramcore_master_p2_address <= litedramcore_inti_p2_address;
end
// synthesis translate_off
- dummy_d_92 = dummy_s;
+ dummy_d_93 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_93;
+reg dummy_d_94;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_bank <= 3'd0;
litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
end
// synthesis translate_off
- dummy_d_93 = dummy_s;
+ dummy_d_94 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_94;
+reg dummy_d_95;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_cas_n <= 1'd1;
litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
end
// synthesis translate_off
- dummy_d_94 = dummy_s;
+ dummy_d_95 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_95;
+reg dummy_d_96;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_cs_n <= 1'd1;
litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
end
// synthesis translate_off
- dummy_d_95 = dummy_s;
+ dummy_d_96 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_96;
+reg dummy_d_97;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_ras_n <= 1'd1;
end else begin
litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
end
-// synthesis translate_off
- dummy_d_96 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_97;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
- end
// synthesis translate_off
dummy_d_97 = dummy_s;
// synthesis translate_on
reg dummy_d_98;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cas_n <= 1'd1;
+ litedramcore_inti_p0_we_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
+ litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
end else begin
- litedramcore_inti_p0_cas_n <= 1'd1;
+ litedramcore_inti_p0_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_98 = dummy_s;
reg dummy_d_99;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cs_n <= 1'd1;
+ litedramcore_inti_p0_cas_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+ litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
end else begin
- litedramcore_inti_p0_cs_n <= {1{1'd1}};
+ litedramcore_inti_p0_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_99 = dummy_s;
reg dummy_d_100;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_ras_n <= 1'd1;
+ litedramcore_inti_p0_cs_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
+ litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
end else begin
- litedramcore_inti_p0_ras_n <= 1'd1;
+ litedramcore_inti_p0_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_100 = dummy_s;
reg dummy_d_101;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_we_n <= 1'd1;
+ litedramcore_inti_p0_ras_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
+ litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
end else begin
- litedramcore_inti_p0_we_n <= 1'd1;
+ litedramcore_inti_p0_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_101 = dummy_s;
reg dummy_d_102;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cas_n <= 1'd1;
+ litedramcore_inti_p1_we_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
+ litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
end else begin
- litedramcore_inti_p1_cas_n <= 1'd1;
+ litedramcore_inti_p1_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_102 = dummy_s;
reg dummy_d_103;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cs_n <= 1'd1;
+ litedramcore_inti_p1_cas_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+ litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
end else begin
- litedramcore_inti_p1_cs_n <= {1{1'd1}};
+ litedramcore_inti_p1_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_103 = dummy_s;
reg dummy_d_104;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_ras_n <= 1'd1;
+ litedramcore_inti_p1_cs_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
+ litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
end else begin
- litedramcore_inti_p1_ras_n <= 1'd1;
+ litedramcore_inti_p1_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_104 = dummy_s;
reg dummy_d_105;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_we_n <= 1'd1;
+ litedramcore_inti_p1_ras_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
+ litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
end else begin
- litedramcore_inti_p1_we_n <= 1'd1;
+ litedramcore_inti_p1_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_105 = dummy_s;
reg dummy_d_106;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cas_n <= 1'd1;
+ litedramcore_inti_p2_we_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
+ litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
end else begin
- litedramcore_inti_p2_cas_n <= 1'd1;
+ litedramcore_inti_p2_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_106 = dummy_s;
reg dummy_d_107;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cs_n <= 1'd1;
+ litedramcore_inti_p2_cas_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
+ litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
end else begin
- litedramcore_inti_p2_cs_n <= {1{1'd1}};
+ litedramcore_inti_p2_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_107 = dummy_s;
reg dummy_d_108;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_ras_n <= 1'd1;
+ litedramcore_inti_p2_cs_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
+ litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
end else begin
- litedramcore_inti_p2_ras_n <= 1'd1;
+ litedramcore_inti_p2_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_108 = dummy_s;
reg dummy_d_109;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_we_n <= 1'd1;
+ litedramcore_inti_p2_ras_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
+ litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
end else begin
- litedramcore_inti_p2_we_n <= 1'd1;
+ litedramcore_inti_p2_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_109 = dummy_s;
reg dummy_d_110;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cas_n <= 1'd1;
+ litedramcore_inti_p3_we_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
+ litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
end else begin
- litedramcore_inti_p3_cas_n <= 1'd1;
+ litedramcore_inti_p3_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_110 = dummy_s;
reg dummy_d_111;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cs_n <= 1'd1;
+ litedramcore_inti_p3_cas_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
+ litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
end else begin
- litedramcore_inti_p3_cs_n <= {1{1'd1}};
+ litedramcore_inti_p3_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_111 = dummy_s;
reg dummy_d_112;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_ras_n <= 1'd1;
+ litedramcore_inti_p3_cs_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
+ litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
end else begin
- litedramcore_inti_p3_ras_n <= 1'd1;
+ litedramcore_inti_p3_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_112 = dummy_s;
reg dummy_d_113;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_we_n <= 1'd1;
+ litedramcore_inti_p3_ras_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
+ litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
end else begin
- litedramcore_inti_p3_we_n <= 1'd1;
+ litedramcore_inti_p3_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_113 = dummy_s;
bankmachine0_next_state <= 4'd8;
end
4'd8: begin
- bankmachine0_next_state <= 1'd0;
+ bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_122 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_123;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
end
default: begin
if (litedramcore_bankmachine0_refresh_req) begin
- bankmachine0_next_state <= 3'd4;
end else begin
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- bankmachine0_next_state <= 2'd2;
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
end
end else begin
- bankmachine0_next_state <= 1'd1;
end
end else begin
- bankmachine0_next_state <= 2'd3;
end
end
end
end
endcase
// synthesis translate_off
- dummy_d_122 = dummy_s;
+ dummy_d_123 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_123;
+reg dummy_d_124;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
case (bankmachine0_state)
1'd1: begin
end
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_123 = dummy_s;
+ dummy_d_124 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_124;
+reg dummy_d_125;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_124 = dummy_s;
+ dummy_d_125 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_125;
+reg dummy_d_126;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_125 = dummy_s;
+ dummy_d_126 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_126;
+reg dummy_d_127;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_valid <= 1'd0;
end
end
endcase
-// synthesis translate_off
- dummy_d_126 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
// synthesis translate_off
dummy_d_127 = dummy_s;
// synthesis translate_on
reg dummy_d_128;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_129;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine0_row_open <= 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_130;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine0_row_close <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
+ litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_131;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_132;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
case (bankmachine0_state)
1'd1: begin
if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_133;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_134;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_135;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
case (bankmachine0_state)
1'd1: begin
end
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_140;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
end
end else begin
end
reg dummy_d_141;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_142;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_143;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_143 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_144;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_143 = dummy_s;
+ dummy_d_144 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_144;
+reg dummy_d_145;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_144 = dummy_s;
+ dummy_d_145 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_145;
+reg dummy_d_146;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_145 = dummy_s;
+ dummy_d_146 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_146;
+reg dummy_d_147;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_146 = dummy_s;
+ dummy_d_147 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_147;
+reg dummy_d_148;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
default: begin
end
endcase
-// synthesis translate_off
- dummy_d_147 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_148;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
// synthesis translate_off
dummy_d_148 = dummy_s;
// synthesis translate_on
reg dummy_d_149;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_150;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_151;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_152;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_157;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
end
end else begin
end
reg dummy_d_158;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_159;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_160;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_161;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_162;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_163;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine2_row_open <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine2_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_164;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine2_row_close <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_165;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_166;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
case (bankmachine2_state)
1'd1: begin
if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_167;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_168;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_169;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_174;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
end
end else begin
end
reg dummy_d_175;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_176;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_177;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_178;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_179;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_180;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine3_row_open <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ litedramcore_bankmachine3_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_181;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine3_row_close <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
+ litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_182;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_183;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_184;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_185;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_186;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_191;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
case (bankmachine4_state)
1'd1: begin
end
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
end
end else begin
end
reg dummy_d_192;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_193;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_195;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_196;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
+ litedramcore_bankmachine4_row_open <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_197;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine4_row_close <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_198;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
reg dummy_d_199;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_200;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
case (bankmachine4_state)
1'd1: begin
if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_201;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_202;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_203;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
case (bankmachine4_state)
1'd1: begin
end
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_208;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
end
end else begin
end
reg dummy_d_209;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_210;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_211;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_212;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
// synthesis translate_off
reg dummy_d_213;
// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_213 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_214;
+// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_row_close <= 1'd0;
case (bankmachine5_state)
end
endcase
// synthesis translate_off
- dummy_d_213 = dummy_s;
+ dummy_d_214 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_214;
+reg dummy_d_215;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_214 = dummy_s;
+ dummy_d_215 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_215;
+reg dummy_d_216;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_215 = dummy_s;
+ dummy_d_216 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_216;
+reg dummy_d_217;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_216 = dummy_s;
+ dummy_d_217 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_217;
+reg dummy_d_218;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
default: begin
end
endcase
-// synthesis translate_off
- dummy_d_217 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_218;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
// synthesis translate_off
dummy_d_218 = dummy_s;
// synthesis translate_on
reg dummy_d_219;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_220;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_225;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
end
end else begin
end
reg dummy_d_226;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_227;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
end else begin
end
end else begin
reg dummy_d_228;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
reg dummy_d_229;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
reg dummy_d_230;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
end else begin
end
end else begin
reg dummy_d_231;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine6_row_open <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ litedramcore_bankmachine6_row_open <= 1'd1;
end
end
3'd4: begin
reg dummy_d_232;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine6_row_close <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
+ litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_233;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_234;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
reg dummy_d_235;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_236;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_237;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_242;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_243;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
end
end else begin
end
reg dummy_d_244;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_245;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_246;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
reg dummy_d_247;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_248;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine7_row_open <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_249;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine7_row_close <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
+ litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
reg dummy_d_250;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
reg dummy_d_251;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
case (bankmachine7_state)
1'd1: begin
if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
reg dummy_d_252;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_253;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
reg dummy_d_254;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
end
end else begin
end
reg dummy_d_272;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
+ litedramcore_steerer_sel2 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel3 <= 2'd2;
+ litedramcore_steerer_sel2 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel3 <= 1'd0;
+ litedramcore_steerer_sel2 <= 2'd2;
end
endcase
// synthesis translate_off
reg dummy_d_273;
// synthesis translate_on
always @(*) begin
- litedramcore_en0 <= 1'd0;
+ litedramcore_choose_cmd_want_activates <= 1'd0;
case (multiplexer_state)
1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_en0 <= 1'd1;
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
end
endcase
// synthesis translate_off
reg dummy_d_274;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
+ litedramcore_steerer_sel3 <= 2'd0;
case (multiplexer_state)
1'd1: begin
+ litedramcore_steerer_sel3 <= 2'd2;
end
2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
+ litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_275;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ litedramcore_en0 <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
+ litedramcore_en0 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_276;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
+ litedramcore_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
end
2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_277;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
endcase
// synthesis translate_off
reg dummy_d_278;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
+ litedramcore_choose_req_want_reads <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
+ litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_279;
// synthesis translate_on
always @(*) begin
- litedramcore_en1 <= 1'd0;
+ litedramcore_choose_req_want_writes <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_en1 <= 1'd1;
+ litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
reg dummy_d_280;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
+ litedramcore_choose_req_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
endcase
// synthesis translate_off
reg dummy_d_281;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
+ litedramcore_en1 <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
+ litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel1 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_282;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
+ litedramcore_steerer_sel0 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel2 <= 1'd1;
+ litedramcore_steerer_sel0 <= 1'd0;
end
2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel2 <= 2'd2;
+ litedramcore_steerer_sel0 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_283;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
+ litedramcore_steerer_sel1 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
+ litedramcore_steerer_sel1 <= 1'd0;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
+ litedramcore_steerer_sel1 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_284;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
+ litedramcore_interface_wdata <= 128'd0;
case ({new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
end
default: begin
- litedramcore_interface_wdata_we <= 1'd0;
+ litedramcore_interface_wdata <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_285;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
+ litedramcore_interface_wdata_we <= 16'd0;
case ({new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
end
default: begin
- litedramcore_interface_wdata <= 1'd0;
+ litedramcore_interface_wdata_we <= 1'd0;
end
endcase
// synthesis translate_off
assign litedramcore_wishbone_cti = wb_bus_cti;
assign litedramcore_wishbone_bte = wb_bus_bte;
assign wb_bus_err = litedramcore_wishbone_err;
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
-always @(*) begin
- csrbank0_sel <= 1'd0;
- csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2);
- if (interface0_bank_bus_adr[0]) begin
- csrbank0_sel <= 1'd0;
- end
-// synthesis translate_off
- dummy_d_286 = dummy_s;
-// synthesis translate_on
-end
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
-assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
-assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
-always @(*) begin
- csrbank1_sel <= 1'd0;
- csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0);
- if (interface1_bank_bus_adr[0]) begin
- csrbank1_sel <= 1'd0;
- end
-// synthesis translate_off
- dummy_d_287 = dummy_s;
-// synthesis translate_on
-end
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
-assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0));
-assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0));
+assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0));
+assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0));
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
-assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1));
-assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1));
+assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1));
+assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1));
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2));
-assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2));
+assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2));
+assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2));
assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3));
-assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3));
+assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3));
+assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3));
assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4));
-assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4));
+assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4));
+assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4));
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
-assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5));
-assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5));
+assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5));
+assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5));
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6));
-assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6));
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7));
-assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7));
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9));
-assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9));
assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
-always @(*) begin
- csrbank2_sel <= 1'd0;
- csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1);
- if (interface2_bank_bus_adr[0]) begin
- csrbank2_sel <= 1'd0;
- end
-// synthesis translate_off
- dummy_d_288 = dummy_s;
-// synthesis translate_on
-end
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
-assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0));
-assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0));
+assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0));
+assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0));
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1));
-assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1));
+assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1));
+assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2));
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3));
-assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3));
+assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3));
+assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3));
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4));
-assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4));
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5));
-assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5));
assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6));
-assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6));
+assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6));
+assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6));
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7));
-assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7));
+assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7));
+assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8));
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9));
-assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9));
+assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9));
+assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9));
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10));
-assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10));
+assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10));
+assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10));
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11));
-assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11));
+assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11));
+assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11));
assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12));
-assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12));
+assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12));
+assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12));
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13));
-assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13));
+assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13));
+assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14));
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15));
-assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15));
+assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15));
+assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15));
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16));
-assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16));
+assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16));
+assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16));
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17));
-assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17));
+assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17));
+assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17));
assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18));
-assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18));
+assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18));
+assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18));
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19));
-assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19));
+assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19));
+assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20));
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
-assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21));
-assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21));
+assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21));
+assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21));
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22));
-assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22));
+assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22));
+assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22));
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23));
-assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23));
+assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23));
+assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23));
assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24));
-assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24));
+assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24));
+assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24));
assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
// synthesis translate_off
-reg dummy_d_289;
+reg dummy_d_286;
// synthesis translate_on
always @(*) begin
rhs_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_289 = dummy_s;
+ dummy_d_286 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_290;
+reg dummy_d_287;
// synthesis translate_on
always @(*) begin
rhs_array_muxed1 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_290 = dummy_s;
+ dummy_d_287 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_291;
+reg dummy_d_288;
// synthesis translate_on
always @(*) begin
rhs_array_muxed2 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_291 = dummy_s;
+ dummy_d_288 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_292;
+reg dummy_d_289;
// synthesis translate_on
always @(*) begin
rhs_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_292 = dummy_s;
+ dummy_d_289 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_293;
+reg dummy_d_290;
// synthesis translate_on
always @(*) begin
rhs_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_293 = dummy_s;
+ dummy_d_290 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_294;
+reg dummy_d_291;
// synthesis translate_on
always @(*) begin
rhs_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_294 = dummy_s;
+ dummy_d_291 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_292;
// synthesis translate_on
always @(*) begin
t_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_295 = dummy_s;
+ dummy_d_292 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_293;
// synthesis translate_on
always @(*) begin
t_array_muxed1 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_296 = dummy_s;
+ dummy_d_293 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_297;
+reg dummy_d_294;
// synthesis translate_on
always @(*) begin
t_array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_297 = dummy_s;
+ dummy_d_294 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_298;
+reg dummy_d_295;
// synthesis translate_on
always @(*) begin
rhs_array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_298 = dummy_s;
+ dummy_d_295 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_299;
+reg dummy_d_296;
// synthesis translate_on
always @(*) begin
rhs_array_muxed7 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_299 = dummy_s;
+ dummy_d_296 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_300;
+reg dummy_d_297;
// synthesis translate_on
always @(*) begin
rhs_array_muxed8 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_300 = dummy_s;
+ dummy_d_297 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_301;
+reg dummy_d_298;
// synthesis translate_on
always @(*) begin
rhs_array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_301 = dummy_s;
+ dummy_d_298 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_302;
+reg dummy_d_299;
// synthesis translate_on
always @(*) begin
rhs_array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_302 = dummy_s;
+ dummy_d_299 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_303;
+reg dummy_d_300;
// synthesis translate_on
always @(*) begin
rhs_array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_303 = dummy_s;
+ dummy_d_300 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_304;
+reg dummy_d_301;
// synthesis translate_on
always @(*) begin
t_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_304 = dummy_s;
+ dummy_d_301 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_305;
+reg dummy_d_302;
// synthesis translate_on
always @(*) begin
t_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_305 = dummy_s;
+ dummy_d_302 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_306;
+reg dummy_d_303;
// synthesis translate_on
always @(*) begin
t_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_306 = dummy_s;
+ dummy_d_303 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_307;
+reg dummy_d_304;
// synthesis translate_on
always @(*) begin
rhs_array_muxed12 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_307 = dummy_s;
+ dummy_d_304 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_308;
+reg dummy_d_305;
// synthesis translate_on
always @(*) begin
rhs_array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_308 = dummy_s;
+ dummy_d_305 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_309;
+reg dummy_d_306;
// synthesis translate_on
always @(*) begin
rhs_array_muxed14 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_309 = dummy_s;
+ dummy_d_306 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_310;
+reg dummy_d_307;
// synthesis translate_on
always @(*) begin
rhs_array_muxed15 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_310 = dummy_s;
+ dummy_d_307 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_311;
+reg dummy_d_308;
// synthesis translate_on
always @(*) begin
rhs_array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_311 = dummy_s;
+ dummy_d_308 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_312;
+reg dummy_d_309;
// synthesis translate_on
always @(*) begin
rhs_array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_312 = dummy_s;
+ dummy_d_309 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_313;
+reg dummy_d_310;
// synthesis translate_on
always @(*) begin
rhs_array_muxed18 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_313 = dummy_s;
+ dummy_d_310 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_314;
+reg dummy_d_311;
// synthesis translate_on
always @(*) begin
rhs_array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_314 = dummy_s;
+ dummy_d_311 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_315;
+reg dummy_d_312;
// synthesis translate_on
always @(*) begin
rhs_array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_315 = dummy_s;
+ dummy_d_312 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_316;
+reg dummy_d_313;
// synthesis translate_on
always @(*) begin
rhs_array_muxed21 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_316 = dummy_s;
+ dummy_d_313 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_317;
+reg dummy_d_314;
// synthesis translate_on
always @(*) begin
rhs_array_muxed22 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_317 = dummy_s;
+ dummy_d_314 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_318;
+reg dummy_d_315;
// synthesis translate_on
always @(*) begin
rhs_array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_318 = dummy_s;
+ dummy_d_315 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_319;
+reg dummy_d_316;
// synthesis translate_on
always @(*) begin
rhs_array_muxed24 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_319 = dummy_s;
+ dummy_d_316 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_320;
+reg dummy_d_317;
// synthesis translate_on
always @(*) begin
rhs_array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_320 = dummy_s;
+ dummy_d_317 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_321;
+reg dummy_d_318;
// synthesis translate_on
always @(*) begin
rhs_array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_321 = dummy_s;
+ dummy_d_318 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_322;
+reg dummy_d_319;
// synthesis translate_on
always @(*) begin
rhs_array_muxed27 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_322 = dummy_s;
+ dummy_d_319 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_323;
+reg dummy_d_320;
// synthesis translate_on
always @(*) begin
rhs_array_muxed28 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_323 = dummy_s;
+ dummy_d_320 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_324;
+reg dummy_d_321;
// synthesis translate_on
always @(*) begin
rhs_array_muxed29 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_324 = dummy_s;
+ dummy_d_321 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_325;
+reg dummy_d_322;
// synthesis translate_on
always @(*) begin
rhs_array_muxed30 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_325 = dummy_s;
+ dummy_d_322 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_326;
+reg dummy_d_323;
// synthesis translate_on
always @(*) begin
rhs_array_muxed31 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_326 = dummy_s;
+ dummy_d_323 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_327;
+reg dummy_d_324;
// synthesis translate_on
always @(*) begin
rhs_array_muxed32 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_327 = dummy_s;
+ dummy_d_324 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_328;
+reg dummy_d_325;
// synthesis translate_on
always @(*) begin
rhs_array_muxed33 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_328 = dummy_s;
+ dummy_d_325 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_329;
+reg dummy_d_326;
// synthesis translate_on
always @(*) begin
rhs_array_muxed34 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_329 = dummy_s;
+ dummy_d_326 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_330;
+reg dummy_d_327;
// synthesis translate_on
always @(*) begin
rhs_array_muxed35 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_330 = dummy_s;
+ dummy_d_327 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_331;
+reg dummy_d_328;
// synthesis translate_on
always @(*) begin
array_muxed0 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_331 = dummy_s;
+ dummy_d_328 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_332;
+reg dummy_d_329;
// synthesis translate_on
always @(*) begin
array_muxed1 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_332 = dummy_s;
+ dummy_d_329 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_333;
+reg dummy_d_330;
// synthesis translate_on
always @(*) begin
array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_333 = dummy_s;
+ dummy_d_330 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_334;
+reg dummy_d_331;
// synthesis translate_on
always @(*) begin
array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_334 = dummy_s;
+ dummy_d_331 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_335;
+reg dummy_d_332;
// synthesis translate_on
always @(*) begin
array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_335 = dummy_s;
+ dummy_d_332 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_336;
+reg dummy_d_333;
// synthesis translate_on
always @(*) begin
array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_336 = dummy_s;
+ dummy_d_333 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_337;
+reg dummy_d_334;
// synthesis translate_on
always @(*) begin
array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_337 = dummy_s;
+ dummy_d_334 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_338;
+reg dummy_d_335;
// synthesis translate_on
always @(*) begin
array_muxed7 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_338 = dummy_s;
+ dummy_d_335 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_339;
+reg dummy_d_336;
// synthesis translate_on
always @(*) begin
array_muxed8 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_339 = dummy_s;
+ dummy_d_336 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_340;
+reg dummy_d_337;
// synthesis translate_on
always @(*) begin
array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_340 = dummy_s;
+ dummy_d_337 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_341;
+reg dummy_d_338;
// synthesis translate_on
always @(*) begin
array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_341 = dummy_s;
+ dummy_d_338 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_342;
+reg dummy_d_339;
// synthesis translate_on
always @(*) begin
array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_342 = dummy_s;
+ dummy_d_339 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_343;
+reg dummy_d_340;
// synthesis translate_on
always @(*) begin
array_muxed12 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_343 = dummy_s;
+ dummy_d_340 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_344;
+reg dummy_d_341;
// synthesis translate_on
always @(*) begin
array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_344 = dummy_s;
+ dummy_d_341 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_345;
+reg dummy_d_342;
// synthesis translate_on
always @(*) begin
array_muxed14 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_345 = dummy_s;
+ dummy_d_342 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_346;
+reg dummy_d_343;
// synthesis translate_on
always @(*) begin
array_muxed15 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_346 = dummy_s;
+ dummy_d_343 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_347;
+reg dummy_d_344;
// synthesis translate_on
always @(*) begin
array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_347 = dummy_s;
+ dummy_d_344 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_348;
+reg dummy_d_345;
// synthesis translate_on
always @(*) begin
array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_348 = dummy_s;
+ dummy_d_345 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_349;
+reg dummy_d_346;
// synthesis translate_on
always @(*) begin
array_muxed18 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_349 = dummy_s;
+ dummy_d_346 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_350;
+reg dummy_d_347;
// synthesis translate_on
always @(*) begin
array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_350 = dummy_s;
+ dummy_d_347 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_351;
+reg dummy_d_348;
// synthesis translate_on
always @(*) begin
array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_351 = dummy_s;
+ dummy_d_348 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_352;
+reg dummy_d_349;
// synthesis translate_on
always @(*) begin
array_muxed21 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_352 = dummy_s;
+ dummy_d_349 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_353;
+reg dummy_d_350;
// synthesis translate_on
always @(*) begin
array_muxed22 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_353 = dummy_s;
+ dummy_d_350 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_354;
+reg dummy_d_351;
// synthesis translate_on
always @(*) begin
array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_354 = dummy_s;
+ dummy_d_351 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_355;
+reg dummy_d_352;
// synthesis translate_on
always @(*) begin
array_muxed24 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_355 = dummy_s;
+ dummy_d_352 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_356;
+reg dummy_d_353;
// synthesis translate_on
always @(*) begin
array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_356 = dummy_s;
+ dummy_d_353 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_357;
+reg dummy_d_354;
// synthesis translate_on
always @(*) begin
array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_357 = dummy_s;
+ dummy_d_354 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_358;
+reg dummy_d_355;
// synthesis translate_on
always @(*) begin
array_muxed27 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_358 = dummy_s;
+ dummy_d_355 = dummy_s;
// synthesis translate_on
end
assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
new_master_rdata_valid8 <= new_master_rdata_valid7;
interface0_bank_bus_dat_r <= 1'd0;
if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[1])
+ case (interface0_bank_bus_adr[0])
1'd0: begin
interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
end
init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[4:1])
+ case (interface1_bank_bus_adr[3:0])
1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
end
a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
interface2_bank_bus_dat_r <= 1'd0;
if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[5:1])
+ case (interface2_bank_bus_adr[4:0])
1'd0: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
end
//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:52
+// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:37
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
wire csrbank0_init_error0_r;
wire csrbank0_init_error0_we;
wire csrbank0_init_error0_w;
-reg csrbank0_sel = 1'd0;
+wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
wire [31:0] interface1_bank_bus_dat_w;
wire [1:0] csrbank1_dly_sel0_r;
wire csrbank1_dly_sel0_we;
wire [1:0] csrbank1_dly_sel0_w;
-reg csrbank1_sel = 1'd0;
+wire csrbank1_sel;
wire [13:0] interface2_bank_bus_adr;
wire interface2_bank_bus_we;
wire [31:0] interface2_bank_bus_dat_w;
wire [31:0] csrbank2_dfii_pi3_rddata_r;
wire csrbank2_dfii_pi3_rddata_we;
wire [31:0] csrbank2_dfii_pi3_rddata_w;
-reg csrbank2_sel = 1'd0;
+wire csrbank2_sel;
wire [13:0] adr;
wire we;
wire [31:0] dat_w;
reg dummy_d_1;
// synthesis translate_on
always @(*) begin
- litedramcore_adr <= 14'd0;
+ litedramcore_we <= 1'd0;
case (state)
1'd1: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr <= litedramcore_wishbone_adr;
+ litedramcore_we <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
end
end
endcase
reg dummy_d_2;
// synthesis translate_on
always @(*) begin
- litedramcore_we <= 1'd0;
+ litedramcore_wishbone_ack <= 1'd0;
case (state)
1'd1: begin
+ litedramcore_wishbone_ack <= 1'd1;
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we <= litedramcore_wishbone_we;
- end
end
endcase
// synthesis translate_off
reg dummy_d_3;
// synthesis translate_on
always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
+ litedramcore_adr <= 14'd0;
case (state)
1'd1: begin
- litedramcore_wishbone_ack <= 1'd1;
end
default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr <= litedramcore_wishbone_adr;
+ end
end
endcase
// synthesis translate_off
// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
-always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
- end
-// synthesis translate_off
- dummy_d_26 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_27;
-// synthesis translate_on
-always @(*) begin
- litedramcore_inti_p2_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- end else begin
- litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
-// synthesis translate_off
- dummy_d_27 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_28;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
- end
-// synthesis translate_off
- dummy_d_28 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_29;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
- end
-// synthesis translate_off
- dummy_d_29 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_30;
-// synthesis translate_on
always @(*) begin
litedramcore_master_p2_address <= 15'd0;
if (litedramcore_storage[0]) begin
litedramcore_master_p2_address <= litedramcore_inti_p2_address;
end
// synthesis translate_off
- dummy_d_30 = dummy_s;
+ dummy_d_26 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_31;
+reg dummy_d_27;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_bank <= 3'd0;
litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
end
// synthesis translate_off
- dummy_d_31 = dummy_s;
+ dummy_d_27 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_32;
+reg dummy_d_28;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_cas_n <= 1'd1;
litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
end
// synthesis translate_off
- dummy_d_32 = dummy_s;
+ dummy_d_28 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_33;
+reg dummy_d_29;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_cs_n <= 1'd1;
litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
end
// synthesis translate_off
- dummy_d_33 = dummy_s;
+ dummy_d_29 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_34;
+reg dummy_d_30;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_ras_n <= 1'd1;
litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
end
// synthesis translate_off
- dummy_d_34 = dummy_s;
+ dummy_d_30 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_35;
+reg dummy_d_31;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p2_rddata <= 32'd0;
end else begin
end
// synthesis translate_off
- dummy_d_35 = dummy_s;
+ dummy_d_31 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_36;
+reg dummy_d_32;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_we_n <= 1'd1;
litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
end
// synthesis translate_off
- dummy_d_36 = dummy_s;
+ dummy_d_32 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_37;
+reg dummy_d_33;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p2_rddata_valid <= 1'd0;
end else begin
end
// synthesis translate_off
- dummy_d_37 = dummy_s;
+ dummy_d_33 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_38;
+reg dummy_d_34;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_cke <= 1'd0;
litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
end
// synthesis translate_off
- dummy_d_38 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_39;
-// synthesis translate_on
-always @(*) begin
- litedramcore_inti_p2_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- end else begin
- litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
- end
-// synthesis translate_off
- dummy_d_39 = dummy_s;
+ dummy_d_34 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_40;
+reg dummy_d_35;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_odt <= 1'd0;
litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
end
// synthesis translate_off
- dummy_d_40 = dummy_s;
+ dummy_d_35 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_41;
+reg dummy_d_36;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_reset_n <= 1'd0;
litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
- dummy_d_41 = dummy_s;
+ dummy_d_36 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_42;
+reg dummy_d_37;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_act_n <= 1'd1;
litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
end
// synthesis translate_off
- dummy_d_42 = dummy_s;
+ dummy_d_37 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_43;
+reg dummy_d_38;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_wrdata <= 32'd0;
litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
end
// synthesis translate_off
- dummy_d_43 = dummy_s;
+ dummy_d_38 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_44;
+reg dummy_d_39;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_rddata <= 32'd0;
litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
end
// synthesis translate_off
- dummy_d_44 = dummy_s;
+ dummy_d_39 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_45;
+reg dummy_d_40;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_wrdata_en <= 1'd0;
litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
end
// synthesis translate_off
- dummy_d_45 = dummy_s;
+ dummy_d_40 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_46;
+reg dummy_d_41;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_rddata_valid <= 1'd0;
litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
- dummy_d_46 = dummy_s;
+ dummy_d_41 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_47;
+reg dummy_d_42;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_wrdata_mask <= 4'd0;
litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
end
// synthesis translate_off
- dummy_d_47 = dummy_s;
+ dummy_d_42 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_48;
+reg dummy_d_43;
// synthesis translate_on
always @(*) begin
litedramcore_master_p2_rddata_en <= 1'd0;
litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
- dummy_d_48 = dummy_s;
+ dummy_d_43 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_49;
+reg dummy_d_44;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_address <= 15'd0;
litedramcore_master_p3_address <= litedramcore_inti_p3_address;
end
// synthesis translate_off
- dummy_d_49 = dummy_s;
+ dummy_d_44 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_50;
+reg dummy_d_45;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_bank <= 3'd0;
litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
end
// synthesis translate_off
- dummy_d_50 = dummy_s;
+ dummy_d_45 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_51;
+reg dummy_d_46;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_cas_n <= 1'd1;
litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
- dummy_d_51 = dummy_s;
+ dummy_d_46 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_52;
+reg dummy_d_47;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_cs_n <= 1'd1;
litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
- dummy_d_52 = dummy_s;
+ dummy_d_47 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_53;
+reg dummy_d_48;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_ras_n <= 1'd1;
litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
end
// synthesis translate_off
- dummy_d_53 = dummy_s;
+ dummy_d_48 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_54;
+reg dummy_d_49;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p3_rddata <= 32'd0;
end else begin
end
// synthesis translate_off
- dummy_d_54 = dummy_s;
+ dummy_d_49 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_55;
+reg dummy_d_50;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_we_n <= 1'd1;
litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
end
// synthesis translate_off
- dummy_d_55 = dummy_s;
+ dummy_d_50 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_56;
+reg dummy_d_51;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p3_rddata_valid <= 1'd0;
end else begin
end
// synthesis translate_off
- dummy_d_56 = dummy_s;
+ dummy_d_51 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_57;
+reg dummy_d_52;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_cke <= 1'd0;
litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
end
// synthesis translate_off
- dummy_d_57 = dummy_s;
+ dummy_d_52 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_58;
+reg dummy_d_53;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_odt <= 1'd0;
litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
end
// synthesis translate_off
- dummy_d_58 = dummy_s;
+ dummy_d_53 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_59;
+reg dummy_d_54;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_reset_n <= 1'd0;
litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
end
// synthesis translate_off
- dummy_d_59 = dummy_s;
+ dummy_d_54 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_60;
+reg dummy_d_55;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_act_n <= 1'd1;
litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
end
// synthesis translate_off
- dummy_d_60 = dummy_s;
+ dummy_d_55 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_61;
+reg dummy_d_56;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_wrdata <= 32'd0;
litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
end
// synthesis translate_off
- dummy_d_61 = dummy_s;
+ dummy_d_56 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_62;
+reg dummy_d_57;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_rddata <= 32'd0;
litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
end
// synthesis translate_off
- dummy_d_62 = dummy_s;
+ dummy_d_57 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_63;
+reg dummy_d_58;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_wrdata_en <= 1'd0;
litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
end
// synthesis translate_off
- dummy_d_63 = dummy_s;
+ dummy_d_58 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_64;
+reg dummy_d_59;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_rddata_valid <= 1'd0;
litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end
// synthesis translate_off
- dummy_d_64 = dummy_s;
+ dummy_d_59 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_65;
+reg dummy_d_60;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_wrdata_mask <= 4'd0;
litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
end
// synthesis translate_off
- dummy_d_65 = dummy_s;
+ dummy_d_60 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_66;
+reg dummy_d_61;
// synthesis translate_on
always @(*) begin
litedramcore_master_p3_rddata_en <= 1'd0;
litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
end
// synthesis translate_off
- dummy_d_66 = dummy_s;
+ dummy_d_61 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_67;
+reg dummy_d_62;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_address <= 15'd0;
litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
- dummy_d_67 = dummy_s;
+ dummy_d_62 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_68;
+reg dummy_d_63;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_bank <= 3'd0;
litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
end
// synthesis translate_off
- dummy_d_68 = dummy_s;
+ dummy_d_63 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_69;
+reg dummy_d_64;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_cas_n <= 1'd1;
litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
- dummy_d_69 = dummy_s;
+ dummy_d_64 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_70;
+reg dummy_d_65;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_cs_n <= 1'd1;
litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
end
// synthesis translate_off
- dummy_d_70 = dummy_s;
+ dummy_d_65 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_71;
+reg dummy_d_66;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_ras_n <= 1'd1;
litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
end
// synthesis translate_off
- dummy_d_71 = dummy_s;
+ dummy_d_66 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_72;
+reg dummy_d_67;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p0_rddata <= 32'd0;
end else begin
end
// synthesis translate_off
- dummy_d_72 = dummy_s;
+ dummy_d_67 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_73;
+reg dummy_d_68;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_we_n <= 1'd1;
litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
end
// synthesis translate_off
- dummy_d_73 = dummy_s;
+ dummy_d_68 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_74;
+reg dummy_d_69;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p0_rddata_valid <= 1'd0;
end else begin
end
// synthesis translate_off
- dummy_d_74 = dummy_s;
+ dummy_d_69 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_75;
+reg dummy_d_70;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_cke <= 1'd0;
litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
end
// synthesis translate_off
- dummy_d_75 = dummy_s;
+ dummy_d_70 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_76;
+reg dummy_d_71;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_odt <= 1'd0;
litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
end
// synthesis translate_off
- dummy_d_76 = dummy_s;
+ dummy_d_71 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_77;
+reg dummy_d_72;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_reset_n <= 1'd0;
litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
end
// synthesis translate_off
- dummy_d_77 = dummy_s;
+ dummy_d_72 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_78;
+reg dummy_d_73;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_act_n <= 1'd1;
litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
end
// synthesis translate_off
- dummy_d_78 = dummy_s;
+ dummy_d_73 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_79;
+reg dummy_d_74;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_wrdata <= 32'd0;
litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
end
// synthesis translate_off
- dummy_d_79 = dummy_s;
+ dummy_d_74 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_80;
+reg dummy_d_75;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_rddata <= 32'd0;
litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
end
// synthesis translate_off
- dummy_d_80 = dummy_s;
+ dummy_d_75 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_81;
+reg dummy_d_76;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_wrdata_en <= 1'd0;
litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
end
// synthesis translate_off
- dummy_d_81 = dummy_s;
+ dummy_d_76 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_82;
+reg dummy_d_77;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_rddata_valid <= 1'd0;
litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end
// synthesis translate_off
- dummy_d_82 = dummy_s;
+ dummy_d_77 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_83;
+reg dummy_d_78;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_wrdata_mask <= 4'd0;
litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
end
// synthesis translate_off
- dummy_d_83 = dummy_s;
+ dummy_d_78 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_84;
+reg dummy_d_79;
// synthesis translate_on
always @(*) begin
litedramcore_master_p0_rddata_en <= 1'd0;
litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
- dummy_d_84 = dummy_s;
+ dummy_d_79 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_85;
+reg dummy_d_80;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_address <= 15'd0;
litedramcore_master_p1_address <= litedramcore_inti_p1_address;
end
// synthesis translate_off
- dummy_d_85 = dummy_s;
+ dummy_d_80 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_86;
+reg dummy_d_81;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_bank <= 3'd0;
litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
end
// synthesis translate_off
- dummy_d_86 = dummy_s;
+ dummy_d_81 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_87;
+reg dummy_d_82;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_cas_n <= 1'd1;
litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
- dummy_d_87 = dummy_s;
+ dummy_d_82 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_88;
+reg dummy_d_83;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_cs_n <= 1'd1;
litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
- dummy_d_88 = dummy_s;
+ dummy_d_83 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_89;
+reg dummy_d_84;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_ras_n <= 1'd1;
litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
end
// synthesis translate_off
- dummy_d_89 = dummy_s;
+ dummy_d_84 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_90;
+reg dummy_d_85;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p1_rddata <= 32'd0;
end else begin
end
// synthesis translate_off
- dummy_d_90 = dummy_s;
+ dummy_d_85 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_91;
+reg dummy_d_86;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_we_n <= 1'd1;
litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
end
// synthesis translate_off
- dummy_d_91 = dummy_s;
+ dummy_d_86 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_92;
+reg dummy_d_87;
// synthesis translate_on
always @(*) begin
litedramcore_slave_p1_rddata_valid <= 1'd0;
end else begin
end
// synthesis translate_off
- dummy_d_92 = dummy_s;
+ dummy_d_87 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_93;
+reg dummy_d_88;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_cke <= 1'd0;
litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
end
// synthesis translate_off
- dummy_d_93 = dummy_s;
+ dummy_d_88 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_94;
+reg dummy_d_89;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_inti_p2_rddata <= 32'd0;
+ if (litedramcore_storage[0]) begin
+ end else begin
+ litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+// synthesis translate_off
+ dummy_d_89 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_90;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_odt <= 1'd0;
litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
end
// synthesis translate_off
- dummy_d_94 = dummy_s;
+ dummy_d_90 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_95;
+reg dummy_d_91;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_reset_n <= 1'd0;
litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
- dummy_d_95 = dummy_s;
+ dummy_d_91 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_96;
+reg dummy_d_92;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_act_n <= 1'd1;
litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
end
// synthesis translate_off
- dummy_d_96 = dummy_s;
+ dummy_d_92 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_97;
+reg dummy_d_93;
// synthesis translate_on
always @(*) begin
litedramcore_master_p1_wrdata <= 32'd0;
end else begin
litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
end
+// synthesis translate_off
+ dummy_d_93 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_94;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+ end
+// synthesis translate_off
+ dummy_d_94 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_95;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_inti_p2_rddata_valid <= 1'd0;
+ if (litedramcore_storage[0]) begin
+ end else begin
+ litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+// synthesis translate_off
+ dummy_d_95 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_96;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+ end
+// synthesis translate_off
+ dummy_d_96 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_97;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
+ end
// synthesis translate_off
dummy_d_97 = dummy_s;
// synthesis translate_on
reg dummy_d_98;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cs_n <= 1'd1;
+ litedramcore_inti_p0_cas_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+ litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
end else begin
- litedramcore_inti_p0_cs_n <= {1{1'd1}};
+ litedramcore_inti_p0_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_98 = dummy_s;
reg dummy_d_99;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_ras_n <= 1'd1;
+ litedramcore_inti_p0_cs_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
+ litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
end else begin
- litedramcore_inti_p0_ras_n <= 1'd1;
+ litedramcore_inti_p0_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_99 = dummy_s;
reg dummy_d_100;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_we_n <= 1'd1;
+ litedramcore_inti_p0_ras_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
+ litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
end else begin
- litedramcore_inti_p0_we_n <= 1'd1;
+ litedramcore_inti_p0_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_100 = dummy_s;
reg dummy_d_101;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cas_n <= 1'd1;
+ litedramcore_inti_p0_we_n <= 1'd1;
if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
+ litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
end else begin
- litedramcore_inti_p0_cas_n <= 1'd1;
+ litedramcore_inti_p0_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_101 = dummy_s;
reg dummy_d_102;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cs_n <= 1'd1;
+ litedramcore_inti_p1_cas_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+ litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
end else begin
- litedramcore_inti_p1_cs_n <= {1{1'd1}};
+ litedramcore_inti_p1_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_102 = dummy_s;
reg dummy_d_103;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_ras_n <= 1'd1;
+ litedramcore_inti_p1_cs_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
+ litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
end else begin
- litedramcore_inti_p1_ras_n <= 1'd1;
+ litedramcore_inti_p1_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_103 = dummy_s;
reg dummy_d_104;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_we_n <= 1'd1;
+ litedramcore_inti_p1_ras_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
+ litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
end else begin
- litedramcore_inti_p1_we_n <= 1'd1;
+ litedramcore_inti_p1_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_104 = dummy_s;
reg dummy_d_105;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cas_n <= 1'd1;
+ litedramcore_inti_p1_we_n <= 1'd1;
if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
+ litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
end else begin
- litedramcore_inti_p1_cas_n <= 1'd1;
+ litedramcore_inti_p1_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_105 = dummy_s;
reg dummy_d_106;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cs_n <= 1'd1;
+ litedramcore_inti_p2_cas_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
+ litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
end else begin
- litedramcore_inti_p2_cs_n <= {1{1'd1}};
+ litedramcore_inti_p2_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_106 = dummy_s;
reg dummy_d_107;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_ras_n <= 1'd1;
+ litedramcore_inti_p2_cs_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
+ litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
end else begin
- litedramcore_inti_p2_ras_n <= 1'd1;
+ litedramcore_inti_p2_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_107 = dummy_s;
reg dummy_d_108;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_we_n <= 1'd1;
+ litedramcore_inti_p2_ras_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
+ litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
end else begin
- litedramcore_inti_p2_we_n <= 1'd1;
+ litedramcore_inti_p2_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_108 = dummy_s;
reg dummy_d_109;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cas_n <= 1'd1;
+ litedramcore_inti_p2_we_n <= 1'd1;
if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
+ litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
end else begin
- litedramcore_inti_p2_cas_n <= 1'd1;
+ litedramcore_inti_p2_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_109 = dummy_s;
reg dummy_d_110;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cs_n <= 1'd1;
+ litedramcore_inti_p3_cas_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
+ litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
end else begin
- litedramcore_inti_p3_cs_n <= {1{1'd1}};
+ litedramcore_inti_p3_cas_n <= 1'd1;
end
// synthesis translate_off
dummy_d_110 = dummy_s;
reg dummy_d_111;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_ras_n <= 1'd1;
+ litedramcore_inti_p3_cs_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
+ litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
end else begin
- litedramcore_inti_p3_ras_n <= 1'd1;
+ litedramcore_inti_p3_cs_n <= {1{1'd1}};
end
// synthesis translate_off
dummy_d_111 = dummy_s;
reg dummy_d_112;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_we_n <= 1'd1;
+ litedramcore_inti_p3_ras_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
+ litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
end else begin
- litedramcore_inti_p3_we_n <= 1'd1;
+ litedramcore_inti_p3_ras_n <= 1'd1;
end
// synthesis translate_off
dummy_d_112 = dummy_s;
reg dummy_d_113;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_cas_n <= 1'd1;
+ litedramcore_inti_p3_we_n <= 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
+ litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
end else begin
- litedramcore_inti_p3_cas_n <= 1'd1;
+ litedramcore_inti_p3_we_n <= 1'd1;
end
// synthesis translate_off
dummy_d_113 = dummy_s;
// synthesis translate_off
reg dummy_d_123;
// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_123 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_124;
-// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_row_close <= 1'd0;
case (bankmachine0_state)
end
endcase
// synthesis translate_off
- dummy_d_124 = dummy_s;
+ dummy_d_123 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_125;
+reg dummy_d_124;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_125 = dummy_s;
+ dummy_d_124 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_126;
+reg dummy_d_125;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_126 = dummy_s;
+ dummy_d_125 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_127;
+reg dummy_d_126;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_127 = dummy_s;
+ dummy_d_126 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_128;
+reg dummy_d_127;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_128 = dummy_s;
+ dummy_d_127 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_129;
+reg dummy_d_128;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_129 = dummy_s;
+ dummy_d_128 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_130;
+reg dummy_d_129;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_130 = dummy_s;
+ dummy_d_129 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_131;
+reg dummy_d_130;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_131 = dummy_s;
+ dummy_d_130 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_132;
+reg dummy_d_131;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_132 = dummy_s;
+ dummy_d_131 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_133;
+reg dummy_d_132;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_133 = dummy_s;
+ dummy_d_132 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_134;
+reg dummy_d_133;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_134 = dummy_s;
+ dummy_d_133 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_135;
+reg dummy_d_134;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_134 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_135;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_135 = dummy_s;
// synthesis translate_on
end
end
3'd5: begin
- bankmachine1_next_state <= 3'd6;
- end
- 3'd6: begin
- bankmachine1_next_state <= 2'd3;
- end
- 3'd7: begin
- bankmachine1_next_state <= 4'd8;
- end
- 4'd8: begin
- bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- bankmachine1_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- bankmachine1_next_state <= 2'd2;
- end
- end else begin
- bankmachine1_next_state <= 1'd1;
- end
- end else begin
- bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-// synthesis translate_off
- dummy_d_139 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_140;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
+ bankmachine1_next_state <= 3'd6;
end
3'd6: begin
+ bankmachine1_next_state <= 2'd3;
end
3'd7: begin
+ bankmachine1_next_state <= 4'd8;
end
4'd8: begin
+ bankmachine1_next_state <= 1'd0;
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_140 = dummy_s;
+ dummy_d_139 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_141;
+reg dummy_d_140;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_141 = dummy_s;
+ dummy_d_140 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_142;
+reg dummy_d_141;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_142 = dummy_s;
+ dummy_d_141 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_143;
+reg dummy_d_142;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_143 = dummy_s;
+ dummy_d_142 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_144;
+reg dummy_d_143;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_144 = dummy_s;
+ dummy_d_143 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_145;
+reg dummy_d_144;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_145 = dummy_s;
+ dummy_d_144 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_146;
+reg dummy_d_145;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_146 = dummy_s;
+ dummy_d_145 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_147;
+reg dummy_d_146;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_147 = dummy_s;
+ dummy_d_146 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_148;
+reg dummy_d_147;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_148 = dummy_s;
+ dummy_d_147 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_149;
+reg dummy_d_148;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_149 = dummy_s;
+ dummy_d_148 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_150;
+reg dummy_d_149;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_150 = dummy_s;
+ dummy_d_149 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_151;
+reg dummy_d_150;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_151 = dummy_s;
+ dummy_d_150 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_152;
+reg dummy_d_151;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_151 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_152;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_152 = dummy_s;
// synthesis translate_on
// synthesis translate_off
reg dummy_d_157;
// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_157 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_158;
-// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_row_close <= 1'd0;
case (bankmachine2_state)
end
endcase
// synthesis translate_off
- dummy_d_158 = dummy_s;
+ dummy_d_157 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_159;
+reg dummy_d_158;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_159 = dummy_s;
+ dummy_d_158 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_160;
+reg dummy_d_159;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_160 = dummy_s;
+ dummy_d_159 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_161;
+reg dummy_d_160;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_161 = dummy_s;
+ dummy_d_160 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_162;
+reg dummy_d_161;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_162 = dummy_s;
+ dummy_d_161 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_163;
+reg dummy_d_162;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_163 = dummy_s;
+ dummy_d_162 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_164;
+reg dummy_d_163;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_164 = dummy_s;
+ dummy_d_163 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_165;
+reg dummy_d_164;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_165 = dummy_s;
+ dummy_d_164 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_166;
+reg dummy_d_165;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_166 = dummy_s;
+ dummy_d_165 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_167;
+reg dummy_d_166;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_167 = dummy_s;
+ dummy_d_166 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_168;
+reg dummy_d_167;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_168 = dummy_s;
+ dummy_d_167 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_169;
+reg dummy_d_168;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_168 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_169;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_169 = dummy_s;
// synthesis translate_on
if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- bankmachine3_next_state <= 2'd2;
- end
- end else begin
- bankmachine3_next_state <= 1'd1;
- end
- end else begin
- bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-// synthesis translate_off
- dummy_d_173 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_174;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_174 = dummy_s;
+ dummy_d_173 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_175;
+reg dummy_d_174;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_175 = dummy_s;
+ dummy_d_174 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_176;
+reg dummy_d_175;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_176 = dummy_s;
+ dummy_d_175 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_177;
+reg dummy_d_176;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_177 = dummy_s;
+ dummy_d_176 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_178;
+reg dummy_d_177;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_178 = dummy_s;
+ dummy_d_177 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_179;
+reg dummy_d_178;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_179 = dummy_s;
+ dummy_d_178 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_180;
+reg dummy_d_179;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_180 = dummy_s;
+ dummy_d_179 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_181;
+reg dummy_d_180;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_181 = dummy_s;
+ dummy_d_180 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_182;
+reg dummy_d_181;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_182 = dummy_s;
+ dummy_d_181 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_183;
+reg dummy_d_182;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_183 = dummy_s;
+ dummy_d_182 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_184;
+reg dummy_d_183;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_184 = dummy_s;
+ dummy_d_183 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_185;
+reg dummy_d_184;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_185 = dummy_s;
+ dummy_d_184 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_186;
+reg dummy_d_185;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_185 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_186;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_186 = dummy_s;
// synthesis translate_on
// synthesis translate_off
reg dummy_d_191;
// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_191 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_192;
-// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_row_close <= 1'd0;
case (bankmachine4_state)
end
endcase
// synthesis translate_off
- dummy_d_192 = dummy_s;
+ dummy_d_191 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_193;
+reg dummy_d_192;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_193 = dummy_s;
+ dummy_d_192 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_194;
+reg dummy_d_193;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_194 = dummy_s;
+ dummy_d_193 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_195;
+reg dummy_d_194;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_195 = dummy_s;
+ dummy_d_194 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_196;
+reg dummy_d_195;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_196 = dummy_s;
+ dummy_d_195 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_197;
+reg dummy_d_196;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_197 = dummy_s;
+ dummy_d_196 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_198;
+reg dummy_d_197;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_198 = dummy_s;
+ dummy_d_197 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_199;
+reg dummy_d_198;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_199 = dummy_s;
+ dummy_d_198 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_200;
+reg dummy_d_199;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_200 = dummy_s;
+ dummy_d_199 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_201;
+reg dummy_d_200;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_201 = dummy_s;
+ dummy_d_200 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_202;
+reg dummy_d_201;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_202 = dummy_s;
+ dummy_d_201 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_203;
+reg dummy_d_202;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_202 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_203;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_203 = dummy_s;
// synthesis translate_on
end
end
3'd5: begin
- bankmachine5_next_state <= 3'd6;
- end
- 3'd6: begin
- bankmachine5_next_state <= 2'd3;
- end
- 3'd7: begin
- bankmachine5_next_state <= 4'd8;
- end
- 4'd8: begin
- bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- bankmachine5_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- bankmachine5_next_state <= 2'd2;
- end
- end else begin
- bankmachine5_next_state <= 1'd1;
- end
- end else begin
- bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-// synthesis translate_off
- dummy_d_207 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_208;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
+ bankmachine5_next_state <= 3'd6;
end
3'd6: begin
+ bankmachine5_next_state <= 2'd3;
end
3'd7: begin
+ bankmachine5_next_state <= 4'd8;
end
4'd8: begin
+ bankmachine5_next_state <= 1'd0;
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_208 = dummy_s;
+ dummy_d_207 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_209;
+reg dummy_d_208;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_209 = dummy_s;
+ dummy_d_208 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_210;
+reg dummy_d_209;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_210 = dummy_s;
+ dummy_d_209 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_211;
+reg dummy_d_210;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_211 = dummy_s;
+ dummy_d_210 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_212;
+reg dummy_d_211;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_212 = dummy_s;
+ dummy_d_211 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_213;
+reg dummy_d_212;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_213 = dummy_s;
+ dummy_d_212 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_214;
+reg dummy_d_213;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_214 = dummy_s;
+ dummy_d_213 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_215;
+reg dummy_d_214;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_215 = dummy_s;
+ dummy_d_214 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_216;
+reg dummy_d_215;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_216 = dummy_s;
+ dummy_d_215 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_217;
+reg dummy_d_216;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_217 = dummy_s;
+ dummy_d_216 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_218;
+reg dummy_d_217;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_218 = dummy_s;
+ dummy_d_217 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_219;
+reg dummy_d_218;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_219 = dummy_s;
+ dummy_d_218 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_220;
+reg dummy_d_219;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_219 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_220;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_220 = dummy_s;
// synthesis translate_on
// synthesis translate_off
reg dummy_d_225;
// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_225 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_226;
-// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_row_close <= 1'd0;
case (bankmachine6_state)
end
endcase
// synthesis translate_off
- dummy_d_226 = dummy_s;
+ dummy_d_225 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_227;
+reg dummy_d_226;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_227 = dummy_s;
+ dummy_d_226 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_228;
+reg dummy_d_227;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_228 = dummy_s;
+ dummy_d_227 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_229;
+reg dummy_d_228;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_229 = dummy_s;
+ dummy_d_228 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_230;
+reg dummy_d_229;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_230 = dummy_s;
+ dummy_d_229 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_231;
+reg dummy_d_230;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_231 = dummy_s;
+ dummy_d_230 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_232;
+reg dummy_d_231;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_232 = dummy_s;
+ dummy_d_231 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_233;
+reg dummy_d_232;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_233 = dummy_s;
+ dummy_d_232 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_234;
+reg dummy_d_233;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_234 = dummy_s;
+ dummy_d_233 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_235;
+reg dummy_d_234;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_235 = dummy_s;
+ dummy_d_234 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_236;
+reg dummy_d_235;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_236 = dummy_s;
+ dummy_d_235 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_237;
+reg dummy_d_236;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_236 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_237;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_237 = dummy_s;
// synthesis translate_on
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- bankmachine7_next_state <= 2'd2;
- end
- end else begin
- bankmachine7_next_state <= 1'd1;
- end
- end else begin
- bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-// synthesis translate_off
- dummy_d_241 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_242;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_242 = dummy_s;
+ dummy_d_241 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_243;
+reg dummy_d_242;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_243 = dummy_s;
+ dummy_d_242 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_244;
+reg dummy_d_243;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_244 = dummy_s;
+ dummy_d_243 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_245;
+reg dummy_d_244;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_245 = dummy_s;
+ dummy_d_244 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_246;
+reg dummy_d_245;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_246 = dummy_s;
+ dummy_d_245 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_247;
+reg dummy_d_246;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_247 = dummy_s;
+ dummy_d_246 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_248;
+reg dummy_d_247;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_248 = dummy_s;
+ dummy_d_247 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_249;
+reg dummy_d_248;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_249 = dummy_s;
+ dummy_d_248 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_250;
+reg dummy_d_249;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_250 = dummy_s;
+ dummy_d_249 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_251;
+reg dummy_d_250;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_251 = dummy_s;
+ dummy_d_250 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_252;
+reg dummy_d_251;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_252 = dummy_s;
+ dummy_d_251 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_253;
+reg dummy_d_252;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_253 = dummy_s;
+ dummy_d_252 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_254;
+reg dummy_d_253;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_valid <= 1'd0;
end
end
endcase
+// synthesis translate_off
+ dummy_d_253 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_254;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
// synthesis translate_off
dummy_d_254 = dummy_s;
// synthesis translate_on
reg dummy_d_272;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
+ litedramcore_steerer_sel0 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
+ litedramcore_steerer_sel0 <= 1'd0;
end
2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
+ litedramcore_steerer_sel0 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_273;
// synthesis translate_on
always @(*) begin
- litedramcore_en1 <= 1'd0;
+ litedramcore_steerer_sel1 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_en1 <= 1'd1;
+ litedramcore_steerer_sel1 <= 1'd0;
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ litedramcore_steerer_sel1 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_274;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
+ litedramcore_steerer_sel2 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
+ litedramcore_steerer_sel2 <= 1'd1;
end
2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel0 <= 1'd0;
+ litedramcore_steerer_sel2 <= 2'd2;
end
endcase
// synthesis translate_off
reg dummy_d_275;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
+ litedramcore_choose_cmd_want_activates <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel1 <= 1'd1;
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
end
endcase
// synthesis translate_off
reg dummy_d_276;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
+ litedramcore_steerer_sel3 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel2 <= 1'd1;
+ litedramcore_steerer_sel3 <= 2'd2;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel2 <= 2'd2;
+ litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_277;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
+ litedramcore_en0 <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
+ litedramcore_en0 <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_278;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
+ litedramcore_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel3 <= 2'd2;
end
2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_279;
// synthesis translate_on
always @(*) begin
- litedramcore_en0 <= 1'd0;
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_en0 <= 1'd1;
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
endcase
// synthesis translate_off
reg dummy_d_280;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
+ litedramcore_choose_req_want_reads <= 1'd0;
case (multiplexer_state)
1'd1: begin
end
2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_281;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ litedramcore_choose_req_want_writes <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
+ litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
end
endcase
// synthesis translate_off
reg dummy_d_282;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
+ litedramcore_en1 <= 1'd0;
case (multiplexer_state)
1'd1: begin
+ litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
reg dummy_d_283;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
+ litedramcore_choose_req_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
endcase
// synthesis translate_off
reg dummy_d_284;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
+ litedramcore_interface_wdata_we <= 16'd0;
case ({new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
end
default: begin
- litedramcore_interface_wdata <= 1'd0;
+ litedramcore_interface_wdata_we <= 1'd0;
end
endcase
// synthesis translate_off
reg dummy_d_285;
// synthesis translate_on
always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
+ litedramcore_interface_wdata <= 128'd0;
case ({new_master_wdata_ready2})
1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
end
default: begin
- litedramcore_interface_wdata_we <= 1'd0;
+ litedramcore_interface_wdata <= 1'd0;
end
endcase
// synthesis translate_off
assign litedramcore_wishbone_cti = wb_bus_cti;
assign litedramcore_wishbone_bte = wb_bus_bte;
assign wb_bus_err = litedramcore_wishbone_err;
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
-always @(*) begin
- csrbank0_sel <= 1'd0;
- csrbank0_sel <= (interface0_bank_bus_adr[13:9] == 2'd2);
- if (interface0_bank_bus_adr[0]) begin
- csrbank0_sel <= 1'd0;
- end
-// synthesis translate_off
- dummy_d_286 = dummy_s;
-// synthesis translate_on
-end
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
-assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
-assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
-always @(*) begin
- csrbank1_sel <= 1'd0;
- csrbank1_sel <= (interface1_bank_bus_adr[13:9] == 1'd0);
- if (interface1_bank_bus_adr[0]) begin
- csrbank1_sel <= 1'd0;
- end
-// synthesis translate_off
- dummy_d_287 = dummy_s;
-// synthesis translate_on
-end
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
-assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd0));
-assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd0));
+assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd0));
+assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd0));
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
-assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 1'd1));
-assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 1'd1));
+assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 1'd1));
+assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 1'd1));
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd2));
-assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd2));
+assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd2));
+assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd2));
assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 2'd3));
-assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 2'd3));
+assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 2'd3));
+assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 2'd3));
assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd4));
-assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd4));
+assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd4));
+assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd4));
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
-assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd5));
-assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd5));
+assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd5));
+assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd5));
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd6));
-assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd6));
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 3'd7));
-assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 3'd7));
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd8));
-assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd8));
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
-assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:1] == 4'd9));
-assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:1] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[3:0] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[3:0] == 4'd9));
assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
-always @(*) begin
- csrbank2_sel <= 1'd0;
- csrbank2_sel <= (interface2_bank_bus_adr[13:9] == 1'd1);
- if (interface2_bank_bus_adr[0]) begin
- csrbank2_sel <= 1'd0;
- end
-// synthesis translate_off
- dummy_d_288 = dummy_s;
-// synthesis translate_on
-end
+assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 1'd1);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
-assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd0));
-assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd0));
+assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd0));
+assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd0));
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 1'd1));
-assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 1'd1));
+assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 1'd1));
+assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd2));
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 2'd3));
-assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 2'd3));
+assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 2'd3));
+assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 2'd3));
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd4));
-assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd4));
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd5));
-assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd5));
assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd6));
-assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd6));
+assign csrbank2_dfii_pi0_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd6));
+assign csrbank2_dfii_pi0_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd6));
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 3'd7));
-assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 3'd7));
+assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 3'd7));
+assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 3'd7));
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd8));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd8));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd8));
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd9));
-assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd9));
+assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd9));
+assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd9));
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd10));
-assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd10));
+assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd10));
+assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd10));
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd11));
-assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd11));
+assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd11));
+assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd11));
assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd12));
-assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd12));
+assign csrbank2_dfii_pi1_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd12));
+assign csrbank2_dfii_pi1_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd12));
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd13));
-assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd13));
+assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd13));
+assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd13));
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd14));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd14));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd14));
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 4'd15));
-assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 4'd15));
+assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 4'd15));
+assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 4'd15));
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd16));
-assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd16));
+assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd16));
+assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd16));
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd17));
-assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd17));
+assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd17));
+assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd17));
assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd18));
-assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd18));
+assign csrbank2_dfii_pi2_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd18));
+assign csrbank2_dfii_pi2_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd18));
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
-assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd19));
-assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd19));
+assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd19));
+assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd19));
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd20));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd20));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd20));
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
-assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd21));
-assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd21));
+assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd21));
+assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd21));
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
-assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd22));
-assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd22));
+assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd22));
+assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd22));
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd23));
-assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd23));
+assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd23));
+assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd23));
assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
-assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[5:1] == 5'd24));
-assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[5:1] == 5'd24));
+assign csrbank2_dfii_pi3_rddata_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[4:0] == 5'd24));
+assign csrbank2_dfii_pi3_rddata_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[4:0] == 5'd24));
assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[14:0];
assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
// synthesis translate_off
-reg dummy_d_289;
+reg dummy_d_286;
// synthesis translate_on
always @(*) begin
rhs_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_289 = dummy_s;
+ dummy_d_286 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_290;
+reg dummy_d_287;
// synthesis translate_on
always @(*) begin
rhs_array_muxed1 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_290 = dummy_s;
+ dummy_d_287 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_291;
+reg dummy_d_288;
// synthesis translate_on
always @(*) begin
rhs_array_muxed2 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_291 = dummy_s;
+ dummy_d_288 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_292;
+reg dummy_d_289;
// synthesis translate_on
always @(*) begin
rhs_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_292 = dummy_s;
+ dummy_d_289 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_293;
+reg dummy_d_290;
// synthesis translate_on
always @(*) begin
rhs_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_293 = dummy_s;
+ dummy_d_290 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_294;
+reg dummy_d_291;
// synthesis translate_on
always @(*) begin
rhs_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_294 = dummy_s;
+ dummy_d_291 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_292;
// synthesis translate_on
always @(*) begin
t_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_295 = dummy_s;
+ dummy_d_292 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_293;
// synthesis translate_on
always @(*) begin
t_array_muxed1 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_296 = dummy_s;
+ dummy_d_293 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_297;
+reg dummy_d_294;
// synthesis translate_on
always @(*) begin
t_array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_297 = dummy_s;
+ dummy_d_294 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_298;
+reg dummy_d_295;
// synthesis translate_on
always @(*) begin
rhs_array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_298 = dummy_s;
+ dummy_d_295 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_299;
+reg dummy_d_296;
// synthesis translate_on
always @(*) begin
rhs_array_muxed7 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_299 = dummy_s;
+ dummy_d_296 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_300;
+reg dummy_d_297;
// synthesis translate_on
always @(*) begin
rhs_array_muxed8 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_300 = dummy_s;
+ dummy_d_297 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_301;
+reg dummy_d_298;
// synthesis translate_on
always @(*) begin
rhs_array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_301 = dummy_s;
+ dummy_d_298 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_302;
+reg dummy_d_299;
// synthesis translate_on
always @(*) begin
rhs_array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_302 = dummy_s;
+ dummy_d_299 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_303;
+reg dummy_d_300;
// synthesis translate_on
always @(*) begin
rhs_array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_303 = dummy_s;
+ dummy_d_300 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_304;
+reg dummy_d_301;
// synthesis translate_on
always @(*) begin
t_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_304 = dummy_s;
+ dummy_d_301 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_305;
+reg dummy_d_302;
// synthesis translate_on
always @(*) begin
t_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_305 = dummy_s;
+ dummy_d_302 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_306;
+reg dummy_d_303;
// synthesis translate_on
always @(*) begin
t_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_306 = dummy_s;
+ dummy_d_303 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_307;
+reg dummy_d_304;
// synthesis translate_on
always @(*) begin
rhs_array_muxed12 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_307 = dummy_s;
+ dummy_d_304 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_308;
+reg dummy_d_305;
// synthesis translate_on
always @(*) begin
rhs_array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_308 = dummy_s;
+ dummy_d_305 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_309;
+reg dummy_d_306;
// synthesis translate_on
always @(*) begin
rhs_array_muxed14 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_309 = dummy_s;
+ dummy_d_306 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_310;
+reg dummy_d_307;
// synthesis translate_on
always @(*) begin
rhs_array_muxed15 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_310 = dummy_s;
+ dummy_d_307 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_311;
+reg dummy_d_308;
// synthesis translate_on
always @(*) begin
rhs_array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_311 = dummy_s;
+ dummy_d_308 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_312;
+reg dummy_d_309;
// synthesis translate_on
always @(*) begin
rhs_array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_312 = dummy_s;
+ dummy_d_309 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_313;
+reg dummy_d_310;
// synthesis translate_on
always @(*) begin
rhs_array_muxed18 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_313 = dummy_s;
+ dummy_d_310 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_314;
+reg dummy_d_311;
// synthesis translate_on
always @(*) begin
rhs_array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_314 = dummy_s;
+ dummy_d_311 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_315;
+reg dummy_d_312;
// synthesis translate_on
always @(*) begin
rhs_array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_315 = dummy_s;
+ dummy_d_312 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_316;
+reg dummy_d_313;
// synthesis translate_on
always @(*) begin
rhs_array_muxed21 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_316 = dummy_s;
+ dummy_d_313 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_317;
+reg dummy_d_314;
// synthesis translate_on
always @(*) begin
rhs_array_muxed22 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_317 = dummy_s;
+ dummy_d_314 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_318;
+reg dummy_d_315;
// synthesis translate_on
always @(*) begin
rhs_array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_318 = dummy_s;
+ dummy_d_315 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_319;
+reg dummy_d_316;
// synthesis translate_on
always @(*) begin
rhs_array_muxed24 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_319 = dummy_s;
+ dummy_d_316 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_320;
+reg dummy_d_317;
// synthesis translate_on
always @(*) begin
rhs_array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_320 = dummy_s;
+ dummy_d_317 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_321;
+reg dummy_d_318;
// synthesis translate_on
always @(*) begin
rhs_array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_321 = dummy_s;
+ dummy_d_318 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_322;
+reg dummy_d_319;
// synthesis translate_on
always @(*) begin
rhs_array_muxed27 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_322 = dummy_s;
+ dummy_d_319 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_323;
+reg dummy_d_320;
// synthesis translate_on
always @(*) begin
rhs_array_muxed28 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_323 = dummy_s;
+ dummy_d_320 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_324;
+reg dummy_d_321;
// synthesis translate_on
always @(*) begin
rhs_array_muxed29 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_324 = dummy_s;
+ dummy_d_321 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_325;
+reg dummy_d_322;
// synthesis translate_on
always @(*) begin
rhs_array_muxed30 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_325 = dummy_s;
+ dummy_d_322 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_326;
+reg dummy_d_323;
// synthesis translate_on
always @(*) begin
rhs_array_muxed31 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_326 = dummy_s;
+ dummy_d_323 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_327;
+reg dummy_d_324;
// synthesis translate_on
always @(*) begin
rhs_array_muxed32 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_327 = dummy_s;
+ dummy_d_324 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_328;
+reg dummy_d_325;
// synthesis translate_on
always @(*) begin
rhs_array_muxed33 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_328 = dummy_s;
+ dummy_d_325 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_329;
+reg dummy_d_326;
// synthesis translate_on
always @(*) begin
rhs_array_muxed34 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_329 = dummy_s;
+ dummy_d_326 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_330;
+reg dummy_d_327;
// synthesis translate_on
always @(*) begin
rhs_array_muxed35 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_330 = dummy_s;
+ dummy_d_327 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_331;
+reg dummy_d_328;
// synthesis translate_on
always @(*) begin
array_muxed0 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_331 = dummy_s;
+ dummy_d_328 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_332;
+reg dummy_d_329;
// synthesis translate_on
always @(*) begin
array_muxed1 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_332 = dummy_s;
+ dummy_d_329 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_333;
+reg dummy_d_330;
// synthesis translate_on
always @(*) begin
array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_333 = dummy_s;
+ dummy_d_330 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_334;
+reg dummy_d_331;
// synthesis translate_on
always @(*) begin
array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_334 = dummy_s;
+ dummy_d_331 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_335;
+reg dummy_d_332;
// synthesis translate_on
always @(*) begin
array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_335 = dummy_s;
+ dummy_d_332 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_336;
+reg dummy_d_333;
// synthesis translate_on
always @(*) begin
array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_336 = dummy_s;
+ dummy_d_333 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_337;
+reg dummy_d_334;
// synthesis translate_on
always @(*) begin
array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_337 = dummy_s;
+ dummy_d_334 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_338;
+reg dummy_d_335;
// synthesis translate_on
always @(*) begin
array_muxed7 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_338 = dummy_s;
+ dummy_d_335 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_339;
+reg dummy_d_336;
// synthesis translate_on
always @(*) begin
array_muxed8 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_339 = dummy_s;
+ dummy_d_336 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_340;
+reg dummy_d_337;
// synthesis translate_on
always @(*) begin
array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_340 = dummy_s;
+ dummy_d_337 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_341;
+reg dummy_d_338;
// synthesis translate_on
always @(*) begin
array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_341 = dummy_s;
+ dummy_d_338 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_342;
+reg dummy_d_339;
// synthesis translate_on
always @(*) begin
array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_342 = dummy_s;
+ dummy_d_339 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_343;
+reg dummy_d_340;
// synthesis translate_on
always @(*) begin
array_muxed12 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_343 = dummy_s;
+ dummy_d_340 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_344;
+reg dummy_d_341;
// synthesis translate_on
always @(*) begin
array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_344 = dummy_s;
+ dummy_d_341 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_345;
+reg dummy_d_342;
// synthesis translate_on
always @(*) begin
array_muxed14 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_345 = dummy_s;
+ dummy_d_342 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_346;
+reg dummy_d_343;
// synthesis translate_on
always @(*) begin
array_muxed15 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_346 = dummy_s;
+ dummy_d_343 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_347;
+reg dummy_d_344;
// synthesis translate_on
always @(*) begin
array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_347 = dummy_s;
+ dummy_d_344 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_348;
+reg dummy_d_345;
// synthesis translate_on
always @(*) begin
array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_348 = dummy_s;
+ dummy_d_345 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_349;
+reg dummy_d_346;
// synthesis translate_on
always @(*) begin
array_muxed18 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_349 = dummy_s;
+ dummy_d_346 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_350;
+reg dummy_d_347;
// synthesis translate_on
always @(*) begin
array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_350 = dummy_s;
+ dummy_d_347 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_351;
+reg dummy_d_348;
// synthesis translate_on
always @(*) begin
array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_351 = dummy_s;
+ dummy_d_348 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_352;
+reg dummy_d_349;
// synthesis translate_on
always @(*) begin
array_muxed21 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_352 = dummy_s;
+ dummy_d_349 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_353;
+reg dummy_d_350;
// synthesis translate_on
always @(*) begin
array_muxed22 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_353 = dummy_s;
+ dummy_d_350 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_354;
+reg dummy_d_351;
// synthesis translate_on
always @(*) begin
array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_354 = dummy_s;
+ dummy_d_351 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_355;
+reg dummy_d_352;
// synthesis translate_on
always @(*) begin
array_muxed24 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_355 = dummy_s;
+ dummy_d_352 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_356;
+reg dummy_d_353;
// synthesis translate_on
always @(*) begin
array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_356 = dummy_s;
+ dummy_d_353 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_357;
+reg dummy_d_354;
// synthesis translate_on
always @(*) begin
array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_357 = dummy_s;
+ dummy_d_354 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_358;
+reg dummy_d_355;
// synthesis translate_on
always @(*) begin
array_muxed27 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_358 = dummy_s;
+ dummy_d_355 = dummy_s;
// synthesis translate_on
end
assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
new_master_rdata_valid8 <= new_master_rdata_valid7;
interface0_bank_bus_dat_r <= 1'd0;
if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[1])
+ case (interface0_bank_bus_adr[0])
1'd0: begin
interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
end
init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[4:1])
+ case (interface1_bank_bus_adr[3:0])
1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
end
a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
interface2_bank_bus_dat_r <= 1'd0;
if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[5:1])
+ case (interface2_bank_bus_adr[4:0])
1'd0: begin
interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
end
//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:54
+// Auto-generated by Migen (b1b2b29) & LiteX (6239eac1) on 2020-06-02 11:27:39
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
reg [13:0] litedramcore_adr = 14'd0;
reg litedramcore_we = 1'd0;
-wire [31:0] litedramcore_dat_w;
-wire [31:0] litedramcore_dat_r;
+wire [7:0] litedramcore_dat_w;
+wire [7:0] litedramcore_dat_r;
wire [29:0] litedramcore_wishbone_adr;
wire [31:0] litedramcore_wishbone_dat_w;
wire [31:0] litedramcore_wishbone_dat_r;
reg ddrphy_dfiphasemodel3_precharge = 1'd0;
reg ddrphy_dfiphasemodel3_write = 1'd0;
reg ddrphy_dfiphasemodel3_read = 1'd0;
-reg [63:0] ddrphy_dfitimingschecker_cnt = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker0 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker1 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker2 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker3 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker4 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker5 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker6 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker7 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker8 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker9 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker10 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker11 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker12 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker13 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker14 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker15 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker16 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker17 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker18 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker19 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker20 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker21 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker22 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker23 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker24 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker25 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker26 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker27 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker28 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker29 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker30 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker31 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker32 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker33 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker34 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker35 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker36 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker37 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker38 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker39 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker40 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker41 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker42 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker43 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker44 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker45 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker46 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_dfitimingschecker47 = 64'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd0 = 4'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd1 = 4'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd2 = 4'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd3 = 4'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd4 = 4'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd5 = 4'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd6 = 4'd0;
-reg [3:0] ddrphy_dfitimingschecker_last_cmd7 = 4'd0;
-reg [63:0] ddrphy_dfitimingschecker0 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker1 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker2 = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker3 = 64'd0;
-reg [1:0] ddrphy_dfitimingschecker_act_curr = 2'd0;
-reg [3:0] ddrphy_dfitimingschecker_ref_issued = 4'd0;
-wire [63:0] ddrphy_dfitimingschecker_ps0;
-wire [3:0] ddrphy_dfitimingschecker_state0;
-wire ddrphy_dfitimingschecker_all_banks0;
-wire ddrphy_dfitimingschecker_cmd_recv0;
-wire ddrphy_dfitimingschecker_cmd_recv1;
-wire ddrphy_dfitimingschecker_cmd_recv2;
-wire [1:0] ddrphy_dfitimingschecker_act_next0;
-wire ddrphy_dfitimingschecker_cmd_recv3;
-wire ddrphy_dfitimingschecker_cmd_recv4;
-wire ddrphy_dfitimingschecker_cmd_recv5;
-wire ddrphy_dfitimingschecker_cmd_recv6;
-wire ddrphy_dfitimingschecker_cmd_recv7;
-wire ddrphy_dfitimingschecker_cmd_recv8;
-wire [1:0] ddrphy_dfitimingschecker_act_next1;
-wire ddrphy_dfitimingschecker_cmd_recv9;
-wire ddrphy_dfitimingschecker_cmd_recv10;
-wire ddrphy_dfitimingschecker_cmd_recv11;
-wire ddrphy_dfitimingschecker_cmd_recv12;
-wire ddrphy_dfitimingschecker_cmd_recv13;
-wire ddrphy_dfitimingschecker_cmd_recv14;
-wire [1:0] ddrphy_dfitimingschecker_act_next2;
-wire ddrphy_dfitimingschecker_cmd_recv15;
-wire ddrphy_dfitimingschecker_cmd_recv16;
-wire ddrphy_dfitimingschecker_cmd_recv17;
-wire ddrphy_dfitimingschecker_cmd_recv18;
-wire ddrphy_dfitimingschecker_cmd_recv19;
-wire ddrphy_dfitimingschecker_cmd_recv20;
-wire [1:0] ddrphy_dfitimingschecker_act_next3;
-wire ddrphy_dfitimingschecker_cmd_recv21;
-wire ddrphy_dfitimingschecker_cmd_recv22;
-wire ddrphy_dfitimingschecker_cmd_recv23;
-wire ddrphy_dfitimingschecker_cmd_recv24;
-wire ddrphy_dfitimingschecker_cmd_recv25;
-wire ddrphy_dfitimingschecker_cmd_recv26;
-wire [1:0] ddrphy_dfitimingschecker_act_next4;
-wire ddrphy_dfitimingschecker_cmd_recv27;
-wire ddrphy_dfitimingschecker_cmd_recv28;
-wire ddrphy_dfitimingschecker_cmd_recv29;
-wire ddrphy_dfitimingschecker_cmd_recv30;
-wire ddrphy_dfitimingschecker_cmd_recv31;
-wire ddrphy_dfitimingschecker_cmd_recv32;
-wire [1:0] ddrphy_dfitimingschecker_act_next5;
-wire ddrphy_dfitimingschecker_cmd_recv33;
-wire ddrphy_dfitimingschecker_cmd_recv34;
-wire ddrphy_dfitimingschecker_cmd_recv35;
-wire ddrphy_dfitimingschecker_cmd_recv36;
-wire ddrphy_dfitimingschecker_cmd_recv37;
-wire ddrphy_dfitimingschecker_cmd_recv38;
-wire [1:0] ddrphy_dfitimingschecker_act_next6;
-wire ddrphy_dfitimingschecker_cmd_recv39;
-wire ddrphy_dfitimingschecker_cmd_recv40;
-wire ddrphy_dfitimingschecker_cmd_recv41;
-wire ddrphy_dfitimingschecker_cmd_recv42;
-wire ddrphy_dfitimingschecker_cmd_recv43;
-wire ddrphy_dfitimingschecker_cmd_recv44;
-wire [1:0] ddrphy_dfitimingschecker_act_next7;
-wire ddrphy_dfitimingschecker_cmd_recv45;
-wire ddrphy_dfitimingschecker_cmd_recv46;
-wire ddrphy_dfitimingschecker_cmd_recv47;
-wire [63:0] ddrphy_dfitimingschecker_ps1;
-wire [3:0] ddrphy_dfitimingschecker_state1;
-wire ddrphy_dfitimingschecker_all_banks1;
-wire ddrphy_dfitimingschecker_cmd_recv48;
-wire ddrphy_dfitimingschecker_cmd_recv49;
-wire ddrphy_dfitimingschecker_cmd_recv50;
-wire [1:0] ddrphy_dfitimingschecker_act_next8;
-wire ddrphy_dfitimingschecker_cmd_recv51;
-wire ddrphy_dfitimingschecker_cmd_recv52;
-wire ddrphy_dfitimingschecker_cmd_recv53;
-wire ddrphy_dfitimingschecker_cmd_recv54;
-wire ddrphy_dfitimingschecker_cmd_recv55;
-wire ddrphy_dfitimingschecker_cmd_recv56;
-wire [1:0] ddrphy_dfitimingschecker_act_next9;
-wire ddrphy_dfitimingschecker_cmd_recv57;
-wire ddrphy_dfitimingschecker_cmd_recv58;
-wire ddrphy_dfitimingschecker_cmd_recv59;
-wire ddrphy_dfitimingschecker_cmd_recv60;
-wire ddrphy_dfitimingschecker_cmd_recv61;
-wire ddrphy_dfitimingschecker_cmd_recv62;
-wire [1:0] ddrphy_dfitimingschecker_act_next10;
-wire ddrphy_dfitimingschecker_cmd_recv63;
-wire ddrphy_dfitimingschecker_cmd_recv64;
-wire ddrphy_dfitimingschecker_cmd_recv65;
-wire ddrphy_dfitimingschecker_cmd_recv66;
-wire ddrphy_dfitimingschecker_cmd_recv67;
-wire ddrphy_dfitimingschecker_cmd_recv68;
-wire [1:0] ddrphy_dfitimingschecker_act_next11;
-wire ddrphy_dfitimingschecker_cmd_recv69;
-wire ddrphy_dfitimingschecker_cmd_recv70;
-wire ddrphy_dfitimingschecker_cmd_recv71;
-wire ddrphy_dfitimingschecker_cmd_recv72;
-wire ddrphy_dfitimingschecker_cmd_recv73;
-wire ddrphy_dfitimingschecker_cmd_recv74;
-wire [1:0] ddrphy_dfitimingschecker_act_next12;
-wire ddrphy_dfitimingschecker_cmd_recv75;
-wire ddrphy_dfitimingschecker_cmd_recv76;
-wire ddrphy_dfitimingschecker_cmd_recv77;
-wire ddrphy_dfitimingschecker_cmd_recv78;
-wire ddrphy_dfitimingschecker_cmd_recv79;
-wire ddrphy_dfitimingschecker_cmd_recv80;
-wire [1:0] ddrphy_dfitimingschecker_act_next13;
-wire ddrphy_dfitimingschecker_cmd_recv81;
-wire ddrphy_dfitimingschecker_cmd_recv82;
-wire ddrphy_dfitimingschecker_cmd_recv83;
-wire ddrphy_dfitimingschecker_cmd_recv84;
-wire ddrphy_dfitimingschecker_cmd_recv85;
-wire ddrphy_dfitimingschecker_cmd_recv86;
-wire [1:0] ddrphy_dfitimingschecker_act_next14;
-wire ddrphy_dfitimingschecker_cmd_recv87;
-wire ddrphy_dfitimingschecker_cmd_recv88;
-wire ddrphy_dfitimingschecker_cmd_recv89;
-wire ddrphy_dfitimingschecker_cmd_recv90;
-wire ddrphy_dfitimingschecker_cmd_recv91;
-wire ddrphy_dfitimingschecker_cmd_recv92;
-wire [1:0] ddrphy_dfitimingschecker_act_next15;
-wire ddrphy_dfitimingschecker_cmd_recv93;
-wire ddrphy_dfitimingschecker_cmd_recv94;
-wire ddrphy_dfitimingschecker_cmd_recv95;
-wire [63:0] ddrphy_dfitimingschecker_ps2;
-wire [3:0] ddrphy_dfitimingschecker_state2;
-wire ddrphy_dfitimingschecker_all_banks2;
-wire ddrphy_dfitimingschecker_cmd_recv96;
-wire ddrphy_dfitimingschecker_cmd_recv97;
-wire ddrphy_dfitimingschecker_cmd_recv98;
-wire [1:0] ddrphy_dfitimingschecker_act_next16;
-wire ddrphy_dfitimingschecker_cmd_recv99;
-wire ddrphy_dfitimingschecker_cmd_recv100;
-wire ddrphy_dfitimingschecker_cmd_recv101;
-wire ddrphy_dfitimingschecker_cmd_recv102;
-wire ddrphy_dfitimingschecker_cmd_recv103;
-wire ddrphy_dfitimingschecker_cmd_recv104;
-wire [1:0] ddrphy_dfitimingschecker_act_next17;
-wire ddrphy_dfitimingschecker_cmd_recv105;
-wire ddrphy_dfitimingschecker_cmd_recv106;
-wire ddrphy_dfitimingschecker_cmd_recv107;
-wire ddrphy_dfitimingschecker_cmd_recv108;
-wire ddrphy_dfitimingschecker_cmd_recv109;
-wire ddrphy_dfitimingschecker_cmd_recv110;
-wire [1:0] ddrphy_dfitimingschecker_act_next18;
-wire ddrphy_dfitimingschecker_cmd_recv111;
-wire ddrphy_dfitimingschecker_cmd_recv112;
-wire ddrphy_dfitimingschecker_cmd_recv113;
-wire ddrphy_dfitimingschecker_cmd_recv114;
-wire ddrphy_dfitimingschecker_cmd_recv115;
-wire ddrphy_dfitimingschecker_cmd_recv116;
-wire [1:0] ddrphy_dfitimingschecker_act_next19;
-wire ddrphy_dfitimingschecker_cmd_recv117;
-wire ddrphy_dfitimingschecker_cmd_recv118;
-wire ddrphy_dfitimingschecker_cmd_recv119;
-wire ddrphy_dfitimingschecker_cmd_recv120;
-wire ddrphy_dfitimingschecker_cmd_recv121;
-wire ddrphy_dfitimingschecker_cmd_recv122;
-wire [1:0] ddrphy_dfitimingschecker_act_next20;
-wire ddrphy_dfitimingschecker_cmd_recv123;
-wire ddrphy_dfitimingschecker_cmd_recv124;
-wire ddrphy_dfitimingschecker_cmd_recv125;
-wire ddrphy_dfitimingschecker_cmd_recv126;
-wire ddrphy_dfitimingschecker_cmd_recv127;
-wire ddrphy_dfitimingschecker_cmd_recv128;
-wire [1:0] ddrphy_dfitimingschecker_act_next21;
-wire ddrphy_dfitimingschecker_cmd_recv129;
-wire ddrphy_dfitimingschecker_cmd_recv130;
-wire ddrphy_dfitimingschecker_cmd_recv131;
-wire ddrphy_dfitimingschecker_cmd_recv132;
-wire ddrphy_dfitimingschecker_cmd_recv133;
-wire ddrphy_dfitimingschecker_cmd_recv134;
-wire [1:0] ddrphy_dfitimingschecker_act_next22;
-wire ddrphy_dfitimingschecker_cmd_recv135;
-wire ddrphy_dfitimingschecker_cmd_recv136;
-wire ddrphy_dfitimingschecker_cmd_recv137;
-wire ddrphy_dfitimingschecker_cmd_recv138;
-wire ddrphy_dfitimingschecker_cmd_recv139;
-wire ddrphy_dfitimingschecker_cmd_recv140;
-wire [1:0] ddrphy_dfitimingschecker_act_next23;
-wire ddrphy_dfitimingschecker_cmd_recv141;
-wire ddrphy_dfitimingschecker_cmd_recv142;
-wire ddrphy_dfitimingschecker_cmd_recv143;
-wire [63:0] ddrphy_dfitimingschecker_ps3;
-wire [3:0] ddrphy_dfitimingschecker_state3;
-wire ddrphy_dfitimingschecker_all_banks3;
-wire ddrphy_dfitimingschecker_cmd_recv144;
-wire ddrphy_dfitimingschecker_cmd_recv145;
-wire ddrphy_dfitimingschecker_cmd_recv146;
-wire [1:0] ddrphy_dfitimingschecker_act_next24;
-wire ddrphy_dfitimingschecker_cmd_recv147;
-wire ddrphy_dfitimingschecker_cmd_recv148;
-wire ddrphy_dfitimingschecker_cmd_recv149;
-wire ddrphy_dfitimingschecker_cmd_recv150;
-wire ddrphy_dfitimingschecker_cmd_recv151;
-wire ddrphy_dfitimingschecker_cmd_recv152;
-wire [1:0] ddrphy_dfitimingschecker_act_next25;
-wire ddrphy_dfitimingschecker_cmd_recv153;
-wire ddrphy_dfitimingschecker_cmd_recv154;
-wire ddrphy_dfitimingschecker_cmd_recv155;
-wire ddrphy_dfitimingschecker_cmd_recv156;
-wire ddrphy_dfitimingschecker_cmd_recv157;
-wire ddrphy_dfitimingschecker_cmd_recv158;
-wire [1:0] ddrphy_dfitimingschecker_act_next26;
-wire ddrphy_dfitimingschecker_cmd_recv159;
-wire ddrphy_dfitimingschecker_cmd_recv160;
-wire ddrphy_dfitimingschecker_cmd_recv161;
-wire ddrphy_dfitimingschecker_cmd_recv162;
-wire ddrphy_dfitimingschecker_cmd_recv163;
-wire ddrphy_dfitimingschecker_cmd_recv164;
-wire [1:0] ddrphy_dfitimingschecker_act_next27;
-wire ddrphy_dfitimingschecker_cmd_recv165;
-wire ddrphy_dfitimingschecker_cmd_recv166;
-wire ddrphy_dfitimingschecker_cmd_recv167;
-wire ddrphy_dfitimingschecker_cmd_recv168;
-wire ddrphy_dfitimingschecker_cmd_recv169;
-wire ddrphy_dfitimingschecker_cmd_recv170;
-wire [1:0] ddrphy_dfitimingschecker_act_next28;
-wire ddrphy_dfitimingschecker_cmd_recv171;
-wire ddrphy_dfitimingschecker_cmd_recv172;
-wire ddrphy_dfitimingschecker_cmd_recv173;
-wire ddrphy_dfitimingschecker_cmd_recv174;
-wire ddrphy_dfitimingschecker_cmd_recv175;
-wire ddrphy_dfitimingschecker_cmd_recv176;
-wire [1:0] ddrphy_dfitimingschecker_act_next29;
-wire ddrphy_dfitimingschecker_cmd_recv177;
-wire ddrphy_dfitimingschecker_cmd_recv178;
-wire ddrphy_dfitimingschecker_cmd_recv179;
-wire ddrphy_dfitimingschecker_cmd_recv180;
-wire ddrphy_dfitimingschecker_cmd_recv181;
-wire ddrphy_dfitimingschecker_cmd_recv182;
-wire [1:0] ddrphy_dfitimingschecker_act_next30;
-wire ddrphy_dfitimingschecker_cmd_recv183;
-wire ddrphy_dfitimingschecker_cmd_recv184;
-wire ddrphy_dfitimingschecker_cmd_recv185;
-wire ddrphy_dfitimingschecker_cmd_recv186;
-wire ddrphy_dfitimingschecker_cmd_recv187;
-wire ddrphy_dfitimingschecker_cmd_recv188;
-wire [1:0] ddrphy_dfitimingschecker_act_next31;
-wire ddrphy_dfitimingschecker_cmd_recv189;
-wire ddrphy_dfitimingschecker_cmd_recv190;
-wire ddrphy_dfitimingschecker_cmd_recv191;
-reg [63:0] ddrphy_dfitimingschecker_ref_ps = 64'd0;
-reg [63:0] ddrphy_dfitimingschecker_ref_ps_mod = 64'd0;
-reg signed [63:0] ddrphy_dfitimingschecker_ref_ps_diff = 64'd0;
-wire signed [63:0] ddrphy_dfitimingschecker_curr_diff;
-reg ddrphy_dfitimingschecker_ref_done = 1'd0;
reg ddrphy_bankmodel0_activate = 1'd0;
reg [13:0] ddrphy_bankmodel0_activate_row = 14'd0;
reg ddrphy_bankmodel0_precharge = 1'd0;
reg new_master_rdata_valid9 = 1'd0;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+wire [7:0] interface0_bank_bus_dat_w;
+reg [7:0] interface0_bank_bus_dat_r = 8'd0;
wire csrbank0_init_done0_re;
wire csrbank0_init_done0_r;
wire csrbank0_init_done0_we;
wire csrbank0_init_error0_r;
wire csrbank0_init_error0_we;
wire csrbank0_init_error0_w;
-reg csrbank0_sel = 1'd0;
+wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+wire [7:0] interface1_bank_bus_dat_w;
+reg [7:0] interface1_bank_bus_dat_r = 8'd0;
wire csrbank1_dfii_control0_re;
wire [3:0] csrbank1_dfii_control0_r;
wire csrbank1_dfii_control0_we;
wire [5:0] csrbank1_dfii_pi0_command0_r;
wire csrbank1_dfii_pi0_command0_we;
wire [5:0] csrbank1_dfii_pi0_command0_w;
+wire csrbank1_dfii_pi0_address1_re;
+wire [5:0] csrbank1_dfii_pi0_address1_r;
+wire csrbank1_dfii_pi0_address1_we;
+wire [5:0] csrbank1_dfii_pi0_address1_w;
wire csrbank1_dfii_pi0_address0_re;
-wire [13:0] csrbank1_dfii_pi0_address0_r;
+wire [7:0] csrbank1_dfii_pi0_address0_r;
wire csrbank1_dfii_pi0_address0_we;
-wire [13:0] csrbank1_dfii_pi0_address0_w;
+wire [7:0] csrbank1_dfii_pi0_address0_w;
wire csrbank1_dfii_pi0_baddress0_re;
wire [2:0] csrbank1_dfii_pi0_baddress0_r;
wire csrbank1_dfii_pi0_baddress0_we;
wire [2:0] csrbank1_dfii_pi0_baddress0_w;
+wire csrbank1_dfii_pi0_wrdata3_re;
+wire [7:0] csrbank1_dfii_pi0_wrdata3_r;
+wire csrbank1_dfii_pi0_wrdata3_we;
+wire [7:0] csrbank1_dfii_pi0_wrdata3_w;
+wire csrbank1_dfii_pi0_wrdata2_re;
+wire [7:0] csrbank1_dfii_pi0_wrdata2_r;
+wire csrbank1_dfii_pi0_wrdata2_we;
+wire [7:0] csrbank1_dfii_pi0_wrdata2_w;
+wire csrbank1_dfii_pi0_wrdata1_re;
+wire [7:0] csrbank1_dfii_pi0_wrdata1_r;
+wire csrbank1_dfii_pi0_wrdata1_we;
+wire [7:0] csrbank1_dfii_pi0_wrdata1_w;
wire csrbank1_dfii_pi0_wrdata0_re;
-wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
+wire [7:0] csrbank1_dfii_pi0_wrdata0_r;
wire csrbank1_dfii_pi0_wrdata0_we;
-wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
-wire csrbank1_dfii_pi0_rddata_re;
-wire [31:0] csrbank1_dfii_pi0_rddata_r;
-wire csrbank1_dfii_pi0_rddata_we;
-wire [31:0] csrbank1_dfii_pi0_rddata_w;
+wire [7:0] csrbank1_dfii_pi0_wrdata0_w;
+wire csrbank1_dfii_pi0_rddata3_re;
+wire [7:0] csrbank1_dfii_pi0_rddata3_r;
+wire csrbank1_dfii_pi0_rddata3_we;
+wire [7:0] csrbank1_dfii_pi0_rddata3_w;
+wire csrbank1_dfii_pi0_rddata2_re;
+wire [7:0] csrbank1_dfii_pi0_rddata2_r;
+wire csrbank1_dfii_pi0_rddata2_we;
+wire [7:0] csrbank1_dfii_pi0_rddata2_w;
+wire csrbank1_dfii_pi0_rddata1_re;
+wire [7:0] csrbank1_dfii_pi0_rddata1_r;
+wire csrbank1_dfii_pi0_rddata1_we;
+wire [7:0] csrbank1_dfii_pi0_rddata1_w;
+wire csrbank1_dfii_pi0_rddata0_re;
+wire [7:0] csrbank1_dfii_pi0_rddata0_r;
+wire csrbank1_dfii_pi0_rddata0_we;
+wire [7:0] csrbank1_dfii_pi0_rddata0_w;
wire csrbank1_dfii_pi1_command0_re;
wire [5:0] csrbank1_dfii_pi1_command0_r;
wire csrbank1_dfii_pi1_command0_we;
wire [5:0] csrbank1_dfii_pi1_command0_w;
+wire csrbank1_dfii_pi1_address1_re;
+wire [5:0] csrbank1_dfii_pi1_address1_r;
+wire csrbank1_dfii_pi1_address1_we;
+wire [5:0] csrbank1_dfii_pi1_address1_w;
wire csrbank1_dfii_pi1_address0_re;
-wire [13:0] csrbank1_dfii_pi1_address0_r;
+wire [7:0] csrbank1_dfii_pi1_address0_r;
wire csrbank1_dfii_pi1_address0_we;
-wire [13:0] csrbank1_dfii_pi1_address0_w;
+wire [7:0] csrbank1_dfii_pi1_address0_w;
wire csrbank1_dfii_pi1_baddress0_re;
wire [2:0] csrbank1_dfii_pi1_baddress0_r;
wire csrbank1_dfii_pi1_baddress0_we;
wire [2:0] csrbank1_dfii_pi1_baddress0_w;
+wire csrbank1_dfii_pi1_wrdata3_re;
+wire [7:0] csrbank1_dfii_pi1_wrdata3_r;
+wire csrbank1_dfii_pi1_wrdata3_we;
+wire [7:0] csrbank1_dfii_pi1_wrdata3_w;
+wire csrbank1_dfii_pi1_wrdata2_re;
+wire [7:0] csrbank1_dfii_pi1_wrdata2_r;
+wire csrbank1_dfii_pi1_wrdata2_we;
+wire [7:0] csrbank1_dfii_pi1_wrdata2_w;
+wire csrbank1_dfii_pi1_wrdata1_re;
+wire [7:0] csrbank1_dfii_pi1_wrdata1_r;
+wire csrbank1_dfii_pi1_wrdata1_we;
+wire [7:0] csrbank1_dfii_pi1_wrdata1_w;
wire csrbank1_dfii_pi1_wrdata0_re;
-wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
+wire [7:0] csrbank1_dfii_pi1_wrdata0_r;
wire csrbank1_dfii_pi1_wrdata0_we;
-wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
-wire csrbank1_dfii_pi1_rddata_re;
-wire [31:0] csrbank1_dfii_pi1_rddata_r;
-wire csrbank1_dfii_pi1_rddata_we;
-wire [31:0] csrbank1_dfii_pi1_rddata_w;
+wire [7:0] csrbank1_dfii_pi1_wrdata0_w;
+wire csrbank1_dfii_pi1_rddata3_re;
+wire [7:0] csrbank1_dfii_pi1_rddata3_r;
+wire csrbank1_dfii_pi1_rddata3_we;
+wire [7:0] csrbank1_dfii_pi1_rddata3_w;
+wire csrbank1_dfii_pi1_rddata2_re;
+wire [7:0] csrbank1_dfii_pi1_rddata2_r;
+wire csrbank1_dfii_pi1_rddata2_we;
+wire [7:0] csrbank1_dfii_pi1_rddata2_w;
+wire csrbank1_dfii_pi1_rddata1_re;
+wire [7:0] csrbank1_dfii_pi1_rddata1_r;
+wire csrbank1_dfii_pi1_rddata1_we;
+wire [7:0] csrbank1_dfii_pi1_rddata1_w;
+wire csrbank1_dfii_pi1_rddata0_re;
+wire [7:0] csrbank1_dfii_pi1_rddata0_r;
+wire csrbank1_dfii_pi1_rddata0_we;
+wire [7:0] csrbank1_dfii_pi1_rddata0_w;
wire csrbank1_dfii_pi2_command0_re;
wire [5:0] csrbank1_dfii_pi2_command0_r;
wire csrbank1_dfii_pi2_command0_we;
wire [5:0] csrbank1_dfii_pi2_command0_w;
+wire csrbank1_dfii_pi2_address1_re;
+wire [5:0] csrbank1_dfii_pi2_address1_r;
+wire csrbank1_dfii_pi2_address1_we;
+wire [5:0] csrbank1_dfii_pi2_address1_w;
wire csrbank1_dfii_pi2_address0_re;
-wire [13:0] csrbank1_dfii_pi2_address0_r;
+wire [7:0] csrbank1_dfii_pi2_address0_r;
wire csrbank1_dfii_pi2_address0_we;
-wire [13:0] csrbank1_dfii_pi2_address0_w;
+wire [7:0] csrbank1_dfii_pi2_address0_w;
wire csrbank1_dfii_pi2_baddress0_re;
wire [2:0] csrbank1_dfii_pi2_baddress0_r;
wire csrbank1_dfii_pi2_baddress0_we;
wire [2:0] csrbank1_dfii_pi2_baddress0_w;
+wire csrbank1_dfii_pi2_wrdata3_re;
+wire [7:0] csrbank1_dfii_pi2_wrdata3_r;
+wire csrbank1_dfii_pi2_wrdata3_we;
+wire [7:0] csrbank1_dfii_pi2_wrdata3_w;
+wire csrbank1_dfii_pi2_wrdata2_re;
+wire [7:0] csrbank1_dfii_pi2_wrdata2_r;
+wire csrbank1_dfii_pi2_wrdata2_we;
+wire [7:0] csrbank1_dfii_pi2_wrdata2_w;
+wire csrbank1_dfii_pi2_wrdata1_re;
+wire [7:0] csrbank1_dfii_pi2_wrdata1_r;
+wire csrbank1_dfii_pi2_wrdata1_we;
+wire [7:0] csrbank1_dfii_pi2_wrdata1_w;
wire csrbank1_dfii_pi2_wrdata0_re;
-wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
+wire [7:0] csrbank1_dfii_pi2_wrdata0_r;
wire csrbank1_dfii_pi2_wrdata0_we;
-wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
-wire csrbank1_dfii_pi2_rddata_re;
-wire [31:0] csrbank1_dfii_pi2_rddata_r;
-wire csrbank1_dfii_pi2_rddata_we;
-wire [31:0] csrbank1_dfii_pi2_rddata_w;
+wire [7:0] csrbank1_dfii_pi2_wrdata0_w;
+wire csrbank1_dfii_pi2_rddata3_re;
+wire [7:0] csrbank1_dfii_pi2_rddata3_r;
+wire csrbank1_dfii_pi2_rddata3_we;
+wire [7:0] csrbank1_dfii_pi2_rddata3_w;
+wire csrbank1_dfii_pi2_rddata2_re;
+wire [7:0] csrbank1_dfii_pi2_rddata2_r;
+wire csrbank1_dfii_pi2_rddata2_we;
+wire [7:0] csrbank1_dfii_pi2_rddata2_w;
+wire csrbank1_dfii_pi2_rddata1_re;
+wire [7:0] csrbank1_dfii_pi2_rddata1_r;
+wire csrbank1_dfii_pi2_rddata1_we;
+wire [7:0] csrbank1_dfii_pi2_rddata1_w;
+wire csrbank1_dfii_pi2_rddata0_re;
+wire [7:0] csrbank1_dfii_pi2_rddata0_r;
+wire csrbank1_dfii_pi2_rddata0_we;
+wire [7:0] csrbank1_dfii_pi2_rddata0_w;
wire csrbank1_dfii_pi3_command0_re;
wire [5:0] csrbank1_dfii_pi3_command0_r;
wire csrbank1_dfii_pi3_command0_we;
wire [5:0] csrbank1_dfii_pi3_command0_w;
+wire csrbank1_dfii_pi3_address1_re;
+wire [5:0] csrbank1_dfii_pi3_address1_r;
+wire csrbank1_dfii_pi3_address1_we;
+wire [5:0] csrbank1_dfii_pi3_address1_w;
wire csrbank1_dfii_pi3_address0_re;
-wire [13:0] csrbank1_dfii_pi3_address0_r;
+wire [7:0] csrbank1_dfii_pi3_address0_r;
wire csrbank1_dfii_pi3_address0_we;
-wire [13:0] csrbank1_dfii_pi3_address0_w;
+wire [7:0] csrbank1_dfii_pi3_address0_w;
wire csrbank1_dfii_pi3_baddress0_re;
wire [2:0] csrbank1_dfii_pi3_baddress0_r;
wire csrbank1_dfii_pi3_baddress0_we;
wire [2:0] csrbank1_dfii_pi3_baddress0_w;
+wire csrbank1_dfii_pi3_wrdata3_re;
+wire [7:0] csrbank1_dfii_pi3_wrdata3_r;
+wire csrbank1_dfii_pi3_wrdata3_we;
+wire [7:0] csrbank1_dfii_pi3_wrdata3_w;
+wire csrbank1_dfii_pi3_wrdata2_re;
+wire [7:0] csrbank1_dfii_pi3_wrdata2_r;
+wire csrbank1_dfii_pi3_wrdata2_we;
+wire [7:0] csrbank1_dfii_pi3_wrdata2_w;
+wire csrbank1_dfii_pi3_wrdata1_re;
+wire [7:0] csrbank1_dfii_pi3_wrdata1_r;
+wire csrbank1_dfii_pi3_wrdata1_we;
+wire [7:0] csrbank1_dfii_pi3_wrdata1_w;
wire csrbank1_dfii_pi3_wrdata0_re;
-wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
+wire [7:0] csrbank1_dfii_pi3_wrdata0_r;
wire csrbank1_dfii_pi3_wrdata0_we;
-wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
-wire csrbank1_dfii_pi3_rddata_re;
-wire [31:0] csrbank1_dfii_pi3_rddata_r;
-wire csrbank1_dfii_pi3_rddata_we;
-wire [31:0] csrbank1_dfii_pi3_rddata_w;
-reg csrbank1_sel = 1'd0;
+wire [7:0] csrbank1_dfii_pi3_wrdata0_w;
+wire csrbank1_dfii_pi3_rddata3_re;
+wire [7:0] csrbank1_dfii_pi3_rddata3_r;
+wire csrbank1_dfii_pi3_rddata3_we;
+wire [7:0] csrbank1_dfii_pi3_rddata3_w;
+wire csrbank1_dfii_pi3_rddata2_re;
+wire [7:0] csrbank1_dfii_pi3_rddata2_r;
+wire csrbank1_dfii_pi3_rddata2_we;
+wire [7:0] csrbank1_dfii_pi3_rddata2_w;
+wire csrbank1_dfii_pi3_rddata1_re;
+wire [7:0] csrbank1_dfii_pi3_rddata1_r;
+wire csrbank1_dfii_pi3_rddata1_we;
+wire [7:0] csrbank1_dfii_pi3_rddata1_w;
+wire csrbank1_dfii_pi3_rddata0_re;
+wire [7:0] csrbank1_dfii_pi3_rddata0_r;
+wire csrbank1_dfii_pi3_rddata0_we;
+wire [7:0] csrbank1_dfii_pi3_rddata0_w;
+wire csrbank1_sel;
wire [13:0] adr;
wire we;
-wire [31:0] dat_w;
-wire [31:0] dat_r;
+wire [7:0] dat_w;
+wire [7:0] dat_r;
wire [24:0] slice_proxy0;
wire [24:0] slice_proxy1;
wire [24:0] slice_proxy2;
wire [24:0] slice_proxy13;
wire [24:0] slice_proxy14;
wire [24:0] slice_proxy15;
-reg comb_rhs_array_muxed0 = 1'd0;
-reg [13:0] comb_rhs_array_muxed1 = 14'd0;
-reg [2:0] comb_rhs_array_muxed2 = 3'd0;
-reg comb_rhs_array_muxed3 = 1'd0;
-reg comb_rhs_array_muxed4 = 1'd0;
-reg comb_rhs_array_muxed5 = 1'd0;
-reg comb_t_array_muxed0 = 1'd0;
-reg comb_t_array_muxed1 = 1'd0;
-reg comb_t_array_muxed2 = 1'd0;
-reg comb_rhs_array_muxed6 = 1'd0;
-reg [13:0] comb_rhs_array_muxed7 = 14'd0;
-reg [2:0] comb_rhs_array_muxed8 = 3'd0;
-reg comb_rhs_array_muxed9 = 1'd0;
-reg comb_rhs_array_muxed10 = 1'd0;
-reg comb_rhs_array_muxed11 = 1'd0;
-reg comb_t_array_muxed3 = 1'd0;
-reg comb_t_array_muxed4 = 1'd0;
-reg comb_t_array_muxed5 = 1'd0;
-reg [20:0] comb_rhs_array_muxed12 = 21'd0;
-reg comb_rhs_array_muxed13 = 1'd0;
-reg comb_rhs_array_muxed14 = 1'd0;
-reg [20:0] comb_rhs_array_muxed15 = 21'd0;
-reg comb_rhs_array_muxed16 = 1'd0;
-reg comb_rhs_array_muxed17 = 1'd0;
-reg [20:0] comb_rhs_array_muxed18 = 21'd0;
-reg comb_rhs_array_muxed19 = 1'd0;
-reg comb_rhs_array_muxed20 = 1'd0;
-reg [20:0] comb_rhs_array_muxed21 = 21'd0;
-reg comb_rhs_array_muxed22 = 1'd0;
-reg comb_rhs_array_muxed23 = 1'd0;
-reg [20:0] comb_rhs_array_muxed24 = 21'd0;
-reg comb_rhs_array_muxed25 = 1'd0;
-reg comb_rhs_array_muxed26 = 1'd0;
-reg [20:0] comb_rhs_array_muxed27 = 21'd0;
-reg comb_rhs_array_muxed28 = 1'd0;
-reg comb_rhs_array_muxed29 = 1'd0;
-reg [20:0] comb_rhs_array_muxed30 = 21'd0;
-reg comb_rhs_array_muxed31 = 1'd0;
-reg comb_rhs_array_muxed32 = 1'd0;
-reg [20:0] comb_rhs_array_muxed33 = 21'd0;
-reg comb_rhs_array_muxed34 = 1'd0;
-reg comb_rhs_array_muxed35 = 1'd0;
-reg [63:0] sync_basiclowerer_array_muxed0 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed1 = 64'd0;
-reg [63:0] sync_t_array_muxed0 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed2 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed3 = 64'd0;
-reg [63:0] sync_t_array_muxed1 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed4 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed5 = 64'd0;
-reg [63:0] sync_t_array_muxed2 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed6 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed7 = 64'd0;
-reg [63:0] sync_t_array_muxed3 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed8 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed9 = 64'd0;
-reg [63:0] sync_t_array_muxed4 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed10 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed11 = 64'd0;
-reg [63:0] sync_t_array_muxed5 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed12 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed13 = 64'd0;
-reg [63:0] sync_t_array_muxed6 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed14 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed15 = 64'd0;
-reg [63:0] sync_t_array_muxed7 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed16 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed17 = 64'd0;
-reg [63:0] sync_t_array_muxed8 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed18 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed19 = 64'd0;
-reg [63:0] sync_t_array_muxed9 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed20 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed21 = 64'd0;
-reg [63:0] sync_t_array_muxed10 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed22 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed23 = 64'd0;
-reg [63:0] sync_t_array_muxed11 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed24 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed25 = 64'd0;
-reg [63:0] sync_t_array_muxed12 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed26 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed27 = 64'd0;
-reg [63:0] sync_t_array_muxed13 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed28 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed29 = 64'd0;
-reg [63:0] sync_t_array_muxed14 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed30 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed31 = 64'd0;
-reg [63:0] sync_t_array_muxed15 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed32 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed33 = 64'd0;
-reg [63:0] sync_t_array_muxed16 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed34 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed35 = 64'd0;
-reg [63:0] sync_t_array_muxed17 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed36 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed37 = 64'd0;
-reg [63:0] sync_t_array_muxed18 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed38 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed39 = 64'd0;
-reg [63:0] sync_t_array_muxed19 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed40 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed41 = 64'd0;
-reg [63:0] sync_t_array_muxed20 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed42 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed43 = 64'd0;
-reg [63:0] sync_t_array_muxed21 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed44 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed45 = 64'd0;
-reg [63:0] sync_t_array_muxed22 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed46 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed47 = 64'd0;
-reg [63:0] sync_t_array_muxed23 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed48 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed49 = 64'd0;
-reg [63:0] sync_t_array_muxed24 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed50 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed51 = 64'd0;
-reg [63:0] sync_t_array_muxed25 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed52 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed53 = 64'd0;
-reg [63:0] sync_t_array_muxed26 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed54 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed55 = 64'd0;
-reg [63:0] sync_t_array_muxed27 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed56 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed57 = 64'd0;
-reg [63:0] sync_t_array_muxed28 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed58 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed59 = 64'd0;
-reg [63:0] sync_t_array_muxed29 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed60 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed61 = 64'd0;
-reg [63:0] sync_t_array_muxed30 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed62 = 64'd0;
-reg [63:0] sync_basiclowerer_array_muxed63 = 64'd0;
-reg [63:0] sync_t_array_muxed31 = 64'd0;
-reg [2:0] sync_rhs_array_muxed0 = 3'd0;
-reg [13:0] sync_rhs_array_muxed1 = 14'd0;
-reg sync_rhs_array_muxed2 = 1'd0;
-reg sync_rhs_array_muxed3 = 1'd0;
-reg sync_rhs_array_muxed4 = 1'd0;
-reg sync_rhs_array_muxed5 = 1'd0;
-reg sync_rhs_array_muxed6 = 1'd0;
-reg [2:0] sync_rhs_array_muxed7 = 3'd0;
-reg [13:0] sync_rhs_array_muxed8 = 14'd0;
-reg sync_rhs_array_muxed9 = 1'd0;
-reg sync_rhs_array_muxed10 = 1'd0;
-reg sync_rhs_array_muxed11 = 1'd0;
-reg sync_rhs_array_muxed12 = 1'd0;
-reg sync_rhs_array_muxed13 = 1'd0;
-reg [2:0] sync_rhs_array_muxed14 = 3'd0;
-reg [13:0] sync_rhs_array_muxed15 = 14'd0;
-reg sync_rhs_array_muxed16 = 1'd0;
-reg sync_rhs_array_muxed17 = 1'd0;
-reg sync_rhs_array_muxed18 = 1'd0;
-reg sync_rhs_array_muxed19 = 1'd0;
-reg sync_rhs_array_muxed20 = 1'd0;
-reg [2:0] sync_rhs_array_muxed21 = 3'd0;
-reg [13:0] sync_rhs_array_muxed22 = 14'd0;
-reg sync_rhs_array_muxed23 = 1'd0;
-reg sync_rhs_array_muxed24 = 1'd0;
-reg sync_rhs_array_muxed25 = 1'd0;
-reg sync_rhs_array_muxed26 = 1'd0;
-reg sync_rhs_array_muxed27 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [13:0] rhs_array_muxed1 = 14'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [13:0] rhs_array_muxed7 = 14'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [20:0] rhs_array_muxed12 = 21'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [20:0] rhs_array_muxed15 = 21'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [20:0] rhs_array_muxed18 = 21'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [20:0] rhs_array_muxed21 = 21'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [20:0] rhs_array_muxed24 = 21'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [20:0] rhs_array_muxed27 = 21'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [20:0] rhs_array_muxed30 = 21'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [20:0] rhs_array_muxed33 = 21'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [13:0] array_muxed1 = 14'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [13:0] array_muxed8 = 14'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [13:0] array_muxed15 = 14'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [13:0] array_muxed22 = 14'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
assign init_done = init_done_storage;
assign init_error = init_error_storage;
endcase
end
always @(*) begin
- litedramcore_adr = 14'd0;
+ litedramcore_we = 1'd0;
case (state)
1'd1: begin
end
default: begin
if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr = litedramcore_wishbone_adr;
+ litedramcore_we = (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
end
end
endcase
end
always @(*) begin
- litedramcore_we = 1'd0;
+ litedramcore_wishbone_ack = 1'd0;
case (state)
1'd1: begin
+ litedramcore_wishbone_ack = 1'd1;
end
default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we = litedramcore_wishbone_we;
- end
end
endcase
end
always @(*) begin
- litedramcore_wishbone_ack = 1'd0;
+ litedramcore_adr = 14'd0;
case (state)
1'd1: begin
- litedramcore_wishbone_ack = 1'd1;
end
default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr = litedramcore_wishbone_adr;
+ end
end
endcase
end
ddrphy_writes0[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write0 = 1'd0;
+ ddrphy_bank_write_col0 = 10'd0;
case (ddrphy_writes0)
1'd1: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0);
+ ddrphy_bank_write_col0 = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bank_write_col0 = 10'd0;
+ ddrphy_bank_write0 = 1'd0;
case (ddrphy_writes0)
1'd1: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p0_bank == 1'd0);
end
2'd2: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p1_bank == 1'd0);
end
3'd4: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p2_bank == 1'd0);
end
4'd8: begin
- ddrphy_bank_write_col0 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write0 = (ddrphy_dfi_p3_bank == 1'd0);
end
endcase
end
ddrphy_reads0[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
- ddrphy_bankmodel0_read_col = 10'd0;
+ ddrphy_bankmodel0_read = 1'd0;
case (ddrphy_reads0)
1'd1: begin
- ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0);
end
2'd2: begin
- ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0);
end
3'd4: begin
- ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0);
end
4'd8: begin
- ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0);
end
endcase
end
always @(*) begin
- ddrphy_bankmodel0_read = 1'd0;
+ ddrphy_bankmodel0_read_col = 10'd0;
case (ddrphy_reads0)
1'd1: begin
- ddrphy_bankmodel0_read = (ddrphy_dfi_p0_bank == 1'd0);
+ ddrphy_bankmodel0_read_col = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel0_read = (ddrphy_dfi_p1_bank == 1'd0);
+ ddrphy_bankmodel0_read_col = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel0_read = (ddrphy_dfi_p2_bank == 1'd0);
+ ddrphy_bankmodel0_read_col = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel0_read = (ddrphy_dfi_p3_bank == 1'd0);
+ ddrphy_bankmodel0_read_col = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_activates2[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
- ddrphy_bankmodel2_activate_row = 14'd0;
+ ddrphy_bankmodel2_activate = 1'd0;
case (ddrphy_activates2)
1'd1: begin
- ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2);
end
2'd2: begin
- ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2);
end
3'd4: begin
- ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2);
end
4'd8: begin
- ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2);
end
endcase
end
always @(*) begin
- ddrphy_bankmodel2_activate = 1'd0;
+ ddrphy_bankmodel2_activate_row = 14'd0;
case (ddrphy_activates2)
1'd1: begin
- ddrphy_bankmodel2_activate = (ddrphy_dfi_p0_bank == 2'd2);
+ ddrphy_bankmodel2_activate_row = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel2_activate = (ddrphy_dfi_p1_bank == 2'd2);
+ ddrphy_bankmodel2_activate_row = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel2_activate = (ddrphy_dfi_p2_bank == 2'd2);
+ ddrphy_bankmodel2_activate_row = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel2_activate = (ddrphy_dfi_p3_bank == 2'd2);
+ ddrphy_bankmodel2_activate_row = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_reads2[3] = ddrphy_dfiphasemodel3_read;
end
always @(*) begin
- ddrphy_bankmodel2_read = 1'd0;
+ ddrphy_bankmodel2_read_col = 10'd0;
case (ddrphy_reads2)
1'd1: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2);
+ ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bankmodel2_read_col = 10'd0;
+ ddrphy_bankmodel2_read = 1'd0;
case (ddrphy_reads2)
1'd1: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p0_bank == 2'd2);
end
2'd2: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p1_bank == 2'd2);
end
3'd4: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p2_bank == 2'd2);
end
4'd8: begin
- ddrphy_bankmodel2_read_col = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel2_read = (ddrphy_dfi_p3_bank == 2'd2);
end
endcase
end
ddrphy_writes3[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write_col3 = 10'd0;
+ ddrphy_bank_write3 = 1'd0;
case (ddrphy_writes3)
1'd1: begin
- ddrphy_bank_write_col3 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3);
end
2'd2: begin
- ddrphy_bank_write_col3 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3);
end
3'd4: begin
- ddrphy_bank_write_col3 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3);
end
4'd8: begin
- ddrphy_bank_write_col3 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3);
end
endcase
end
always @(*) begin
- ddrphy_bank_write3 = 1'd0;
+ ddrphy_bank_write_col3 = 10'd0;
case (ddrphy_writes3)
1'd1: begin
- ddrphy_bank_write3 = (ddrphy_dfi_p0_bank == 2'd3);
+ ddrphy_bank_write_col3 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write3 = (ddrphy_dfi_p1_bank == 2'd3);
+ ddrphy_bank_write_col3 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write3 = (ddrphy_dfi_p2_bank == 2'd3);
+ ddrphy_bank_write_col3 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write3 = (ddrphy_dfi_p3_bank == 2'd3);
+ ddrphy_bank_write_col3 = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_activates4[3] = ddrphy_dfiphasemodel3_activate;
end
always @(*) begin
- ddrphy_bankmodel4_activate = 1'd0;
+ ddrphy_bankmodel4_activate_row = 14'd0;
case (ddrphy_activates4)
1'd1: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4);
+ ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bankmodel4_activate_row = 14'd0;
+ ddrphy_bankmodel4_activate = 1'd0;
case (ddrphy_activates4)
1'd1: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p0_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p1_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p2_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
- ddrphy_bankmodel4_activate_row = ddrphy_dfi_p3_address;
+ ddrphy_bankmodel4_activate = (ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
ddrphy_writes4[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write4 = 1'd0;
+ ddrphy_bank_write_col4 = 10'd0;
case (ddrphy_writes4)
1'd1: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4);
+ ddrphy_bank_write_col4 = ddrphy_dfi_p3_address;
end
endcase
end
always @(*) begin
- ddrphy_bank_write_col4 = 10'd0;
+ ddrphy_bank_write4 = 1'd0;
case (ddrphy_writes4)
1'd1: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p0_bank == 3'd4);
end
2'd2: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p1_bank == 3'd4);
end
3'd4: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p2_bank == 3'd4);
end
4'd8: begin
- ddrphy_bank_write_col4 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write4 = (ddrphy_dfi_p3_bank == 3'd4);
end
endcase
end
ddrphy_writes7[3] = ddrphy_dfiphasemodel3_write;
end
always @(*) begin
- ddrphy_bank_write_col7 = 10'd0;
+ ddrphy_bank_write7 = 1'd0;
case (ddrphy_writes7)
1'd1: begin
- ddrphy_bank_write_col7 = ddrphy_dfi_p0_address;
+ ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7);
end
2'd2: begin
- ddrphy_bank_write_col7 = ddrphy_dfi_p1_address;
+ ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7);
end
3'd4: begin
- ddrphy_bank_write_col7 = ddrphy_dfi_p2_address;
+ ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7);
end
4'd8: begin
- ddrphy_bank_write_col7 = ddrphy_dfi_p3_address;
+ ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7);
end
endcase
end
always @(*) begin
- ddrphy_bank_write7 = 1'd0;
+ ddrphy_bank_write_col7 = 10'd0;
case (ddrphy_writes7)
1'd1: begin
- ddrphy_bank_write7 = (ddrphy_dfi_p0_bank == 3'd7);
+ ddrphy_bank_write_col7 = ddrphy_dfi_p0_address;
end
2'd2: begin
- ddrphy_bank_write7 = (ddrphy_dfi_p1_bank == 3'd7);
+ ddrphy_bank_write_col7 = ddrphy_dfi_p1_address;
end
3'd4: begin
- ddrphy_bank_write7 = (ddrphy_dfi_p2_bank == 3'd7);
+ ddrphy_bank_write_col7 = ddrphy_dfi_p2_address;
end
4'd8: begin
- ddrphy_bank_write7 = (ddrphy_dfi_p3_bank == 3'd7);
+ ddrphy_bank_write_col7 = ddrphy_dfi_p3_address;
end
endcase
end
ddrphy_dfiphasemodel3_read = ddrphy_dfi_p3_we_n;
end
end
-assign ddrphy_dfitimingschecker_ps0 = ((ddrphy_dfitimingschecker_cnt + 1'd0) * 12'd2500);
-assign ddrphy_dfitimingschecker_state0 = {ddrphy_dfi_p0_cs_n, ddrphy_dfi_p0_ras_n, ddrphy_dfi_p0_cas_n, ddrphy_dfi_p0_we_n};
-assign ddrphy_dfitimingschecker_all_banks0 = ((ddrphy_dfitimingschecker_state0 == 1'd1) | ((ddrphy_dfitimingschecker_state0 == 2'd2) & ddrphy_dfi_p0_address[10]));
-always @(*) begin
- ddrphy_dfitimingschecker_ref_issued = 4'd0;
- ddrphy_dfitimingschecker_ref_issued[0] = (ddrphy_dfitimingschecker_state0 == 1'd1);
- ddrphy_dfitimingschecker_ref_issued[1] = (ddrphy_dfitimingschecker_state1 == 1'd1);
- ddrphy_dfitimingschecker_ref_issued[2] = (ddrphy_dfitimingschecker_state2 == 1'd1);
- ddrphy_dfitimingschecker_ref_issued[3] = (ddrphy_dfitimingschecker_state3 == 1'd1);
-end
-assign ddrphy_dfitimingschecker_cmd_recv0 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv1 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv2 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next0 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv3 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv4 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv5 = (((ddrphy_dfi_p0_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv6 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv7 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv8 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next1 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv9 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv10 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv11 = (((ddrphy_dfi_p0_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv12 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv13 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv14 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next2 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv15 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv16 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv17 = (((ddrphy_dfi_p0_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv18 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv19 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv20 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next3 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv21 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv22 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv23 = (((ddrphy_dfi_p0_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv24 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv25 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv26 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next4 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv27 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv28 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv29 = (((ddrphy_dfi_p0_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv30 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv31 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv32 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next5 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv33 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv34 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv35 = (((ddrphy_dfi_p0_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv36 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv37 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv38 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next6 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv39 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv40 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv41 = (((ddrphy_dfi_p0_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv42 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv43 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv44 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next7 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv45 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv46 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv47 = (((ddrphy_dfi_p0_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks0) & (ddrphy_dfitimingschecker_state0 == 3'd6));
-assign ddrphy_dfitimingschecker_ps1 = ((ddrphy_dfitimingschecker_cnt + 1'd1) * 12'd2500);
-assign ddrphy_dfitimingschecker_state1 = {ddrphy_dfi_p1_cs_n, ddrphy_dfi_p1_ras_n, ddrphy_dfi_p1_cas_n, ddrphy_dfi_p1_we_n};
-assign ddrphy_dfitimingschecker_all_banks1 = ((ddrphy_dfitimingschecker_state1 == 1'd1) | ((ddrphy_dfitimingschecker_state1 == 2'd2) & ddrphy_dfi_p1_address[10]));
-assign ddrphy_dfitimingschecker_cmd_recv48 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv49 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv50 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next8 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv51 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv52 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv53 = (((ddrphy_dfi_p1_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv54 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv55 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv56 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next9 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv57 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv58 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv59 = (((ddrphy_dfi_p1_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv60 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv61 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv62 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next10 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv63 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv64 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv65 = (((ddrphy_dfi_p1_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv66 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv67 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv68 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next11 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv69 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv70 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv71 = (((ddrphy_dfi_p1_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv72 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv73 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv74 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next12 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv75 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv76 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv77 = (((ddrphy_dfi_p1_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv78 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv79 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv80 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next13 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv81 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv82 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv83 = (((ddrphy_dfi_p1_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv84 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv85 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv86 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next14 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv87 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv88 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv89 = (((ddrphy_dfi_p1_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv90 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv91 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv92 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next15 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv93 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv94 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv95 = (((ddrphy_dfi_p1_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks1) & (ddrphy_dfitimingschecker_state1 == 3'd6));
-assign ddrphy_dfitimingschecker_ps2 = ((ddrphy_dfitimingschecker_cnt + 2'd2) * 12'd2500);
-assign ddrphy_dfitimingschecker_state2 = {ddrphy_dfi_p2_cs_n, ddrphy_dfi_p2_ras_n, ddrphy_dfi_p2_cas_n, ddrphy_dfi_p2_we_n};
-assign ddrphy_dfitimingschecker_all_banks2 = ((ddrphy_dfitimingschecker_state2 == 1'd1) | ((ddrphy_dfitimingschecker_state2 == 2'd2) & ddrphy_dfi_p2_address[10]));
-assign ddrphy_dfitimingschecker_cmd_recv96 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv97 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv98 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next16 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv99 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv100 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv101 = (((ddrphy_dfi_p2_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv102 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv103 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv104 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next17 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv105 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv106 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv107 = (((ddrphy_dfi_p2_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv108 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv109 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv110 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next18 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv111 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv112 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv113 = (((ddrphy_dfi_p2_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv114 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv115 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv116 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next19 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv117 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv118 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv119 = (((ddrphy_dfi_p2_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv120 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv121 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv122 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next20 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv123 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv124 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv125 = (((ddrphy_dfi_p2_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv126 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv127 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv128 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next21 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv129 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv130 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv131 = (((ddrphy_dfi_p2_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv132 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv133 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv134 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next22 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv135 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv136 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv137 = (((ddrphy_dfi_p2_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv138 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv139 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv140 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next23 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv141 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv142 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv143 = (((ddrphy_dfi_p2_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks2) & (ddrphy_dfitimingschecker_state2 == 3'd6));
-assign ddrphy_dfitimingschecker_ps3 = ((ddrphy_dfitimingschecker_cnt + 2'd3) * 12'd2500);
-assign ddrphy_dfitimingschecker_state3 = {ddrphy_dfi_p3_cs_n, ddrphy_dfi_p3_ras_n, ddrphy_dfi_p3_cas_n, ddrphy_dfi_p3_we_n};
-assign ddrphy_dfitimingschecker_all_banks3 = ((ddrphy_dfitimingschecker_state3 == 1'd1) | ((ddrphy_dfitimingschecker_state3 == 2'd2) & ddrphy_dfi_p3_address[10]));
-assign ddrphy_dfitimingschecker_cmd_recv144 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv145 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv146 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next24 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv147 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv148 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv149 = (((ddrphy_dfi_p3_bank == 1'd0) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv150 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv151 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv152 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next25 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv153 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv154 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv155 = (((ddrphy_dfi_p3_bank == 1'd1) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv156 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv157 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv158 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next26 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv159 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv160 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv161 = (((ddrphy_dfi_p3_bank == 2'd2) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv162 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv163 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv164 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next27 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv165 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv166 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv167 = (((ddrphy_dfi_p3_bank == 2'd3) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv168 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv169 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv170 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next28 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv171 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv172 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv173 = (((ddrphy_dfi_p3_bank == 3'd4) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv174 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv175 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv176 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next29 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv177 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv178 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv179 = (((ddrphy_dfi_p3_bank == 3'd5) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv180 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv181 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv182 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next30 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv183 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv184 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv185 = (((ddrphy_dfi_p3_bank == 3'd6) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_cmd_recv186 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd2));
-assign ddrphy_dfitimingschecker_cmd_recv187 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 1'd1));
-assign ddrphy_dfitimingschecker_cmd_recv188 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 2'd3));
-assign ddrphy_dfitimingschecker_act_next31 = (ddrphy_dfitimingschecker_act_curr + 1'd1);
-assign ddrphy_dfitimingschecker_cmd_recv189 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd5));
-assign ddrphy_dfitimingschecker_cmd_recv190 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd4));
-assign ddrphy_dfitimingschecker_cmd_recv191 = (((ddrphy_dfi_p3_bank == 3'd7) | ddrphy_dfitimingschecker_all_banks3) & (ddrphy_dfitimingschecker_state3 == 3'd6));
-assign ddrphy_dfitimingschecker_curr_diff = (ddrphy_dfitimingschecker_ps3 - (ddrphy_dfitimingschecker_ref_ps + 23'd7812500));
assign ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
assign ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
always @(*) begin
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
- litedramcore_master_p2_ras_n = 1'd1;
+ litedramcore_master_p1_cs_n = 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n;
+ litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n;
end else begin
- litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n;
+ litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n;
end
end
always @(*) begin
- litedramcore_slave_p2_rddata = 32'd0;
+ litedramcore_master_p1_ras_n = 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata;
+ litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n;
end else begin
+ litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n;
end
end
always @(*) begin
- litedramcore_master_p2_we_n = 1'd1;
+ litedramcore_slave_p1_rddata = 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n;
+ litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata;
end else begin
- litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n;
end
end
always @(*) begin
- litedramcore_slave_p2_rddata_valid = 1'd0;
+ litedramcore_master_p1_we_n = 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n;
end else begin
+ litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n;
end
end
always @(*) begin
- litedramcore_master_p2_cke = 1'd0;
+ litedramcore_slave_p1_rddata_valid = 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cke = litedramcore_slave_p2_cke;
+ litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
end else begin
- litedramcore_master_p2_cke = litedramcore_inti_p2_cke;
end
end
always @(*) begin
- litedramcore_master_p2_odt = 1'd0;
+ litedramcore_master_p1_cke = 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_odt = litedramcore_slave_p2_odt;
+ litedramcore_master_p1_cke = litedramcore_slave_p1_cke;
end else begin
- litedramcore_master_p2_odt = litedramcore_inti_p2_odt;
+ litedramcore_master_p1_cke = litedramcore_inti_p1_cke;
end
end
always @(*) begin
- litedramcore_master_p2_reset_n = 1'd0;
+ litedramcore_master_p1_odt = 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n;
+ litedramcore_master_p1_odt = litedramcore_slave_p1_odt;
end else begin
- litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n;
+ litedramcore_master_p1_odt = litedramcore_inti_p1_odt;
end
end
always @(*) begin
- litedramcore_master_p2_act_n = 1'd1;
+ litedramcore_master_p1_reset_n = 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n;
+ litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n;
end else begin
- litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n;
+ litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n;
end
end
always @(*) begin
- litedramcore_master_p2_wrdata = 32'd0;
+ litedramcore_master_p1_act_n = 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata;
+ litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n;
end else begin
- litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata;
+ litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n;
end
end
always @(*) begin
- litedramcore_inti_p3_rddata = 32'd0;
+ litedramcore_master_p1_wrdata = 32'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata;
end else begin
- litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata;
+ litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata;
end
end
always @(*) begin
- litedramcore_master_p2_wrdata_en = 1'd0;
+ litedramcore_inti_p2_rddata = 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en;
end else begin
- litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en;
+ litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata;
end
end
always @(*) begin
- litedramcore_inti_p3_rddata_valid = 1'd0;
+ litedramcore_master_p1_wrdata_en = 1'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en;
end else begin
- litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
+ litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en;
end
end
always @(*) begin
- litedramcore_master_p2_wrdata_mask = 4'd0;
+ litedramcore_inti_p2_rddata_valid = 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask;
end else begin
- litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask;
+ litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
end
end
always @(*) begin
- litedramcore_master_p2_rddata_en = 1'd0;
+ litedramcore_master_p1_wrdata_mask = 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en;
+ litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask;
end else begin
- litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en;
+ litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask;
end
end
always @(*) begin
- litedramcore_master_p3_address = 14'd0;
+ litedramcore_master_p1_rddata_en = 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_address = litedramcore_slave_p3_address;
+ litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p3_address = litedramcore_inti_p3_address;
+ litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_address = 14'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_address = litedramcore_slave_p2_address;
+ end else begin
+ litedramcore_master_p2_address = litedramcore_inti_p2_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_bank = 3'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_bank = litedramcore_slave_p2_bank;
+ end else begin
+ litedramcore_master_p2_bank = litedramcore_inti_p2_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cas_n = 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n;
+ end else begin
+ litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cs_n = 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n;
+ end else begin
+ litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_ras_n = 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_ras_n = litedramcore_slave_p2_ras_n;
+ end else begin
+ litedramcore_master_p2_ras_n = litedramcore_inti_p2_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata = 32'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_slave_p2_rddata = litedramcore_master_p2_rddata;
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_we_n = 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_we_n = litedramcore_slave_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n = litedramcore_inti_p2_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata_valid = 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_slave_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cke = 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_cke = litedramcore_slave_p2_cke;
+ end else begin
+ litedramcore_master_p2_cke = litedramcore_inti_p2_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_odt = 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_odt = litedramcore_slave_p2_odt;
+ end else begin
+ litedramcore_master_p2_odt = litedramcore_inti_p2_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_reset_n = 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_reset_n = litedramcore_slave_p2_reset_n;
+ end else begin
+ litedramcore_master_p2_reset_n = litedramcore_inti_p2_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_act_n = 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_act_n = litedramcore_slave_p2_act_n;
+ end else begin
+ litedramcore_master_p2_act_n = litedramcore_inti_p2_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata = 32'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_wrdata = litedramcore_slave_p2_wrdata;
+ end else begin
+ litedramcore_master_p2_wrdata = litedramcore_inti_p2_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p3_rddata = 32'd0;
+ if (litedramcore_storage[0]) begin
+ end else begin
+ litedramcore_inti_p3_rddata = litedramcore_master_p3_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_en = 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_wrdata_en = litedramcore_slave_p2_wrdata_en;
+ end else begin
+ litedramcore_master_p2_wrdata_en = litedramcore_inti_p2_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_inti_p3_rddata_valid = 1'd0;
+ if (litedramcore_storage[0]) begin
+ end else begin
+ litedramcore_inti_p3_rddata_valid = litedramcore_master_p3_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_mask = 4'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_wrdata_mask = litedramcore_slave_p2_wrdata_mask;
+ end else begin
+ litedramcore_master_p2_wrdata_mask = litedramcore_inti_p2_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_rddata_en = 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_rddata_en = litedramcore_slave_p2_rddata_en;
+ end else begin
+ litedramcore_master_p2_rddata_en = litedramcore_inti_p2_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_address = 14'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p3_address = litedramcore_slave_p3_address;
+ end else begin
+ litedramcore_master_p3_address = litedramcore_inti_p3_address;
end
end
always @(*) begin
litedramcore_master_p1_cas_n = litedramcore_inti_p1_cas_n;
end
end
+assign litedramcore_inti_p0_cke = litedramcore_storage[1];
+assign litedramcore_inti_p1_cke = litedramcore_storage[1];
+assign litedramcore_inti_p2_cke = litedramcore_storage[1];
+assign litedramcore_inti_p3_cke = litedramcore_storage[1];
+assign litedramcore_inti_p0_odt = litedramcore_storage[2];
+assign litedramcore_inti_p1_odt = litedramcore_storage[2];
+assign litedramcore_inti_p2_odt = litedramcore_storage[2];
+assign litedramcore_inti_p3_odt = litedramcore_storage[2];
+assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
always @(*) begin
- litedramcore_master_p1_cs_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cs_n = litedramcore_slave_p1_cs_n;
+ litedramcore_inti_p0_cs_n = 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}};
end else begin
- litedramcore_master_p1_cs_n = litedramcore_inti_p1_cs_n;
+ litedramcore_inti_p0_cs_n = {1{1'd1}};
end
end
always @(*) begin
- litedramcore_master_p1_ras_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_ras_n = litedramcore_slave_p1_ras_n;
+ litedramcore_inti_p0_ras_n = 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]);
end else begin
- litedramcore_master_p1_ras_n = litedramcore_inti_p1_ras_n;
+ litedramcore_inti_p0_ras_n = 1'd1;
end
end
always @(*) begin
- litedramcore_slave_p1_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata = litedramcore_master_p1_rddata;
+ litedramcore_inti_p0_we_n = 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]);
end else begin
+ litedramcore_inti_p0_we_n = 1'd1;
end
end
always @(*) begin
- litedramcore_master_p1_we_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_we_n = litedramcore_slave_p1_we_n;
+ litedramcore_inti_p0_cas_n = 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]);
end else begin
- litedramcore_master_p1_we_n = litedramcore_inti_p1_we_n;
+ litedramcore_inti_p0_cas_n = 1'd1;
end
end
+assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
+assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
+assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_inti_p0_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_slave_p1_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata_valid = litedramcore_master_p1_rddata_valid;
+ litedramcore_inti_p1_cs_n = 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}};
end else begin
+ litedramcore_inti_p1_cs_n = {1{1'd1}};
end
end
always @(*) begin
- litedramcore_master_p1_cke = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cke = litedramcore_slave_p1_cke;
+ litedramcore_inti_p1_ras_n = 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]);
end else begin
- litedramcore_master_p1_cke = litedramcore_inti_p1_cke;
+ litedramcore_inti_p1_ras_n = 1'd1;
end
end
always @(*) begin
- litedramcore_master_p1_odt = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_odt = litedramcore_slave_p1_odt;
+ litedramcore_inti_p1_we_n = 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]);
end else begin
- litedramcore_master_p1_odt = litedramcore_inti_p1_odt;
+ litedramcore_inti_p1_we_n = 1'd1;
end
end
always @(*) begin
- litedramcore_master_p1_reset_n = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n = litedramcore_slave_p1_reset_n;
+ litedramcore_inti_p1_cas_n = 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]);
end else begin
- litedramcore_master_p1_reset_n = litedramcore_inti_p1_reset_n;
+ litedramcore_inti_p1_cas_n = 1'd1;
end
end
+assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
+assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
+assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_inti_p1_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_master_p1_act_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_act_n = litedramcore_slave_p1_act_n;
+ litedramcore_inti_p2_cs_n = 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}};
end else begin
- litedramcore_master_p1_act_n = litedramcore_inti_p1_act_n;
+ litedramcore_inti_p2_cs_n = {1{1'd1}};
end
end
always @(*) begin
- litedramcore_master_p1_wrdata = 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata = litedramcore_slave_p1_wrdata;
+ litedramcore_inti_p2_ras_n = 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]);
end else begin
- litedramcore_master_p1_wrdata = litedramcore_inti_p1_wrdata;
+ litedramcore_inti_p2_ras_n = 1'd1;
end
end
always @(*) begin
- litedramcore_inti_p2_rddata = 32'd0;
- if (litedramcore_storage[0]) begin
- end else begin
- litedramcore_inti_p2_rddata = litedramcore_master_p2_rddata;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en = litedramcore_slave_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en = litedramcore_inti_p1_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_inti_p2_rddata_valid = 1'd0;
- if (litedramcore_storage[0]) begin
- end else begin
- litedramcore_inti_p2_rddata_valid = litedramcore_master_p2_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_mask = 4'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask = litedramcore_slave_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask = litedramcore_inti_p1_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p1_rddata_en = 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en = litedramcore_slave_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en = litedramcore_inti_p1_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_address = 14'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_address = litedramcore_slave_p2_address;
- end else begin
- litedramcore_master_p2_address = litedramcore_inti_p2_address;
- end
-end
-always @(*) begin
- litedramcore_master_p2_bank = 3'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_bank = litedramcore_slave_p2_bank;
- end else begin
- litedramcore_master_p2_bank = litedramcore_inti_p2_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cas_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cas_n = litedramcore_slave_p2_cas_n;
- end else begin
- litedramcore_master_p2_cas_n = litedramcore_inti_p2_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cs_n = 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cs_n = litedramcore_slave_p2_cs_n;
- end else begin
- litedramcore_master_p2_cs_n = litedramcore_inti_p2_cs_n;
- end
-end
-assign litedramcore_inti_p0_cke = litedramcore_storage[1];
-assign litedramcore_inti_p1_cke = litedramcore_storage[1];
-assign litedramcore_inti_p2_cke = litedramcore_storage[1];
-assign litedramcore_inti_p3_cke = litedramcore_storage[1];
-assign litedramcore_inti_p0_odt = litedramcore_storage[2];
-assign litedramcore_inti_p1_odt = litedramcore_storage[2];
-assign litedramcore_inti_p2_odt = litedramcore_storage[2];
-assign litedramcore_inti_p3_odt = litedramcore_storage[2];
-assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
-assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
-always @(*) begin
- litedramcore_inti_p0_ras_n = 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_ras_n = (~litedramcore_phaseinjector0_command_storage[3]);
- end else begin
- litedramcore_inti_p0_ras_n = 1'd1;
- end
-end
-always @(*) begin
- litedramcore_inti_p0_we_n = 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_we_n = (~litedramcore_phaseinjector0_command_storage[1]);
- end else begin
- litedramcore_inti_p0_we_n = 1'd1;
- end
-end
-always @(*) begin
- litedramcore_inti_p0_cas_n = 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cas_n = (~litedramcore_phaseinjector0_command_storage[2]);
- end else begin
- litedramcore_inti_p0_cas_n = 1'd1;
- end
-end
-always @(*) begin
- litedramcore_inti_p0_cs_n = 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cs_n = {1{(~litedramcore_phaseinjector0_command_storage[0])}};
- end else begin
- litedramcore_inti_p0_cs_n = {1{1'd1}};
- end
-end
-assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
-assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
-assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_inti_p0_wrdata_mask = 1'd0;
-always @(*) begin
- litedramcore_inti_p1_ras_n = 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_ras_n = (~litedramcore_phaseinjector1_command_storage[3]);
- end else begin
- litedramcore_inti_p1_ras_n = 1'd1;
- end
-end
-always @(*) begin
- litedramcore_inti_p1_we_n = 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_we_n = (~litedramcore_phaseinjector1_command_storage[1]);
- end else begin
- litedramcore_inti_p1_we_n = 1'd1;
- end
-end
-always @(*) begin
- litedramcore_inti_p1_cas_n = 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cas_n = (~litedramcore_phaseinjector1_command_storage[2]);
- end else begin
- litedramcore_inti_p1_cas_n = 1'd1;
- end
-end
-always @(*) begin
- litedramcore_inti_p1_cs_n = 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cs_n = {1{(~litedramcore_phaseinjector1_command_storage[0])}};
- end else begin
- litedramcore_inti_p1_cs_n = {1{1'd1}};
- end
-end
-assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
-assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
-assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_inti_p1_wrdata_mask = 1'd0;
-always @(*) begin
- litedramcore_inti_p2_ras_n = 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_ras_n = (~litedramcore_phaseinjector2_command_storage[3]);
- end else begin
- litedramcore_inti_p2_ras_n = 1'd1;
- end
-end
-always @(*) begin
- litedramcore_inti_p2_we_n = 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]);
+ litedramcore_inti_p2_we_n = 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_inti_p2_we_n = (~litedramcore_phaseinjector2_command_storage[1]);
end else begin
litedramcore_inti_p2_we_n = 1'd1;
end
litedramcore_inti_p2_cas_n = 1'd1;
end
end
-always @(*) begin
- litedramcore_inti_p2_cs_n = 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cs_n = {1{(~litedramcore_phaseinjector2_command_storage[0])}};
- end else begin
- litedramcore_inti_p2_cs_n = {1{1'd1}};
- end
-end
assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_inti_p2_wrdata_mask = 1'd0;
+always @(*) begin
+ litedramcore_inti_p3_cs_n = 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}};
+ end else begin
+ litedramcore_inti_p3_cs_n = {1{1'd1}};
+ end
+end
always @(*) begin
litedramcore_inti_p3_ras_n = 1'd1;
if (litedramcore_phaseinjector3_command_issue_re) begin
litedramcore_inti_p3_cas_n = 1'd1;
end
end
-always @(*) begin
- litedramcore_inti_p3_cs_n = 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cs_n = {1{(~litedramcore_phaseinjector3_command_storage[0])}};
- end else begin
- litedramcore_inti_p3_cs_n = {1{1'd1}};
- end
-end
assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
end
endcase
end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+ case (bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
always @(*) begin
litedramcore_bankmachine0_cmd_valid = 1'd0;
case (bankmachine0_state)
end
endcase
end
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
- case (bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel = 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
always @(*) begin
litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
case (bankmachine0_state)
endcase
end
always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
- case (bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine1_req_wdata_ready = 1'd0;
case (bankmachine1_state)
1'd1: begin
end
end
endcase
end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+ case (bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel = 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
always @(*) begin
litedramcore_bankmachine1_row_close = 1'd0;
case (bankmachine1_state)
end
endcase
end
-always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
- case (bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
always @(*) begin
litedramcore_bankmachine2_row_open = 1'd0;
case (bankmachine2_state)
end
endcase
end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+ case (bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel = 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
always @(*) begin
litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
case (bankmachine2_state)
end
endcase
end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+ case (bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
always @(*) begin
litedramcore_bankmachine3_refresh_gnt = 1'd0;
case (bankmachine3_state)
end
endcase
end
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
- case (bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel = 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
always @(*) begin
litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
case (bankmachine3_state)
endcase
end
always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine4_cmd_valid = 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1;
+ litedramcore_bankmachine4_cmd_valid = 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine4_cmd_valid = 1'd0;
+ litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid = 1'd1;
+ litedramcore_bankmachine4_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid = 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine5_refresh_gnt = 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt = 1'd1;
+ end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt = 1'd0;
+ litedramcore_bankmachine5_cmd_valid = 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine5_cmd_valid = 1'd0;
+ litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid = 1'd1;
+ litedramcore_bankmachine5_row_col_n_addr_sel = 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid = 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+ litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
case (bankmachine6_state)
1'd1: begin
end
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready;
+ litedramcore_bankmachine6_cmd_payload_is_write = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+ case (bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready = litedramcore_bankmachine6_cmd_ready;
end else begin
end
end else begin
end
endcase
end
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
- case (bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel = 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
always @(*) begin
litedramcore_bankmachine6_row_open = 1'd0;
case (bankmachine6_state)
endcase
end
always @(*) begin
- litedramcore_bankmachine7_refresh_gnt = 1'd0;
+ litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt = 1'd1;
- end
end
3'd5: begin
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_cmd_valid = 1'd0;
+ litedramcore_bankmachine7_refresh_gnt = 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid = 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid = 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt = 1'd1;
+ end
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid = 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
end
always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+ litedramcore_bankmachine7_cmd_valid = 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid = 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel = 1'd1;
+ litedramcore_bankmachine7_cmd_valid = 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid = 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
end
litedramcore_choose_cmd_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
-assign litedramcore_choose_cmd_cmd_valid = comb_rhs_array_muxed0;
-assign litedramcore_choose_cmd_cmd_payload_a = comb_rhs_array_muxed1;
-assign litedramcore_choose_cmd_cmd_payload_ba = comb_rhs_array_muxed2;
-assign litedramcore_choose_cmd_cmd_payload_is_read = comb_rhs_array_muxed3;
-assign litedramcore_choose_cmd_cmd_payload_is_write = comb_rhs_array_muxed4;
-assign litedramcore_choose_cmd_cmd_payload_is_cmd = comb_rhs_array_muxed5;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas = comb_t_array_muxed0;
+ litedramcore_choose_cmd_cmd_payload_cas = t_array_muxed0;
end
end
always @(*) begin
litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras = comb_t_array_muxed1;
+ litedramcore_choose_cmd_cmd_payload_ras = t_array_muxed1;
end
end
always @(*) begin
litedramcore_choose_cmd_cmd_payload_we = 1'd0;
if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we = comb_t_array_muxed2;
+ litedramcore_choose_cmd_cmd_payload_we = t_array_muxed2;
end
end
always @(*) begin
litedramcore_choose_req_valids[7] = (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
-assign litedramcore_choose_req_cmd_valid = comb_rhs_array_muxed6;
-assign litedramcore_choose_req_cmd_payload_a = comb_rhs_array_muxed7;
-assign litedramcore_choose_req_cmd_payload_ba = comb_rhs_array_muxed8;
-assign litedramcore_choose_req_cmd_payload_is_read = comb_rhs_array_muxed9;
-assign litedramcore_choose_req_cmd_payload_is_write = comb_rhs_array_muxed10;
-assign litedramcore_choose_req_cmd_payload_is_cmd = comb_rhs_array_muxed11;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
litedramcore_choose_req_cmd_payload_cas = 1'd0;
if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas = comb_t_array_muxed3;
+ litedramcore_choose_req_cmd_payload_cas = t_array_muxed3;
end
end
always @(*) begin
litedramcore_choose_req_cmd_payload_ras = 1'd0;
if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras = comb_t_array_muxed4;
+ litedramcore_choose_req_cmd_payload_ras = t_array_muxed4;
end
end
always @(*) begin
litedramcore_choose_req_cmd_payload_we = 1'd0;
if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we = comb_t_array_muxed5;
+ litedramcore_choose_req_cmd_payload_we = t_array_muxed5;
end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
end
assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
-assign litedramcore_interface_bank0_addr = comb_rhs_array_muxed12;
-assign litedramcore_interface_bank0_we = comb_rhs_array_muxed13;
-assign litedramcore_interface_bank0_valid = comb_rhs_array_muxed14;
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
-assign litedramcore_interface_bank1_addr = comb_rhs_array_muxed15;
-assign litedramcore_interface_bank1_we = comb_rhs_array_muxed16;
-assign litedramcore_interface_bank1_valid = comb_rhs_array_muxed17;
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
-assign litedramcore_interface_bank2_addr = comb_rhs_array_muxed18;
-assign litedramcore_interface_bank2_we = comb_rhs_array_muxed19;
-assign litedramcore_interface_bank2_valid = comb_rhs_array_muxed20;
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
-assign litedramcore_interface_bank3_addr = comb_rhs_array_muxed21;
-assign litedramcore_interface_bank3_we = comb_rhs_array_muxed22;
-assign litedramcore_interface_bank3_valid = comb_rhs_array_muxed23;
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
-assign litedramcore_interface_bank4_addr = comb_rhs_array_muxed24;
-assign litedramcore_interface_bank4_we = comb_rhs_array_muxed25;
-assign litedramcore_interface_bank4_valid = comb_rhs_array_muxed26;
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
-assign litedramcore_interface_bank5_addr = comb_rhs_array_muxed27;
-assign litedramcore_interface_bank5_we = comb_rhs_array_muxed28;
-assign litedramcore_interface_bank5_valid = comb_rhs_array_muxed29;
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
-assign litedramcore_interface_bank6_addr = comb_rhs_array_muxed30;
-assign litedramcore_interface_bank6_we = comb_rhs_array_muxed31;
-assign litedramcore_interface_bank6_valid = comb_rhs_array_muxed32;
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
-assign litedramcore_interface_bank7_addr = comb_rhs_array_muxed33;
-assign litedramcore_interface_bank7_we = comb_rhs_array_muxed34;
-assign litedramcore_interface_bank7_valid = comb_rhs_array_muxed35;
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
assign user_port_wdata_ready = new_master_wdata_ready2;
assign user_port_rdata_valid = new_master_rdata_valid9;
assign litedramcore_wishbone_cti = wb_bus_cti;
assign litedramcore_wishbone_bte = wb_bus_bte;
assign wb_bus_err = litedramcore_wishbone_err;
-always @(*) begin
- csrbank0_sel = 1'd0;
- csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
- if (interface0_bank_bus_adr[0]) begin
- csrbank0_sel = 1'd0;
- end
-end
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 2'd2);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd0));
-assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd0));
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd0));
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
-assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[1] == 1'd1));
-assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[1] == 1'd1));
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[0] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[0] == 1'd1));
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
-always @(*) begin
- csrbank1_sel = 1'd0;
- csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
- if (interface1_bank_bus_adr[0]) begin
- csrbank1_sel = 1'd0;
- end
-end
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
-assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 1'd0));
-assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 1'd0));
+assign csrbank1_dfii_control0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd0));
+assign csrbank1_dfii_control0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd0));
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 1'd1));
-assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 1'd1));
+assign csrbank1_dfii_pi0_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 1'd1));
+assign csrbank1_dfii_pi0_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 1'd1));
assign litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 2'd2));
-assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 2'd2));
-assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
-assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 2'd3));
-assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 2'd3));
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd2));
+assign csrbank1_dfii_pi0_address1_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi0_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 2'd3));
+assign csrbank1_dfii_pi0_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 2'd3));
+assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd4));
+assign csrbank1_dfii_pi0_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd4));
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd4));
-assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd4));
-assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd5));
-assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd5));
-assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi0_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd6));
-assign csrbank1_dfii_pi0_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd6));
+assign csrbank1_dfii_pi0_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd5));
+assign csrbank1_dfii_pi0_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd5));
+assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd6));
+assign csrbank1_dfii_pi0_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd6));
+assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 3'd7));
+assign csrbank1_dfii_pi0_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 3'd7));
+assign csrbank1_dfii_pi0_wrdata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd8));
+assign csrbank1_dfii_pi0_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd8));
+assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd9));
+assign csrbank1_dfii_pi0_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd9));
+assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd10));
+assign csrbank1_dfii_pi0_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd10));
+assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd11));
+assign csrbank1_dfii_pi0_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd11));
+assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd12));
+assign csrbank1_dfii_pi0_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd12));
+assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi0_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd13));
+assign csrbank1_dfii_pi0_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd13));
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 3'd7));
-assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 3'd7));
+assign csrbank1_dfii_pi1_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd14));
+assign csrbank1_dfii_pi1_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd14));
assign litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd8));
-assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd8));
-assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
-assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd9));
-assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd9));
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 4'd15));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 4'd15));
+assign csrbank1_dfii_pi1_address1_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi1_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd16));
+assign csrbank1_dfii_pi1_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd16));
+assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd17));
+assign csrbank1_dfii_pi1_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd17));
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd10));
-assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd10));
-assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd11));
-assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd11));
-assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi1_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd12));
-assign csrbank1_dfii_pi1_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd12));
+assign csrbank1_dfii_pi1_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd18));
+assign csrbank1_dfii_pi1_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd18));
+assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd19));
+assign csrbank1_dfii_pi1_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd19));
+assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd20));
+assign csrbank1_dfii_pi1_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd20));
+assign csrbank1_dfii_pi1_wrdata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd21));
+assign csrbank1_dfii_pi1_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd21));
+assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd22));
+assign csrbank1_dfii_pi1_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd22));
+assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd23));
+assign csrbank1_dfii_pi1_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd23));
+assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd24));
+assign csrbank1_dfii_pi1_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd24));
+assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd25));
+assign csrbank1_dfii_pi1_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd25));
+assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi1_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd26));
+assign csrbank1_dfii_pi1_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd26));
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd13));
-assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd13));
+assign csrbank1_dfii_pi2_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd27));
+assign csrbank1_dfii_pi2_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd27));
assign litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd14));
-assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd14));
-assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
-assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 4'd15));
-assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 4'd15));
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd28));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd28));
+assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi2_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd29));
+assign csrbank1_dfii_pi2_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd29));
+assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd30));
+assign csrbank1_dfii_pi2_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd30));
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd16));
-assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd16));
-assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd17));
-assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd17));
-assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi2_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd18));
-assign csrbank1_dfii_pi2_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd18));
+assign csrbank1_dfii_pi2_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 5'd31));
+assign csrbank1_dfii_pi2_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 5'd31));
+assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd32));
+assign csrbank1_dfii_pi2_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd32));
+assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd33));
+assign csrbank1_dfii_pi2_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd33));
+assign csrbank1_dfii_pi2_wrdata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd34));
+assign csrbank1_dfii_pi2_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd34));
+assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd35));
+assign csrbank1_dfii_pi2_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd35));
+assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd36));
+assign csrbank1_dfii_pi2_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd36));
+assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd37));
+assign csrbank1_dfii_pi2_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd37));
+assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd38));
+assign csrbank1_dfii_pi2_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd38));
+assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi2_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd39));
+assign csrbank1_dfii_pi2_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd39));
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
-assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd19));
-assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd19));
+assign csrbank1_dfii_pi3_command0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd40));
+assign csrbank1_dfii_pi3_command0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd40));
assign litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
-assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd20));
-assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd20));
-assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
-assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd21));
-assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd21));
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd41));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd41));
+assign csrbank1_dfii_pi3_address1_r = interface1_bank_bus_dat_w[5:0];
+assign csrbank1_dfii_pi3_address1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd42));
+assign csrbank1_dfii_pi3_address1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd42));
+assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_address0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd43));
+assign csrbank1_dfii_pi3_address0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd43));
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
-assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd22));
-assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd22));
-assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd23));
-assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd23));
-assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
-assign csrbank1_dfii_pi3_rddata_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:1] == 5'd24));
-assign csrbank1_dfii_pi3_rddata_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:1] == 5'd24));
+assign csrbank1_dfii_pi3_baddress0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd44));
+assign csrbank1_dfii_pi3_baddress0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd44));
+assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_wrdata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd45));
+assign csrbank1_dfii_pi3_wrdata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd45));
+assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_wrdata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd46));
+assign csrbank1_dfii_pi3_wrdata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd46));
+assign csrbank1_dfii_pi3_wrdata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_wrdata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd47));
+assign csrbank1_dfii_pi3_wrdata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd47));
+assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_wrdata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd48));
+assign csrbank1_dfii_pi3_wrdata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd48));
+assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_rddata3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd49));
+assign csrbank1_dfii_pi3_rddata3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd49));
+assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_rddata2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd50));
+assign csrbank1_dfii_pi3_rddata2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd50));
+assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_rddata1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd51));
+assign csrbank1_dfii_pi3_rddata1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd51));
+assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
+assign csrbank1_dfii_pi3_rddata0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[5:0] == 6'd52));
+assign csrbank1_dfii_pi3_rddata0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[5:0] == 6'd52));
assign csrbank1_dfii_control0_w = litedramcore_storage[3:0];
assign csrbank1_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
-assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[13:0];
+assign csrbank1_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8];
+assign csrbank1_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
assign csrbank1_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
-assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[31:0];
-assign csrbank1_dfii_pi0_rddata_w = litedramcore_phaseinjector0_status[31:0];
-assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata_we;
+assign csrbank1_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
+assign csrbank1_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
+assign csrbank1_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
+assign csrbank1_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
+assign csrbank1_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
+assign csrbank1_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
+assign csrbank1_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
+assign csrbank1_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
+assign litedramcore_phaseinjector0_we = csrbank1_dfii_pi0_rddata0_we;
assign csrbank1_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
-assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[13:0];
+assign csrbank1_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8];
+assign csrbank1_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
assign csrbank1_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
-assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[31:0];
-assign csrbank1_dfii_pi1_rddata_w = litedramcore_phaseinjector1_status[31:0];
-assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata_we;
+assign csrbank1_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
+assign csrbank1_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
+assign csrbank1_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
+assign csrbank1_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
+assign csrbank1_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
+assign csrbank1_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
+assign csrbank1_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
+assign csrbank1_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
+assign litedramcore_phaseinjector1_we = csrbank1_dfii_pi1_rddata0_we;
assign csrbank1_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
-assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[13:0];
+assign csrbank1_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8];
+assign csrbank1_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
assign csrbank1_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
-assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[31:0];
-assign csrbank1_dfii_pi2_rddata_w = litedramcore_phaseinjector2_status[31:0];
-assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata_we;
+assign csrbank1_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
+assign csrbank1_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
+assign csrbank1_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
+assign csrbank1_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
+assign csrbank1_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
+assign csrbank1_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
+assign csrbank1_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
+assign csrbank1_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
+assign litedramcore_phaseinjector2_we = csrbank1_dfii_pi2_rddata0_we;
assign csrbank1_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
-assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[13:0];
+assign csrbank1_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8];
+assign csrbank1_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
assign csrbank1_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
-assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
-assign csrbank1_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
-assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata_we;
+assign csrbank1_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
+assign csrbank1_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
+assign csrbank1_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
+assign csrbank1_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
+assign csrbank1_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
+assign csrbank1_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
+assign csrbank1_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
+assign csrbank1_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
+assign litedramcore_phaseinjector3_we = csrbank1_dfii_pi3_rddata0_we;
assign adr = litedramcore_adr;
assign we = litedramcore_we;
assign dat_w = litedramcore_dat_w;
assign slice_proxy14 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_write_col);
assign slice_proxy15 = ((ddrphy_bankmodel7_row * 11'd1024) | ddrphy_bankmodel7_read_col);
always @(*) begin
- comb_rhs_array_muxed0 = 1'd0;
+ rhs_array_muxed0 = 1'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[0];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[0];
end
1'd1: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[1];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[1];
end
2'd2: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[2];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[2];
end
2'd3: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[3];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[3];
end
3'd4: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[4];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[4];
end
3'd5: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[5];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[5];
end
3'd6: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[6];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[6];
end
default: begin
- comb_rhs_array_muxed0 = litedramcore_choose_cmd_valids[7];
+ rhs_array_muxed0 = litedramcore_choose_cmd_valids[7];
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed1 = 14'd0;
+ rhs_array_muxed1 = 14'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
- comb_rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a;
+ rhs_array_muxed1 = litedramcore_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed2 = 3'd0;
+ rhs_array_muxed2 = 3'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
- comb_rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba;
+ rhs_array_muxed2 = litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed3 = 1'd0;
+ rhs_array_muxed3 = 1'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
- comb_rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read;
+ rhs_array_muxed3 = litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed4 = 1'd0;
+ rhs_array_muxed4 = 1'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
- comb_rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write;
+ rhs_array_muxed4 = litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed5 = 1'd0;
+ rhs_array_muxed5 = 1'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
- comb_rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd;
+ rhs_array_muxed5 = litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
- comb_t_array_muxed0 = 1'd0;
+ t_array_muxed0 = 1'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
- comb_t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
- comb_t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
- comb_t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
- comb_t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
- comb_t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
- comb_t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
- comb_t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas;
+ t_array_muxed0 = litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
- comb_t_array_muxed1 = 1'd0;
+ t_array_muxed1 = 1'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
- comb_t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
- comb_t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
- comb_t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
- comb_t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
- comb_t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
- comb_t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
- comb_t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras;
+ t_array_muxed1 = litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
- comb_t_array_muxed2 = 1'd0;
+ t_array_muxed2 = 1'd0;
case (litedramcore_choose_cmd_grant)
1'd0: begin
- comb_t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
- comb_t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
- comb_t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
- comb_t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
- comb_t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
- comb_t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
- comb_t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
- comb_t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we;
+ t_array_muxed2 = litedramcore_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed6 = 1'd0;
+ rhs_array_muxed6 = 1'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[0];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[0];
end
1'd1: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[1];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[1];
end
2'd2: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[2];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[2];
end
2'd3: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[3];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[3];
end
3'd4: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[4];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[4];
end
3'd5: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[5];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[5];
end
3'd6: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[6];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[6];
end
default: begin
- comb_rhs_array_muxed6 = litedramcore_choose_req_valids[7];
+ rhs_array_muxed6 = litedramcore_choose_req_valids[7];
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed7 = 14'd0;
+ rhs_array_muxed7 = 14'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine0_cmd_payload_a;
end
1'd1: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine1_cmd_payload_a;
end
2'd2: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine2_cmd_payload_a;
end
2'd3: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine3_cmd_payload_a;
end
3'd4: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine4_cmd_payload_a;
end
3'd5: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine5_cmd_payload_a;
end
3'd6: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine6_cmd_payload_a;
end
default: begin
- comb_rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a;
+ rhs_array_muxed7 = litedramcore_bankmachine7_cmd_payload_a;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed8 = 3'd0;
+ rhs_array_muxed8 = 3'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine0_cmd_payload_ba;
end
1'd1: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine1_cmd_payload_ba;
end
2'd2: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine2_cmd_payload_ba;
end
2'd3: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine3_cmd_payload_ba;
end
3'd4: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine4_cmd_payload_ba;
end
3'd5: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine5_cmd_payload_ba;
end
3'd6: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine6_cmd_payload_ba;
end
default: begin
- comb_rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba;
+ rhs_array_muxed8 = litedramcore_bankmachine7_cmd_payload_ba;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed9 = 1'd0;
+ rhs_array_muxed9 = 1'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine0_cmd_payload_is_read;
end
1'd1: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine1_cmd_payload_is_read;
end
2'd2: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine2_cmd_payload_is_read;
end
2'd3: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine3_cmd_payload_is_read;
end
3'd4: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine4_cmd_payload_is_read;
end
3'd5: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine5_cmd_payload_is_read;
end
3'd6: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine6_cmd_payload_is_read;
end
default: begin
- comb_rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read;
+ rhs_array_muxed9 = litedramcore_bankmachine7_cmd_payload_is_read;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed10 = 1'd0;
+ rhs_array_muxed10 = 1'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine0_cmd_payload_is_write;
end
1'd1: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine1_cmd_payload_is_write;
end
2'd2: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine2_cmd_payload_is_write;
end
2'd3: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine3_cmd_payload_is_write;
end
3'd4: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine4_cmd_payload_is_write;
end
3'd5: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine5_cmd_payload_is_write;
end
3'd6: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine6_cmd_payload_is_write;
end
default: begin
- comb_rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write;
+ rhs_array_muxed10 = litedramcore_bankmachine7_cmd_payload_is_write;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed11 = 1'd0;
+ rhs_array_muxed11 = 1'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine0_cmd_payload_is_cmd;
end
1'd1: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine1_cmd_payload_is_cmd;
end
2'd2: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine2_cmd_payload_is_cmd;
end
2'd3: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine3_cmd_payload_is_cmd;
end
3'd4: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine4_cmd_payload_is_cmd;
end
3'd5: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine5_cmd_payload_is_cmd;
end
3'd6: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine6_cmd_payload_is_cmd;
end
default: begin
- comb_rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd;
+ rhs_array_muxed11 = litedramcore_bankmachine7_cmd_payload_is_cmd;
end
endcase
end
always @(*) begin
- comb_t_array_muxed3 = 1'd0;
+ t_array_muxed3 = 1'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine0_cmd_payload_cas;
end
1'd1: begin
- comb_t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine1_cmd_payload_cas;
end
2'd2: begin
- comb_t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine2_cmd_payload_cas;
end
2'd3: begin
- comb_t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine3_cmd_payload_cas;
end
3'd4: begin
- comb_t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine4_cmd_payload_cas;
end
3'd5: begin
- comb_t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine5_cmd_payload_cas;
end
3'd6: begin
- comb_t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine6_cmd_payload_cas;
end
default: begin
- comb_t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas;
+ t_array_muxed3 = litedramcore_bankmachine7_cmd_payload_cas;
end
endcase
end
always @(*) begin
- comb_t_array_muxed4 = 1'd0;
+ t_array_muxed4 = 1'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine0_cmd_payload_ras;
end
1'd1: begin
- comb_t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine1_cmd_payload_ras;
end
2'd2: begin
- comb_t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine2_cmd_payload_ras;
end
2'd3: begin
- comb_t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine3_cmd_payload_ras;
end
3'd4: begin
- comb_t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine4_cmd_payload_ras;
end
3'd5: begin
- comb_t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine5_cmd_payload_ras;
end
3'd6: begin
- comb_t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine6_cmd_payload_ras;
end
default: begin
- comb_t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras;
+ t_array_muxed4 = litedramcore_bankmachine7_cmd_payload_ras;
end
endcase
end
always @(*) begin
- comb_t_array_muxed5 = 1'd0;
+ t_array_muxed5 = 1'd0;
case (litedramcore_choose_req_grant)
1'd0: begin
- comb_t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine0_cmd_payload_we;
end
1'd1: begin
- comb_t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine1_cmd_payload_we;
end
2'd2: begin
- comb_t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine2_cmd_payload_we;
end
2'd3: begin
- comb_t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine3_cmd_payload_we;
end
3'd4: begin
- comb_t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine4_cmd_payload_we;
end
3'd5: begin
- comb_t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine5_cmd_payload_we;
end
3'd6: begin
- comb_t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine6_cmd_payload_we;
end
default: begin
- comb_t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we;
+ t_array_muxed5 = litedramcore_bankmachine7_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed12 = 21'd0;
+ rhs_array_muxed12 = 21'd0;
case (roundrobin0_grant)
default: begin
- comb_rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed12 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed13 = 1'd0;
+ rhs_array_muxed13 = 1'd0;
case (roundrobin0_grant)
default: begin
- comb_rhs_array_muxed13 = user_port_cmd_payload_we;
+ rhs_array_muxed13 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed14 = 1'd0;
+ rhs_array_muxed14 = 1'd0;
case (roundrobin0_grant)
default: begin
- comb_rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ rhs_array_muxed14 = (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed15 = 21'd0;
+ rhs_array_muxed15 = 21'd0;
case (roundrobin1_grant)
default: begin
- comb_rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed15 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed16 = 1'd0;
+ rhs_array_muxed16 = 1'd0;
case (roundrobin1_grant)
default: begin
- comb_rhs_array_muxed16 = user_port_cmd_payload_we;
+ rhs_array_muxed16 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed17 = 1'd0;
+ rhs_array_muxed17 = 1'd0;
case (roundrobin1_grant)
default: begin
- comb_rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ rhs_array_muxed17 = (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed18 = 21'd0;
+ rhs_array_muxed18 = 21'd0;
case (roundrobin2_grant)
default: begin
- comb_rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed18 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed19 = 1'd0;
+ rhs_array_muxed19 = 1'd0;
case (roundrobin2_grant)
default: begin
- comb_rhs_array_muxed19 = user_port_cmd_payload_we;
+ rhs_array_muxed19 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed20 = 1'd0;
+ rhs_array_muxed20 = 1'd0;
case (roundrobin2_grant)
default: begin
- comb_rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ rhs_array_muxed20 = (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed21 = 21'd0;
+ rhs_array_muxed21 = 21'd0;
case (roundrobin3_grant)
default: begin
- comb_rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed21 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed22 = 1'd0;
+ rhs_array_muxed22 = 1'd0;
case (roundrobin3_grant)
default: begin
- comb_rhs_array_muxed22 = user_port_cmd_payload_we;
+ rhs_array_muxed22 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed23 = 1'd0;
+ rhs_array_muxed23 = 1'd0;
case (roundrobin3_grant)
default: begin
- comb_rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ rhs_array_muxed23 = (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed24 = 21'd0;
+ rhs_array_muxed24 = 21'd0;
case (roundrobin4_grant)
default: begin
- comb_rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed24 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed25 = 1'd0;
+ rhs_array_muxed25 = 1'd0;
case (roundrobin4_grant)
default: begin
- comb_rhs_array_muxed25 = user_port_cmd_payload_we;
+ rhs_array_muxed25 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed26 = 1'd0;
+ rhs_array_muxed26 = 1'd0;
case (roundrobin4_grant)
default: begin
- comb_rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ rhs_array_muxed26 = (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed27 = 21'd0;
+ rhs_array_muxed27 = 21'd0;
case (roundrobin5_grant)
default: begin
- comb_rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed27 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed28 = 1'd0;
+ rhs_array_muxed28 = 1'd0;
case (roundrobin5_grant)
default: begin
- comb_rhs_array_muxed28 = user_port_cmd_payload_we;
+ rhs_array_muxed28 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed29 = 1'd0;
+ rhs_array_muxed29 = 1'd0;
case (roundrobin5_grant)
default: begin
- comb_rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ rhs_array_muxed29 = (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed30 = 21'd0;
+ rhs_array_muxed30 = 21'd0;
case (roundrobin6_grant)
default: begin
- comb_rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed30 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed31 = 1'd0;
+ rhs_array_muxed31 = 1'd0;
case (roundrobin6_grant)
default: begin
- comb_rhs_array_muxed31 = user_port_cmd_payload_we;
+ rhs_array_muxed31 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed32 = 1'd0;
+ rhs_array_muxed32 = 1'd0;
case (roundrobin6_grant)
default: begin
- comb_rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ rhs_array_muxed32 = (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed33 = 21'd0;
+ rhs_array_muxed33 = 21'd0;
case (roundrobin7_grant)
default: begin
- comb_rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ rhs_array_muxed33 = {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed34 = 1'd0;
+ rhs_array_muxed34 = 1'd0;
case (roundrobin7_grant)
default: begin
- comb_rhs_array_muxed34 = user_port_cmd_payload_we;
+ rhs_array_muxed34 = user_port_cmd_payload_we;
end
endcase
end
always @(*) begin
- comb_rhs_array_muxed35 = 1'd0;
+ rhs_array_muxed35 = 1'd0;
case (roundrobin7_grant)
default: begin
- comb_rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed0 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed0 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed1 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next0)
- 1'd0: begin
- sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed1 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed2 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed2 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed3 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next1)
- 1'd0: begin
- sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed3 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed4 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed4 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed5 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next2)
- 1'd0: begin
- sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed5 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed6 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed6 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed7 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next3)
- 1'd0: begin
- sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed7 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed8 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed8 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed9 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next4)
- 1'd0: begin
- sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed9 = ddrphy_dfitimingschecker3;
+ rhs_array_muxed35 = (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed10 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed0 = 3'd0;
+ case (litedramcore_steerer_sel0)
1'd0: begin
- sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker0;
+ array_muxed0 = litedramcore_nop_ba[2:0];
end
1'd1: begin
- sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker1;
+ array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker2;
+ array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- sync_basiclowerer_array_muxed10 = ddrphy_dfitimingschecker3;
+ array_muxed0 = litedramcore_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed11 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next5)
+ array_muxed1 = 14'd0;
+ case (litedramcore_steerer_sel0)
1'd0: begin
- sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker0;
+ array_muxed1 = litedramcore_nop_a;
end
1'd1: begin
- sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker1;
+ array_muxed1 = litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker2;
+ array_muxed1 = litedramcore_choose_req_cmd_payload_a;
end
default: begin
- sync_basiclowerer_array_muxed11 = ddrphy_dfitimingschecker3;
+ array_muxed1 = litedramcore_cmd_payload_a;
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed12 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed2 = 1'd0;
+ case (litedramcore_steerer_sel0)
1'd0: begin
- sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker0;
+ array_muxed2 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker1;
+ array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker2;
+ array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- sync_basiclowerer_array_muxed12 = ddrphy_dfitimingschecker3;
+ array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed13 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next6)
+ array_muxed3 = 1'd0;
+ case (litedramcore_steerer_sel0)
1'd0: begin
- sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker0;
+ array_muxed3 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker1;
+ array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker2;
+ array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- sync_basiclowerer_array_muxed13 = ddrphy_dfitimingschecker3;
+ array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed14 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed4 = 1'd0;
+ case (litedramcore_steerer_sel0)
1'd0: begin
- sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker0;
+ array_muxed4 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker1;
+ array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker2;
+ array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
end
default: begin
- sync_basiclowerer_array_muxed14 = ddrphy_dfitimingschecker3;
+ array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed15 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next7)
+ array_muxed5 = 1'd0;
+ case (litedramcore_steerer_sel0)
1'd0: begin
- sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker0;
+ array_muxed5 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker1;
+ array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker2;
+ array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- sync_basiclowerer_array_muxed15 = ddrphy_dfitimingschecker3;
+ array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed16 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed6 = 1'd0;
+ case (litedramcore_steerer_sel0)
1'd0: begin
- sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker0;
+ array_muxed6 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker1;
+ array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker2;
+ array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- sync_basiclowerer_array_muxed16 = ddrphy_dfitimingschecker3;
+ array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed17 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next8)
+ array_muxed7 = 3'd0;
+ case (litedramcore_steerer_sel1)
1'd0: begin
- sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker0;
+ array_muxed7 = litedramcore_nop_ba[2:0];
end
1'd1: begin
- sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker1;
+ array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker2;
+ array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- sync_basiclowerer_array_muxed17 = ddrphy_dfitimingschecker3;
+ array_muxed7 = litedramcore_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed18 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed8 = 14'd0;
+ case (litedramcore_steerer_sel1)
1'd0: begin
- sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker0;
+ array_muxed8 = litedramcore_nop_a;
end
1'd1: begin
- sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker1;
+ array_muxed8 = litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker2;
+ array_muxed8 = litedramcore_choose_req_cmd_payload_a;
end
default: begin
- sync_basiclowerer_array_muxed18 = ddrphy_dfitimingschecker3;
+ array_muxed8 = litedramcore_cmd_payload_a;
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed19 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next9)
+ array_muxed9 = 1'd0;
+ case (litedramcore_steerer_sel1)
1'd0: begin
- sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker0;
+ array_muxed9 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker1;
+ array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker2;
+ array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- sync_basiclowerer_array_muxed19 = ddrphy_dfitimingschecker3;
+ array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed20 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed10 = 1'd0;
+ case (litedramcore_steerer_sel1)
1'd0: begin
- sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker0;
+ array_muxed10 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker1;
+ array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker2;
+ array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- sync_basiclowerer_array_muxed20 = ddrphy_dfitimingschecker3;
+ array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed21 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next10)
+ array_muxed11 = 1'd0;
+ case (litedramcore_steerer_sel1)
1'd0: begin
- sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker0;
+ array_muxed11 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker1;
+ array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
end
2'd2: begin
- sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker2;
+ array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
end
default: begin
- sync_basiclowerer_array_muxed21 = ddrphy_dfitimingschecker3;
+ array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed22 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed12 = 1'd0;
+ case (litedramcore_steerer_sel1)
1'd0: begin
- sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker0;
+ array_muxed12 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker1;
+ array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
end
2'd2: begin
- sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker2;
+ array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
end
default: begin
- sync_basiclowerer_array_muxed22 = ddrphy_dfitimingschecker3;
+ array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed23 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next11)
+ array_muxed13 = 1'd0;
+ case (litedramcore_steerer_sel1)
1'd0: begin
- sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker0;
+ array_muxed13 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker1;
+ array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
end
2'd2: begin
- sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker2;
+ array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
end
default: begin
- sync_basiclowerer_array_muxed23 = ddrphy_dfitimingschecker3;
+ array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed24 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed14 = 3'd0;
+ case (litedramcore_steerer_sel2)
1'd0: begin
- sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker0;
+ array_muxed14 = litedramcore_nop_ba[2:0];
end
1'd1: begin
- sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker1;
+ array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
end
2'd2: begin
- sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker2;
+ array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0];
end
default: begin
- sync_basiclowerer_array_muxed24 = ddrphy_dfitimingschecker3;
+ array_muxed14 = litedramcore_cmd_payload_ba[2:0];
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed25 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next12)
+ array_muxed15 = 14'd0;
+ case (litedramcore_steerer_sel2)
1'd0: begin
- sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker0;
+ array_muxed15 = litedramcore_nop_a;
end
1'd1: begin
- sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker1;
+ array_muxed15 = litedramcore_choose_cmd_cmd_payload_a;
end
2'd2: begin
- sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker2;
+ array_muxed15 = litedramcore_choose_req_cmd_payload_a;
end
default: begin
- sync_basiclowerer_array_muxed25 = ddrphy_dfitimingschecker3;
+ array_muxed15 = litedramcore_cmd_payload_a;
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed26 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
+ array_muxed16 = 1'd0;
+ case (litedramcore_steerer_sel2)
1'd0: begin
- sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker0;
+ array_muxed16 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker1;
+ array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
end
2'd2: begin
- sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker2;
+ array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
end
default: begin
- sync_basiclowerer_array_muxed26 = ddrphy_dfitimingschecker3;
+ array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed27 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next13)
+ array_muxed17 = 1'd0;
+ case (litedramcore_steerer_sel2)
1'd0: begin
- sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker0;
+ array_muxed17 = 1'd0;
end
1'd1: begin
- sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker1;
+ array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
end
2'd2: begin
- sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker2;
+ array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
end
default: begin
- sync_basiclowerer_array_muxed27 = ddrphy_dfitimingschecker3;
+ array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
end
endcase
end
always @(*) begin
- sync_basiclowerer_array_muxed28 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed28 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed29 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next14)
- 1'd0: begin
- sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed29 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed30 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed30 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed31 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next15)
- 1'd0: begin
- sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed31 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed32 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed32 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed33 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next16)
- 1'd0: begin
- sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed33 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed34 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed34 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed35 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next17)
- 1'd0: begin
- sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed35 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed36 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed36 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed37 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next18)
- 1'd0: begin
- sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed37 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed38 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed38 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed39 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next19)
- 1'd0: begin
- sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed39 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed40 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed40 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed41 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next20)
- 1'd0: begin
- sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed41 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed42 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed42 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed43 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next21)
- 1'd0: begin
- sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed43 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed44 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed44 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed45 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next22)
- 1'd0: begin
- sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed45 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed46 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed46 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed47 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next23)
- 1'd0: begin
- sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed47 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed48 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed48 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed49 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next24)
- 1'd0: begin
- sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed49 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed50 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed50 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed51 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next25)
- 1'd0: begin
- sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed51 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed52 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed52 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed53 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next26)
- 1'd0: begin
- sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed53 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed54 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed54 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed55 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next27)
- 1'd0: begin
- sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed55 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed56 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed56 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed57 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next28)
- 1'd0: begin
- sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed57 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed58 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed58 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed59 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next29)
- 1'd0: begin
- sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed59 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed60 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed60 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed61 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next30)
- 1'd0: begin
- sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed61 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed62 = 64'd0;
- case (ddrphy_dfitimingschecker_act_curr)
- 1'd0: begin
- sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed62 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_basiclowerer_array_muxed63 = 64'd0;
- case (ddrphy_dfitimingschecker_act_next31)
- 1'd0: begin
- sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker0;
- end
- 1'd1: begin
- sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker1;
- end
- 2'd2: begin
- sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker2;
- end
- default: begin
- sync_basiclowerer_array_muxed63 = ddrphy_dfitimingschecker3;
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed0 = 3'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- sync_rhs_array_muxed0 = litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- sync_rhs_array_muxed0 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- sync_rhs_array_muxed0 = litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- sync_rhs_array_muxed0 = litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed1 = 14'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- sync_rhs_array_muxed1 = litedramcore_nop_a;
- end
- 1'd1: begin
- sync_rhs_array_muxed1 = litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- sync_rhs_array_muxed1 = litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- sync_rhs_array_muxed1 = litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed2 = 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- sync_rhs_array_muxed2 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed2 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- sync_rhs_array_muxed2 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- sync_rhs_array_muxed2 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed3 = 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- sync_rhs_array_muxed3 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed3 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- sync_rhs_array_muxed3 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- sync_rhs_array_muxed3 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed4 = 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- sync_rhs_array_muxed4 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed4 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- sync_rhs_array_muxed4 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- sync_rhs_array_muxed4 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed5 = 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- sync_rhs_array_muxed5 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed5 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- sync_rhs_array_muxed5 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- sync_rhs_array_muxed5 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed6 = 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- sync_rhs_array_muxed6 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed6 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- sync_rhs_array_muxed6 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- sync_rhs_array_muxed6 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed7 = 3'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- sync_rhs_array_muxed7 = litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- sync_rhs_array_muxed7 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- sync_rhs_array_muxed7 = litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- sync_rhs_array_muxed7 = litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed8 = 14'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- sync_rhs_array_muxed8 = litedramcore_nop_a;
- end
- 1'd1: begin
- sync_rhs_array_muxed8 = litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- sync_rhs_array_muxed8 = litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- sync_rhs_array_muxed8 = litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed9 = 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- sync_rhs_array_muxed9 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed9 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- sync_rhs_array_muxed9 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- sync_rhs_array_muxed9 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed10 = 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- sync_rhs_array_muxed10 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed10 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- sync_rhs_array_muxed10 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- sync_rhs_array_muxed10 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed11 = 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- sync_rhs_array_muxed11 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed11 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- sync_rhs_array_muxed11 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- sync_rhs_array_muxed11 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed12 = 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- sync_rhs_array_muxed12 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed12 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- sync_rhs_array_muxed12 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- sync_rhs_array_muxed12 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed13 = 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- sync_rhs_array_muxed13 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed13 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- sync_rhs_array_muxed13 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- sync_rhs_array_muxed13 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed14 = 3'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- sync_rhs_array_muxed14 = litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- sync_rhs_array_muxed14 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- sync_rhs_array_muxed14 = litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- sync_rhs_array_muxed14 = litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed15 = 14'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- sync_rhs_array_muxed15 = litedramcore_nop_a;
- end
- 1'd1: begin
- sync_rhs_array_muxed15 = litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- sync_rhs_array_muxed15 = litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- sync_rhs_array_muxed15 = litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed16 = 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- sync_rhs_array_muxed16 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed16 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- sync_rhs_array_muxed16 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- sync_rhs_array_muxed16 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed17 = 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- sync_rhs_array_muxed17 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed17 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- sync_rhs_array_muxed17 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- sync_rhs_array_muxed17 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed18 = 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- sync_rhs_array_muxed18 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- sync_rhs_array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- sync_rhs_array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed19 = 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- sync_rhs_array_muxed19 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- sync_rhs_array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- sync_rhs_array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed20 = 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- sync_rhs_array_muxed20 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- sync_rhs_array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- sync_rhs_array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed21 = 3'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- sync_rhs_array_muxed21 = litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- sync_rhs_array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- sync_rhs_array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- sync_rhs_array_muxed21 = litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed22 = 14'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- sync_rhs_array_muxed22 = litedramcore_nop_a;
- end
- 1'd1: begin
- sync_rhs_array_muxed22 = litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- sync_rhs_array_muxed22 = litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- sync_rhs_array_muxed22 = litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed23 = 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- sync_rhs_array_muxed23 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- sync_rhs_array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- sync_rhs_array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed24 = 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- sync_rhs_array_muxed24 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- sync_rhs_array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- sync_rhs_array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed25 = 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- sync_rhs_array_muxed25 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- sync_rhs_array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- sync_rhs_array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed26 = 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- sync_rhs_array_muxed26 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- sync_rhs_array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- sync_rhs_array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- sync_rhs_array_muxed27 = 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- sync_rhs_array_muxed27 = 1'd0;
- end
- 1'd1: begin
- sync_rhs_array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- sync_rhs_array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- sync_rhs_array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-
-always @(posedge por_clk) begin
- int_rst <= 1'd0;
-end
-
-always @(posedge sys_clk) begin
- state <= next_state;
- ddrphy_new_bank_write0 <= ddrphy_bank_write0;
- ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0;
- ddrphy_new_bank_write1 <= ddrphy_new_bank_write0;
- ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0;
- ddrphy_new_bank_write2 <= ddrphy_bank_write1;
- ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1;
- ddrphy_new_bank_write3 <= ddrphy_new_bank_write2;
- ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2;
- ddrphy_new_bank_write4 <= ddrphy_bank_write2;
- ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2;
- ddrphy_new_bank_write5 <= ddrphy_new_bank_write4;
- ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4;
- ddrphy_new_bank_write6 <= ddrphy_bank_write3;
- ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3;
- ddrphy_new_bank_write7 <= ddrphy_new_bank_write6;
- ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6;
- ddrphy_new_bank_write8 <= ddrphy_bank_write4;
- ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4;
- ddrphy_new_bank_write9 <= ddrphy_new_bank_write8;
- ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8;
- ddrphy_new_bank_write10 <= ddrphy_bank_write5;
- ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5;
- ddrphy_new_bank_write11 <= ddrphy_new_bank_write10;
- ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10;
- ddrphy_new_bank_write12 <= ddrphy_bank_write6;
- ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6;
- ddrphy_new_bank_write13 <= ddrphy_new_bank_write12;
- ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12;
- ddrphy_new_bank_write14 <= ddrphy_bank_write7;
- ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7;
- ddrphy_new_bank_write15 <= ddrphy_new_bank_write14;
- ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14;
- ddrphy_new_banks_read0 <= ddrphy_banks_read;
- ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data;
- ddrphy_new_banks_read1 <= ddrphy_new_banks_read0;
- ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0;
- ddrphy_new_banks_read2 <= ddrphy_new_banks_read1;
- ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1;
- ddrphy_new_banks_read3 <= ddrphy_new_banks_read2;
- ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2;
- ddrphy_new_banks_read4 <= ddrphy_new_banks_read3;
- ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3;
- ddrphy_new_banks_read5 <= ddrphy_new_banks_read4;
- ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4;
- ddrphy_new_banks_read6 <= ddrphy_new_banks_read5;
- ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5;
- ddrphy_new_banks_read7 <= ddrphy_new_banks_read6;
- ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6;
- ddrphy_new_banks_read8 <= ddrphy_new_banks_read7;
- ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7;
- ddrphy_dfitimingschecker_cnt <= (ddrphy_dfitimingschecker_cnt + 3'd4);
- if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv0 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv0) begin
- ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv1 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv1) begin
- ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv2) begin
- ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed0 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv2 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed1 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv2) begin
- sync_t_array_muxed0 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next0)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed0;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed0;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed0;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed0;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv3 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv3) begin
- ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv4 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv4) begin
- ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv5) begin
- ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv6 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv6) begin
- ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv7 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv7) begin
- ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv8) begin
- ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed2 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv8 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed3 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv8) begin
- sync_t_array_muxed1 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next1)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed1;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed1;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed1;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed1;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv9 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv9) begin
- ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv10 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv10) begin
- ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv11) begin
- ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv12 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv12) begin
- ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv13 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv13) begin
- ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv14) begin
- ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed4 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv14 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed5 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv14) begin
- sync_t_array_muxed2 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next2)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed2;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed2;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed2;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed2;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv15 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv15) begin
- ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv16 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv16) begin
- ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv17) begin
- ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv18 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv18) begin
- ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv19 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv19) begin
- ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv20) begin
- ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed6 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv20 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed7 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv20) begin
- sync_t_array_muxed3 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next3)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed3;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed3;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed3;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed3;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv21 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv21) begin
- ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv22 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv22) begin
- ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv23) begin
- ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv24 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv24) begin
- ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv25 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv25) begin
- ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv26) begin
- ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed8 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv26 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed9 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv26) begin
- sync_t_array_muxed4 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next4)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed4;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed4;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed4;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed4;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next4;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv27 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv27) begin
- ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv28 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv28) begin
- ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv29) begin
- ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv30 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv30) begin
- ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv31 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv31) begin
- ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv32) begin
- ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed10 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv32 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed11 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv32) begin
- sync_t_array_muxed5 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next5)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed5;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed5;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed5;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed5;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next5;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv33 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv33) begin
- ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv34 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv34) begin
- ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv35) begin
- ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv36 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv36) begin
- ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv37 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv37) begin
- ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv38) begin
- ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed12 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv38 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed13 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv38) begin
- sync_t_array_muxed6 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next6)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed6;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed6;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed6;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed6;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next6;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv39 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv39) begin
- ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv40 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv40) begin
- ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv41) begin
- ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv42 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv42) begin
- ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv43 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv43) begin
- ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv44) begin
- ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed14 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv44 & (ddrphy_dfitimingschecker_ps0 < (sync_basiclowerer_array_muxed15 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv44) begin
- sync_t_array_muxed7 = ddrphy_dfitimingschecker_ps0;
- case (ddrphy_dfitimingschecker_act_next7)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed7;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed7;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed7;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed7;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next7;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv45 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv45) begin
- ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv46 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps0 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps0, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv46) begin
- ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
- end
- if (ddrphy_dfitimingschecker_cmd_recv47) begin
- ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps0;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state0;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv48 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv48) begin
- ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv49 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv49) begin
- ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv50) begin
- ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed16 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv50 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed17 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv50) begin
- sync_t_array_muxed8 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next8)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed8;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed8;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed8;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed8;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next8;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv51 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv51) begin
- ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv52 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv52) begin
- ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv53) begin
- ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv54 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv54) begin
- ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv55 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv55) begin
- ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv56) begin
- ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed18 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv56 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed19 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv56) begin
- sync_t_array_muxed9 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next9)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed9;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed9;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed9;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed9;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next9;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv57 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv57) begin
- ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv58 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv58) begin
- ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv59) begin
- ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv60 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv60) begin
- ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv61 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv61) begin
- ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv62) begin
- ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed20 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv62 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed21 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv62) begin
- sync_t_array_muxed10 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next10)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed10;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed10;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed10;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed10;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next10;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv63 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv63) begin
- ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv64 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv64) begin
- ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv65) begin
- ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv66 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv66) begin
- ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv67 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv67) begin
- ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv68) begin
- ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed22 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv68 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed23 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv68) begin
- sync_t_array_muxed11 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next11)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed11;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed11;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed11;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed11;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next11;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv69 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv69) begin
- ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv70 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv70) begin
- ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv71) begin
- ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv72 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv72) begin
- ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv73 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv73) begin
- ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv74) begin
- ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed24 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv74 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed25 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv74) begin
- sync_t_array_muxed12 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next12)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed12;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed12;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed12;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed12;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next12;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv75 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv75) begin
- ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv76 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv76) begin
- ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv77) begin
- ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv78 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv78) begin
- ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv79 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv79) begin
- ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv80) begin
- ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed26 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv80 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed27 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv80) begin
- sync_t_array_muxed13 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next13)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed13;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed13;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed13;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed13;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next13;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv81 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv81) begin
- ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv82 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv82) begin
- ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv83) begin
- ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv84 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv84) begin
- ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv85 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv85) begin
- ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv86) begin
- ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed28 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv86 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed29 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv86) begin
- sync_t_array_muxed14 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next14)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed14;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed14;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed14;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed14;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next14;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv87 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv87) begin
- ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv88 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv88) begin
- ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv89) begin
- ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv90 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv90) begin
- ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv91 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv91) begin
- ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv92) begin
- ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed30 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv92 & (ddrphy_dfitimingschecker_ps1 < (sync_basiclowerer_array_muxed31 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv92) begin
- sync_t_array_muxed15 = ddrphy_dfitimingschecker_ps1;
- case (ddrphy_dfitimingschecker_act_next15)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed15;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed15;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed15;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed15;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next15;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv93 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv93) begin
- ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv94 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps1 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps1, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv94) begin
- ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
- end
- if (ddrphy_dfitimingschecker_cmd_recv95) begin
- ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps1;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state1;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv96 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv96) begin
- ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv97 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv97) begin
- ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv98) begin
- ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed32 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv98 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed33 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv98) begin
- sync_t_array_muxed16 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next16)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed16;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed16;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed16;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed16;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next16;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv99 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv99) begin
- ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv100 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv100) begin
- ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv101) begin
- ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv102 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv102) begin
- ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv103 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv103) begin
- ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv104) begin
- ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed34 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv104 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed35 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv104) begin
- sync_t_array_muxed17 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next17)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed17;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed17;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed17;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed17;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next17;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv105 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv105) begin
- ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv106 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv106) begin
- ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv107) begin
- ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv108 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv108) begin
- ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv109 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv109) begin
- ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv110) begin
- ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed36 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv110 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed37 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv110) begin
- sync_t_array_muxed18 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next18)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed18;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed18;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed18;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed18;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next18;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv111 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv111) begin
- ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv112 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv112) begin
- ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv113) begin
- ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv114 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv114) begin
- ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv115 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv115) begin
- ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv116) begin
- ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed38 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv116 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed39 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv116) begin
- sync_t_array_muxed19 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next19)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed19;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed19;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed19;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed19;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next19;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv117 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv117) begin
- ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv118 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv118) begin
- ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv119) begin
- ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv120 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv120) begin
- ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv121 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv121) begin
- ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv122) begin
- ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed40 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv122 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed41 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv122) begin
- sync_t_array_muxed20 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next20)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed20;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed20;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed20;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed20;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next20;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv123 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv123) begin
- ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv124 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv124) begin
- ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv125) begin
- ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv126 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv126) begin
- ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv127 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv127) begin
- ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv128) begin
- ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed42 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv128 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed43 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv128) begin
- sync_t_array_muxed21 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next21)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed21;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed21;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed21;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed21;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next21;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv129 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv129) begin
- ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv130 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv130) begin
- ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv131) begin
- ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv132 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv132) begin
- ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv133 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv133) begin
- ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv134) begin
- ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed44 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv134 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed45 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv134) begin
- sync_t_array_muxed22 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next22)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed22;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed22;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed22;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed22;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next22;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv135 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv135) begin
- ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv136 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv136) begin
- ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv137) begin
- ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv138 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv138) begin
- ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv139 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv139) begin
- ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv140) begin
- ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed46 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv140 & (ddrphy_dfitimingschecker_ps2 < (sync_basiclowerer_array_muxed47 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv140) begin
- sync_t_array_muxed23 = ddrphy_dfitimingschecker_ps2;
- case (ddrphy_dfitimingschecker_act_next23)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed23;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed23;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed23;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed23;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next23;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv141 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv141) begin
- ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv142 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps2 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps2, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv142) begin
- ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
- end
- if (ddrphy_dfitimingschecker_cmd_recv143) begin
- ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps2;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state2;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv144 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv144) begin
- ddrphy_dfitimingschecker_dfitimingschecker0 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv145 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv145) begin
- ddrphy_dfitimingschecker_dfitimingschecker1 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker0 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker1 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker5 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv146) begin
- ddrphy_dfitimingschecker_dfitimingschecker2 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed48 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv146 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed49 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv146) begin
- sync_t_array_muxed24 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next24)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed24;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed24;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed24;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed24;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next24;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv147 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv147) begin
- ddrphy_dfitimingschecker_dfitimingschecker3 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker2 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker3 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv148 & (ddrphy_dfitimingschecker_last_cmd0 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker4 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 0);
- end
- if (ddrphy_dfitimingschecker_cmd_recv148) begin
- ddrphy_dfitimingschecker_dfitimingschecker4 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv149) begin
- ddrphy_dfitimingschecker_dfitimingschecker5 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd0 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv150 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv150) begin
- ddrphy_dfitimingschecker_dfitimingschecker6 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv151 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv151) begin
- ddrphy_dfitimingschecker_dfitimingschecker7 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker6 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker7 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker11 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv152) begin
- ddrphy_dfitimingschecker_dfitimingschecker8 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed50 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv152 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed51 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv152) begin
- sync_t_array_muxed25 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next25)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed25;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed25;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed25;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed25;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next25;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv153 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv153) begin
- ddrphy_dfitimingschecker_dfitimingschecker9 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker8 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker9 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv154 & (ddrphy_dfitimingschecker_last_cmd1 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker10 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 1);
- end
- if (ddrphy_dfitimingschecker_cmd_recv154) begin
- ddrphy_dfitimingschecker_dfitimingschecker10 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv155) begin
- ddrphy_dfitimingschecker_dfitimingschecker11 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd1 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv156 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv156) begin
- ddrphy_dfitimingschecker_dfitimingschecker12 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv157 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv157) begin
- ddrphy_dfitimingschecker_dfitimingschecker13 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker12 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker13 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker17 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv158) begin
- ddrphy_dfitimingschecker_dfitimingschecker14 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed52 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv158 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed53 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv158) begin
- sync_t_array_muxed26 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next26)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed26;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed26;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed26;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed26;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next26;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv159 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv159) begin
- ddrphy_dfitimingschecker_dfitimingschecker15 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker14 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker15 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv160 & (ddrphy_dfitimingschecker_last_cmd2 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker16 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 2);
- end
- if (ddrphy_dfitimingschecker_cmd_recv160) begin
- ddrphy_dfitimingschecker_dfitimingschecker16 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv161) begin
- ddrphy_dfitimingschecker_dfitimingschecker17 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd2 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv162 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv162) begin
- ddrphy_dfitimingschecker_dfitimingschecker18 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv163 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv163) begin
- ddrphy_dfitimingschecker_dfitimingschecker19 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker18 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker19 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker23 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv164) begin
- ddrphy_dfitimingschecker_dfitimingschecker20 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed54 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv164 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed55 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv164) begin
- sync_t_array_muxed27 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next27)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed27;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed27;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed27;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed27;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next27;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv165 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv165) begin
- ddrphy_dfitimingschecker_dfitimingschecker21 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker20 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker21 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv166 & (ddrphy_dfitimingschecker_last_cmd3 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker22 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 3);
- end
- if (ddrphy_dfitimingschecker_cmd_recv166) begin
- ddrphy_dfitimingschecker_dfitimingschecker22 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv167) begin
- ddrphy_dfitimingschecker_dfitimingschecker23 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd3 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv168 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv168) begin
- ddrphy_dfitimingschecker_dfitimingschecker24 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv169 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv169) begin
- ddrphy_dfitimingschecker_dfitimingschecker25 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker24 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker25 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker29 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv170) begin
- ddrphy_dfitimingschecker_dfitimingschecker26 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed56 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv170 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed57 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv170) begin
- sync_t_array_muxed28 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next28)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed28;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed28;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed28;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed28;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next28;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv171 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv171) begin
- ddrphy_dfitimingschecker_dfitimingschecker27 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker26 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker27 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv172 & (ddrphy_dfitimingschecker_last_cmd4 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker28 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 4);
- end
- if (ddrphy_dfitimingschecker_cmd_recv172) begin
- ddrphy_dfitimingschecker_dfitimingschecker28 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv173) begin
- ddrphy_dfitimingschecker_dfitimingschecker29 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd4 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv174 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv174) begin
- ddrphy_dfitimingschecker_dfitimingschecker30 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv175 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv175) begin
- ddrphy_dfitimingschecker_dfitimingschecker31 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker30 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker31 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker35 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv176) begin
- ddrphy_dfitimingschecker_dfitimingschecker32 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed58 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv176 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed59 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv176) begin
- sync_t_array_muxed29 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next29)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed29;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed29;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed29;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed29;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next29;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv177 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv177) begin
- ddrphy_dfitimingschecker_dfitimingschecker33 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker32 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker33 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv178 & (ddrphy_dfitimingschecker_last_cmd5 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker34 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 5);
- end
- if (ddrphy_dfitimingschecker_cmd_recv178) begin
- ddrphy_dfitimingschecker_dfitimingschecker34 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv179) begin
- ddrphy_dfitimingschecker_dfitimingschecker35 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd5 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv180 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv180) begin
- ddrphy_dfitimingschecker_dfitimingschecker36 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv181 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv181) begin
- ddrphy_dfitimingschecker_dfitimingschecker37 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker36 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker37 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker41 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv182) begin
- ddrphy_dfitimingschecker_dfitimingschecker38 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed60 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv182 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed61 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv182) begin
- sync_t_array_muxed30 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next30)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed30;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed30;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed30;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed30;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next30;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv183 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv183) begin
- ddrphy_dfitimingschecker_dfitimingschecker39 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker38 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker39 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv184 & (ddrphy_dfitimingschecker_last_cmd6 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker40 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 6);
- end
- if (ddrphy_dfitimingschecker_cmd_recv184) begin
- ddrphy_dfitimingschecker_dfitimingschecker40 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv185) begin
- ddrphy_dfitimingschecker_dfitimingschecker41 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd6 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd35000)))) begin
- $display("[%016dps] ACT->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv186 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd21250)))) begin
- $display("[%016dps] WR->PRE violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv186) begin
- ddrphy_dfitimingschecker_dfitimingschecker42 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv187 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->REF violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv187) begin
- ddrphy_dfitimingschecker_dfitimingschecker43 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd2)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker42 + 14'd13750)))) begin
- $display("[%016dps] PRE->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 1'd1)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker43 + 19'd320000)))) begin
- $display("[%016dps] REF->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 16'd48750)))) begin
- $display("[%016dps] ACT->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd6)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker47 + 18'd160000)))) begin
- $display("[%016dps] ZQCS->ACT violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv188) begin
- ddrphy_dfitimingschecker_dfitimingschecker44 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed62 + 14'd10000)))) begin
- $display("[%016dps] tRRD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if ((ddrphy_dfitimingschecker_cmd_recv188 & (ddrphy_dfitimingschecker_ps3 < (sync_basiclowerer_array_muxed63 + 16'd40000)))) begin
- $display("[%016dps] tFAW violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv188) begin
- sync_t_array_muxed31 = ddrphy_dfitimingschecker_ps3;
- case (ddrphy_dfitimingschecker_act_next31)
- 1'd0: begin
- ddrphy_dfitimingschecker0 <= sync_t_array_muxed31;
- end
- 1'd1: begin
- ddrphy_dfitimingschecker1 <= sync_t_array_muxed31;
- end
- 2'd2: begin
- ddrphy_dfitimingschecker2 <= sync_t_array_muxed31;
- end
- default: begin
- ddrphy_dfitimingschecker3 <= sync_t_array_muxed31;
- end
- endcase
- ddrphy_dfitimingschecker_act_curr <= ddrphy_dfitimingschecker_act_next31;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv189 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 15'd17500)))) begin
- $display("[%016dps] WR->RD violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv189) begin
- ddrphy_dfitimingschecker_dfitimingschecker45 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
- end
- if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 2'd3)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker44 + 14'd13750)))) begin
- $display("[%016dps] ACT->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd5)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker45 + 14'd10000)))) begin
- $display("[%016dps] RD->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (((ddrphy_dfitimingschecker_cmd_recv190 & (ddrphy_dfitimingschecker_last_cmd7 == 3'd4)) & (ddrphy_dfitimingschecker_ps3 < (ddrphy_dfitimingschecker_dfitimingschecker46 + 14'd10000)))) begin
- $display("[%016dps] WR->WR violation on bank %0d", ddrphy_dfitimingschecker_ps3, 7);
- end
- if (ddrphy_dfitimingschecker_cmd_recv190) begin
- ddrphy_dfitimingschecker_dfitimingschecker46 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
- end
- if (ddrphy_dfitimingschecker_cmd_recv191) begin
- ddrphy_dfitimingschecker_dfitimingschecker47 <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_last_cmd7 <= ddrphy_dfitimingschecker_state3;
- end
- if ((ddrphy_dfitimingschecker_ref_ps_mod < 36'd64000000000)) begin
- ddrphy_dfitimingschecker_ref_ps_mod <= (ddrphy_dfitimingschecker_ref_ps_mod + 14'd10000);
- end else begin
- ddrphy_dfitimingschecker_ref_ps_mod <= 1'd0;
- end
- if ((ddrphy_dfitimingschecker_ref_issued != 1'd0)) begin
- ddrphy_dfitimingschecker_ref_ps <= ddrphy_dfitimingschecker_ps3;
- ddrphy_dfitimingschecker_ref_ps_diff <= (ddrphy_dfitimingschecker_ref_ps_diff - ddrphy_dfitimingschecker_curr_diff);
- end
- if (($signed({1'd0, (ddrphy_dfitimingschecker_ref_ps_mod == 1'd0)}) & (ddrphy_dfitimingschecker_ref_ps_diff > $signed({1'd0, 1'd0})))) begin
- $display("[%016dps] tREFI violation (64ms period): %0d", ddrphy_dfitimingschecker_ps3, ddrphy_dfitimingschecker_ref_ps_diff);
- end
- if ((ddrphy_dfitimingschecker_ref_issued != 1'd0)) begin
- ddrphy_dfitimingschecker_ref_done <= 1'd1;
- end
- if ((((ddrphy_dfitimingschecker_ref_issued == 1'd0) & ddrphy_dfitimingschecker_ref_done) & (ddrphy_dfitimingschecker_ref_ps > (ddrphy_dfitimingschecker_ps3 + 27'd70312500)))) begin
- $display("[%016dps] tREFI violation (too many postponed refreshes)", ddrphy_dfitimingschecker_ps3);
- ddrphy_dfitimingschecker_ref_done <= 1'd0;
- end
+ array_muxed18 = 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed18 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed18 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed18 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed18 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed19 = 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed19 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed19 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed19 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed19 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed20 = 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed20 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed20 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed20 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed20 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed21 = 3'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed21 = litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed21 = litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed21 = litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed21 = litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed22 = 14'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed22 = litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed22 = litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed22 = litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed22 = litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed23 = 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed23 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed23 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed23 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed23 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed24 = 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed24 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed24 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed24 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed24 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed25 = 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed25 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed25 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed25 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed25 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed26 = 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed26 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed26 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed26 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed26 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed27 = 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed27 = 1'd0;
+ end
+ 1'd1: begin
+ array_muxed27 = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed27 = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed27 = ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+
+always @(posedge por_clk) begin
+ int_rst <= 1'd0;
+end
+
+always @(posedge sys_clk) begin
+ state <= next_state;
+ ddrphy_new_bank_write0 <= ddrphy_bank_write0;
+ ddrphy_new_bank_write_col0 <= ddrphy_bank_write_col0;
+ ddrphy_new_bank_write1 <= ddrphy_new_bank_write0;
+ ddrphy_new_bank_write_col1 <= ddrphy_new_bank_write_col0;
+ ddrphy_new_bank_write2 <= ddrphy_bank_write1;
+ ddrphy_new_bank_write_col2 <= ddrphy_bank_write_col1;
+ ddrphy_new_bank_write3 <= ddrphy_new_bank_write2;
+ ddrphy_new_bank_write_col3 <= ddrphy_new_bank_write_col2;
+ ddrphy_new_bank_write4 <= ddrphy_bank_write2;
+ ddrphy_new_bank_write_col4 <= ddrphy_bank_write_col2;
+ ddrphy_new_bank_write5 <= ddrphy_new_bank_write4;
+ ddrphy_new_bank_write_col5 <= ddrphy_new_bank_write_col4;
+ ddrphy_new_bank_write6 <= ddrphy_bank_write3;
+ ddrphy_new_bank_write_col6 <= ddrphy_bank_write_col3;
+ ddrphy_new_bank_write7 <= ddrphy_new_bank_write6;
+ ddrphy_new_bank_write_col7 <= ddrphy_new_bank_write_col6;
+ ddrphy_new_bank_write8 <= ddrphy_bank_write4;
+ ddrphy_new_bank_write_col8 <= ddrphy_bank_write_col4;
+ ddrphy_new_bank_write9 <= ddrphy_new_bank_write8;
+ ddrphy_new_bank_write_col9 <= ddrphy_new_bank_write_col8;
+ ddrphy_new_bank_write10 <= ddrphy_bank_write5;
+ ddrphy_new_bank_write_col10 <= ddrphy_bank_write_col5;
+ ddrphy_new_bank_write11 <= ddrphy_new_bank_write10;
+ ddrphy_new_bank_write_col11 <= ddrphy_new_bank_write_col10;
+ ddrphy_new_bank_write12 <= ddrphy_bank_write6;
+ ddrphy_new_bank_write_col12 <= ddrphy_bank_write_col6;
+ ddrphy_new_bank_write13 <= ddrphy_new_bank_write12;
+ ddrphy_new_bank_write_col13 <= ddrphy_new_bank_write_col12;
+ ddrphy_new_bank_write14 <= ddrphy_bank_write7;
+ ddrphy_new_bank_write_col14 <= ddrphy_bank_write_col7;
+ ddrphy_new_bank_write15 <= ddrphy_new_bank_write14;
+ ddrphy_new_bank_write_col15 <= ddrphy_new_bank_write_col14;
+ ddrphy_new_banks_read0 <= ddrphy_banks_read;
+ ddrphy_new_banks_read_data0 <= ddrphy_banks_read_data;
+ ddrphy_new_banks_read1 <= ddrphy_new_banks_read0;
+ ddrphy_new_banks_read_data1 <= ddrphy_new_banks_read_data0;
+ ddrphy_new_banks_read2 <= ddrphy_new_banks_read1;
+ ddrphy_new_banks_read_data2 <= ddrphy_new_banks_read_data1;
+ ddrphy_new_banks_read3 <= ddrphy_new_banks_read2;
+ ddrphy_new_banks_read_data3 <= ddrphy_new_banks_read_data2;
+ ddrphy_new_banks_read4 <= ddrphy_new_banks_read3;
+ ddrphy_new_banks_read_data4 <= ddrphy_new_banks_read_data3;
+ ddrphy_new_banks_read5 <= ddrphy_new_banks_read4;
+ ddrphy_new_banks_read_data5 <= ddrphy_new_banks_read_data4;
+ ddrphy_new_banks_read6 <= ddrphy_new_banks_read5;
+ ddrphy_new_banks_read_data6 <= ddrphy_new_banks_read_data5;
+ ddrphy_new_banks_read7 <= ddrphy_new_banks_read6;
+ ddrphy_new_banks_read_data7 <= ddrphy_new_banks_read_data6;
+ ddrphy_new_banks_read8 <= ddrphy_new_banks_read7;
+ ddrphy_new_banks_read_data8 <= ddrphy_new_banks_read_data7;
if (ddrphy_bankmodel0_precharge) begin
ddrphy_bankmodel0_active <= 1'd0;
end else begin
endcase
end
litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= sync_rhs_array_muxed0;
- litedramcore_dfi_p0_address <= sync_rhs_array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~sync_rhs_array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~sync_rhs_array_muxed3);
- litedramcore_dfi_p0_we_n <= (~sync_rhs_array_muxed4);
- litedramcore_dfi_p0_rddata_en <= sync_rhs_array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= sync_rhs_array_muxed6;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= sync_rhs_array_muxed7;
- litedramcore_dfi_p1_address <= sync_rhs_array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~sync_rhs_array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~sync_rhs_array_muxed10);
- litedramcore_dfi_p1_we_n <= (~sync_rhs_array_muxed11);
- litedramcore_dfi_p1_rddata_en <= sync_rhs_array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= sync_rhs_array_muxed13;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= sync_rhs_array_muxed14;
- litedramcore_dfi_p2_address <= sync_rhs_array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~sync_rhs_array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~sync_rhs_array_muxed17);
- litedramcore_dfi_p2_we_n <= (~sync_rhs_array_muxed18);
- litedramcore_dfi_p2_rddata_en <= sync_rhs_array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= sync_rhs_array_muxed20;
+ litedramcore_dfi_p2_bank <= array_muxed14;
+ litedramcore_dfi_p2_address <= array_muxed15;
+ litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+ litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+ litedramcore_dfi_p2_we_n <= (~array_muxed18);
+ litedramcore_dfi_p2_rddata_en <= array_muxed19;
+ litedramcore_dfi_p2_wrdata_en <= array_muxed20;
litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= sync_rhs_array_muxed21;
- litedramcore_dfi_p3_address <= sync_rhs_array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~sync_rhs_array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~sync_rhs_array_muxed24);
- litedramcore_dfi_p3_we_n <= (~sync_rhs_array_muxed25);
- litedramcore_dfi_p3_rddata_en <= sync_rhs_array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= sync_rhs_array_muxed27;
+ litedramcore_dfi_p3_bank <= array_muxed21;
+ litedramcore_dfi_p3_address <= array_muxed22;
+ litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+ litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+ litedramcore_dfi_p3_we_n <= (~array_muxed25);
+ litedramcore_dfi_p3_rddata_en <= array_muxed26;
+ litedramcore_dfi_p3_wrdata_en <= array_muxed27;
if (litedramcore_trrdcon_valid) begin
litedramcore_trrdcon_count <= 1'd1;
if (1'd0) begin
new_master_rdata_valid9 <= new_master_rdata_valid8;
interface0_bank_bus_dat_r <= 1'd0;
if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[1])
+ case (interface0_bank_bus_adr[0])
1'd0: begin
interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
end
init_error_re <= csrbank0_init_error0_re;
interface1_bank_bus_dat_r <= 1'd0;
if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[5:1])
+ case (interface1_bank_bus_adr[5:0])
1'd0: begin
interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
end
interface1_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
end
2'd3: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address1_w;
end
3'd4: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
end
3'd5: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
end
3'd6: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata3_w;
end
3'd7: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata2_w;
end
4'd8: begin
- interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata1_w;
end
4'd9: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
end
4'd10: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata3_w;
end
4'd11: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata2_w;
end
4'd12: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata1_w;
end
4'd13: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata0_w;
end
4'd14: begin
- interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
end
4'd15: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
+ interface1_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
end
5'd16: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address1_w;
end
5'd17: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
end
5'd18: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
end
5'd19: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata3_w;
end
5'd20: begin
- interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata2_w;
end
5'd21: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata1_w;
end
5'd22: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
end
5'd23: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata3_w;
end
5'd24: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata2_w;
+ end
+ 5'd25: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata1_w;
+ end
+ 5'd26: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata0_w;
+ end
+ 5'd27: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
+ end
+ 5'd28: begin
+ interface1_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ end
+ 5'd29: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address1_w;
+ end
+ 5'd30: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
+ end
+ 5'd31: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
+ end
+ 6'd32: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata3_w;
+ end
+ 6'd33: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata2_w;
+ end
+ 6'd34: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata1_w;
+ end
+ 6'd35: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
+ end
+ 6'd36: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata3_w;
+ end
+ 6'd37: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata2_w;
+ end
+ 6'd38: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata1_w;
+ end
+ 6'd39: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata0_w;
+ end
+ 6'd40: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
+ end
+ 6'd41: begin
+ interface1_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ end
+ 6'd42: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address1_w;
+ end
+ 6'd43: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
+ end
+ 6'd44: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
+ end
+ 6'd45: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata3_w;
+ end
+ 6'd46: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata2_w;
+ end
+ 6'd47: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata1_w;
+ end
+ 6'd48: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
+ end
+ 6'd49: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata3_w;
+ end
+ 6'd50: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata2_w;
+ end
+ 6'd51: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata1_w;
+ end
+ 6'd52: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata0_w;
end
endcase
end
litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
end
litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
+ if (csrbank1_dfii_pi0_address1_re) begin
+ litedramcore_phaseinjector0_address_storage[13:8] <= csrbank1_dfii_pi0_address1_r;
+ end
if (csrbank1_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
+ litedramcore_phaseinjector0_address_storage[7:0] <= csrbank1_dfii_pi0_address0_r;
end
litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
if (csrbank1_dfii_pi0_baddress0_re) begin
litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
end
litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
+ if (csrbank1_dfii_pi0_wrdata3_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank1_dfii_pi0_wrdata3_r;
+ end
+ if (csrbank1_dfii_pi0_wrdata2_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank1_dfii_pi0_wrdata2_r;
+ end
+ if (csrbank1_dfii_pi0_wrdata1_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank1_dfii_pi0_wrdata1_r;
+ end
if (csrbank1_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
+ litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank1_dfii_pi0_wrdata0_r;
end
litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
if (csrbank1_dfii_pi1_command0_re) begin
litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
end
litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
+ if (csrbank1_dfii_pi1_address1_re) begin
+ litedramcore_phaseinjector1_address_storage[13:8] <= csrbank1_dfii_pi1_address1_r;
+ end
if (csrbank1_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
+ litedramcore_phaseinjector1_address_storage[7:0] <= csrbank1_dfii_pi1_address0_r;
end
litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
if (csrbank1_dfii_pi1_baddress0_re) begin
litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
end
litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
+ if (csrbank1_dfii_pi1_wrdata3_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank1_dfii_pi1_wrdata3_r;
+ end
+ if (csrbank1_dfii_pi1_wrdata2_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank1_dfii_pi1_wrdata2_r;
+ end
+ if (csrbank1_dfii_pi1_wrdata1_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank1_dfii_pi1_wrdata1_r;
+ end
if (csrbank1_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
+ litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank1_dfii_pi1_wrdata0_r;
end
litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
if (csrbank1_dfii_pi2_command0_re) begin
litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
end
litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
+ if (csrbank1_dfii_pi2_address1_re) begin
+ litedramcore_phaseinjector2_address_storage[13:8] <= csrbank1_dfii_pi2_address1_r;
+ end
if (csrbank1_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
+ litedramcore_phaseinjector2_address_storage[7:0] <= csrbank1_dfii_pi2_address0_r;
end
litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
if (csrbank1_dfii_pi2_baddress0_re) begin
litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
end
litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
+ if (csrbank1_dfii_pi2_wrdata3_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank1_dfii_pi2_wrdata3_r;
+ end
+ if (csrbank1_dfii_pi2_wrdata2_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank1_dfii_pi2_wrdata2_r;
+ end
+ if (csrbank1_dfii_pi2_wrdata1_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank1_dfii_pi2_wrdata1_r;
+ end
if (csrbank1_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
+ litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank1_dfii_pi2_wrdata0_r;
end
litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
if (csrbank1_dfii_pi3_command0_re) begin
litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
end
litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
+ if (csrbank1_dfii_pi3_address1_re) begin
+ litedramcore_phaseinjector3_address_storage[13:8] <= csrbank1_dfii_pi3_address1_r;
+ end
if (csrbank1_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
+ litedramcore_phaseinjector3_address_storage[7:0] <= csrbank1_dfii_pi3_address0_r;
end
litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
if (csrbank1_dfii_pi3_baddress0_re) begin
litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
end
litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
+ if (csrbank1_dfii_pi3_wrdata3_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank1_dfii_pi3_wrdata3_r;
+ end
+ if (csrbank1_dfii_pi3_wrdata2_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank1_dfii_pi3_wrdata2_r;
+ end
+ if (csrbank1_dfii_pi3_wrdata1_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank1_dfii_pi3_wrdata1_r;
+ end
if (csrbank1_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
+ litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank1_dfii_pi3_wrdata0_r;
end
litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
if (sys_rst) begin
- ddrphy_dfitimingschecker_cnt <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker0 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker1 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker2 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker3 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker4 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker5 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker6 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker7 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker8 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker9 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker10 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker11 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker12 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker13 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker14 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker15 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker16 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker17 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker18 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker19 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker20 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker21 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker22 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker23 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker24 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker25 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker26 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker27 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker28 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker29 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker30 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker31 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker32 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker33 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker34 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker35 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker36 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker37 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker38 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker39 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker40 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker41 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker42 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker43 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker44 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker45 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker46 <= 64'd0;
- ddrphy_dfitimingschecker_dfitimingschecker47 <= 64'd0;
- ddrphy_dfitimingschecker_last_cmd0 <= 4'd0;
- ddrphy_dfitimingschecker_last_cmd1 <= 4'd0;
- ddrphy_dfitimingschecker_last_cmd2 <= 4'd0;
- ddrphy_dfitimingschecker_last_cmd3 <= 4'd0;
- ddrphy_dfitimingschecker_last_cmd4 <= 4'd0;
- ddrphy_dfitimingschecker_last_cmd5 <= 4'd0;
- ddrphy_dfitimingschecker_last_cmd6 <= 4'd0;
- ddrphy_dfitimingschecker_last_cmd7 <= 4'd0;
- ddrphy_dfitimingschecker0 <= 64'd0;
- ddrphy_dfitimingschecker1 <= 64'd0;
- ddrphy_dfitimingschecker2 <= 64'd0;
- ddrphy_dfitimingschecker3 <= 64'd0;
- ddrphy_dfitimingschecker_act_curr <= 2'd0;
- ddrphy_dfitimingschecker_ref_ps <= 64'd0;
- ddrphy_dfitimingschecker_ref_ps_mod <= 64'd0;
- ddrphy_dfitimingschecker_ref_ps_diff <= 64'd0;
- ddrphy_dfitimingschecker_ref_done <= 1'd0;
ddrphy_bankmodel0_active <= 1'd0;
ddrphy_bankmodel0_row <= 14'd0;
ddrphy_bankmodel1_active <= 1'd0;
projects / microwatt.git / commitdiff