#include "arch/alpha/arguments.hh"
#include "arch/alpha/vtophys.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/vport.hh"
using namespace AlphaISA;
{
if (number < 6) {
if (fp)
- return xc->readFloatRegBits(16 + number);
+ return tc->readFloatRegBits(16 + number);
else
- return xc->readIntReg(16 + number);
+ return tc->readIntReg(16 + number);
} else {
- Addr sp = xc->readIntReg(30);
- VirtualPort *vp = xc->getVirtPort(xc);
+ Addr sp = tc->readIntReg(30);
+ VirtualPort *vp = tc->getVirtPort(tc);
uint64_t arg = vp->read<uint64_t>(sp + (number-6) * sizeof(uint64_t));
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
return arg;
}
}
#include "base/refcnt.hh"
#include "sim/host.hh"
-class ExecContext;
+class ThreadContext;
namespace AlphaISA {
class AlphaArguments
{
protected:
- ExecContext *xc;
+ ThreadContext *tc;
int number;
uint64_t getArg(bool fp = false);
RefCountingPtr<Data> data;
public:
- AlphaArguments(ExecContext *ctx, int n = 0)
- : xc(ctx), number(n), data(NULL)
+ AlphaArguments(ThreadContext *ctx, int n = 0)
+ : tc(ctx), number(n), data(NULL)
{ assert(number >= 0); data = new Data;}
AlphaArguments(const AlphaArguments &args)
- : xc(args.xc), number(args.number), data(args.data) {}
+ : tc(args.tc), number(args.number), data(args.data) {}
~AlphaArguments() {}
- ExecContext *getExecContext() const { return xc; }
+ ThreadContext *getThreadContext() const { return tc; }
const AlphaArguments &operator=(const AlphaArguments &args) {
- xc = args.xc;
+ tc = args.tc;
number = args.number;
data = args.data;
return *this;
}
AlphaArguments operator[](int index) {
- return AlphaArguments(xc, index);
+ return AlphaArguments(tc, index);
}
template <class T>
template <class T>
operator T *() {
T *buf = (T *)data->alloc(sizeof(T));
- CopyData(xc, buf, getArg(), sizeof(T));
+ CopyData(tc, buf, getArg(), sizeof(T));
return buf;
}
operator char *() {
char *buf = data->alloc(2048);
- CopyStringOut(xc, buf, getArg(), 2048);
+ CopyStringOut(tc, buf, getArg(), 2048);
return buf;
}
};
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh"
#include "sim/debug.hh"
#include "sim/sim_events.hh"
// Machine dependent functions
//
void
-AlphaISA::initCPU(ExecContext *xc, int cpuId)
+AlphaISA::initCPU(ThreadContext *tc, int cpuId)
{
- initIPRs(xc, cpuId);
+ initIPRs(tc, cpuId);
- xc->setIntReg(16, cpuId);
- xc->setIntReg(0, cpuId);
+ tc->setIntReg(16, cpuId);
+ tc->setIntReg(0, cpuId);
- xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
- xc->setNextPC(xc->readPC() + sizeof(MachInst));
+ tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
+ tc->setNextPC(tc->readPC() + sizeof(MachInst));
}
////////////////////////////////////////////////////////////////////////
//
//
void
-AlphaISA::initIPRs(ExecContext *xc, int cpuId)
+AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
{
for (int i = 0; i < NumInternalProcRegs; ++i) {
- xc->setMiscReg(i, 0);
+ tc->setMiscReg(i, 0);
}
- xc->setMiscReg(IPR_PAL_BASE, PalBase);
- xc->setMiscReg(IPR_MCSR, 0x6);
- xc->setMiscReg(IPR_PALtemp16, cpuId);
+ tc->setMiscReg(IPR_PAL_BASE, PalBase);
+ tc->setMiscReg(IPR_MCSR, 0x6);
+ tc->setMiscReg(IPR_PALtemp16, cpuId);
}
}
AlphaISA::MiscReg
-AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
+AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
{
uint64_t retval = 0; // return value, default 0
case AlphaISA::IPR_CC:
retval |= ipr[idx] & ULL(0xffffffff00000000);
- retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
+ retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
break;
case AlphaISA::IPR_VA:
case AlphaISA::IPR_DTB_PTE:
{
- AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
+ AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
#endif
Fault
-AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
+AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
uint64_t old;
- if (xc->misspeculating())
+ if (tc->misspeculating())
return NoFault;
switch (idx) {
// write entire quad w/ no side-effect
old = ipr[idx];
ipr[idx] = val;
- if (xc->getKernelStats())
- xc->getKernelStats()->context(old, val, xc);
+ if (tc->getKernelStats())
+ tc->getKernelStats()->context(old, val, tc);
break;
case AlphaISA::IPR_DTB_PTE:
// only write least significant five bits - interrupt level
ipr[idx] = val & 0x1f;
- if (xc->getKernelStats())
- xc->getKernelStats()->swpipl(ipr[idx]);
+ if (tc->getKernelStats())
+ tc->getKernelStats()->swpipl(ipr[idx]);
break;
case AlphaISA::IPR_DTB_CM:
if (val & 0x18) {
- if (xc->getKernelStats())
- xc->getKernelStats()->mode(Kernel::user, xc);
+ if (tc->getKernelStats())
+ tc->getKernelStats()->mode(Kernel::user, tc);
} else {
- if (xc->getKernelStats())
- xc->getKernelStats()->mode(Kernel::kernel, xc);
+ if (tc->getKernelStats())
+ tc->getKernelStats()->mode(Kernel::kernel, tc);
}
case AlphaISA::IPR_ICM:
// really a control write
ipr[idx] = 0;
- xc->getDTBPtr()->flushAll();
+ tc->getDTBPtr()->flushAll();
break;
case AlphaISA::IPR_DTB_IAP:
// really a control write
ipr[idx] = 0;
- xc->getDTBPtr()->flushProcesses();
+ tc->getDTBPtr()->flushProcesses();
break;
case AlphaISA::IPR_DTB_IS:
// really a control write
ipr[idx] = val;
- xc->getDTBPtr()->flushAddr(val,
+ tc->getDTBPtr()->flushAddr(val,
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
break;
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
// insert new TAG/PTE value into data TLB
- xc->getDTBPtr()->insert(val, pte);
+ tc->getDTBPtr()->insert(val, pte);
}
break;
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
// insert new TAG/PTE value into data TLB
- xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
+ tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
}
break;
// really a control write
ipr[idx] = 0;
- xc->getITBPtr()->flushAll();
+ tc->getITBPtr()->flushAll();
break;
case AlphaISA::IPR_ITB_IAP:
// really a control write
ipr[idx] = 0;
- xc->getITBPtr()->flushProcesses();
+ tc->getITBPtr()->flushProcesses();
break;
case AlphaISA::IPR_ITB_IS:
// really a control write
ipr[idx] = val;
- xc->getITBPtr()->flushAddr(val,
+ tc->getITBPtr()->flushAddr(val,
ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
break;
}
void
-AlphaISA::copyIprs(ExecContext *src, ExecContext *dest)
+AlphaISA::copyIprs(ThreadContext *src, ThreadContext *dest)
{
for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) {
dest->setMiscReg(i, src->readMiscReg(i));
CPUExecContext::simPalCheck(int palFunc)
{
if (kernelStats)
- kernelStats->callpal(palFunc, proxy);
+ kernelStats->callpal(palFunc, tc);
switch (palFunc) {
case PAL::halt:
*/
#include "arch/alpha/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
#if FULL_SYSTEM
#if FULL_SYSTEM
-void AlphaFault::invoke(ExecContext * xc)
+void AlphaFault::invoke(ThreadContext * tc)
{
- FaultBase::invoke(xc);
+ FaultBase::invoke(tc);
countStat()++;
// exception restart address
- if (setRestartAddress() || !xc->inPalMode())
- xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->readPC());
+ if (setRestartAddress() || !tc->inPalMode())
+ tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->readPC());
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
- xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
- xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+ tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
+ tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
- xc->setPC(xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
- xc->setNextPC(xc->readPC() + sizeof(MachInst));
+ tc->setPC(tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect());
+ tc->setNextPC(tc->readPC() + sizeof(MachInst));
}
-void ArithmeticFault::invoke(ExecContext * xc)
+void ArithmeticFault::invoke(ThreadContext * tc)
{
- FaultBase::invoke(xc);
+ FaultBase::invoke(tc);
panic("Arithmetic traps are unimplemented!");
}
-void DtbFault::invoke(ExecContext * xc)
+void DtbFault::invoke(ThreadContext * tc)
{
// Set fault address and flags. Even though we're modeling an
// EV5, we use the EV6 technique of not latching fault registers
// on VPTE loads (instead of locking the registers until IPR_VA is
// read, like the EV5). The EV6 approach is cleaner and seems to
// work with EV5 PAL code, but not the other way around.
- if (!xc->misspeculating()
+ if (!tc->misspeculating()
&& !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) {
// set VA register with faulting address
- xc->setMiscReg(AlphaISA::IPR_VA, vaddr);
+ tc->setMiscReg(AlphaISA::IPR_VA, vaddr);
// set MM_STAT register flags
- xc->setMiscReg(AlphaISA::IPR_MM_STAT,
- (((EV5::Opcode(xc->getInst()) & 0x3f) << 11)
- | ((EV5::Ra(xc->getInst()) & 0x1f) << 6)
+ tc->setMiscReg(AlphaISA::IPR_MM_STAT,
+ (((EV5::Opcode(tc->getInst()) & 0x3f) << 11)
+ | ((EV5::Ra(tc->getInst()) & 0x1f) << 6)
| (flags & 0x3f)));
// set VA_FORM register with faulting formatted address
- xc->setMiscReg(AlphaISA::IPR_VA_FORM,
- xc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
+ tc->setMiscReg(AlphaISA::IPR_VA_FORM,
+ tc->readMiscReg(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3));
}
- AlphaFault::invoke(xc);
+ AlphaFault::invoke(tc);
}
-void ItbFault::invoke(ExecContext * xc)
+void ItbFault::invoke(ThreadContext * tc)
{
- if (!xc->misspeculating()) {
- xc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
- xc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
- xc->readMiscReg(AlphaISA::IPR_IVPTBR) |
+ if (!tc->misspeculating()) {
+ tc->setMiscReg(AlphaISA::IPR_ITB_TAG, pc);
+ tc->setMiscReg(AlphaISA::IPR_IFAULT_VA_FORM,
+ tc->readMiscReg(AlphaISA::IPR_IVPTBR) |
(AlphaISA::VAddr(pc).vpn() << 3));
}
- AlphaFault::invoke(xc);
+ AlphaFault::invoke(tc);
}
#endif
virtual bool setRestartAddress() {return true;}
public:
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
};
FaultVect vect() = 0;
FaultStat & countStat() = 0;
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
};
FaultVect vect() = 0;
FaultStat & countStat() = 0;
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
};
#include "arch/alpha/system.hh"
#include "arch/alpha/freebsd/system.hh"
#include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "arch/isa_traits.hh"
void
-FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc)
+FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc)
{
Addr ppc_vaddr = 0;
Addr timer_vaddr = 0;
- ppc_vaddr = (Addr)xc->readIntReg(ArgumentReg1);
- timer_vaddr = (Addr)xc->readIntReg(ArgumentReg2);
+ ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1);
+ timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2);
virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency);
virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
void
-FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc)
+FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc)
{
- SkipFuncEvent::process(xc);
- ((FreebsdAlphaSystem *)xc->getSystemPtr())->doCalibrateClocks(xc);
+ SkipFuncEvent::process(tc);
+ ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
}
SkipCalibrateClocksEvent(PCEventQueue *q, const std::string &desc,
Addr addr)
: SkipFuncEvent(q, desc, addr) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
SkipFuncEvent *skipDelayEvent;
public:
FreebsdAlphaSystem(Params *p);
~FreebsdAlphaSystem();
- void doCalibrateClocks(ExecContext *xc);
+ void doCalibrateClocks(ThreadContext *tc);
};
{
}
- Addr branchTarget(ExecContext *xc) const;
+ Addr branchTarget(ThreadContext *tc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
}
Addr
- Jump::branchTarget(ExecContext *xc) const
+ Jump::branchTarget(ThreadContext *tc) const
{
- Addr NPC = xc->readPC() + 4;
- uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+ Addr NPC = tc->readPC() + 4;
+ uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
return (Rb & ~3) | (NPC & 1);
}
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
- AlphaPseudo::arm(xc->xcBase());
+ AlphaPseudo::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- AlphaPseudo::quiesce(xc->xcBase());
+ AlphaPseudo::quiesce(xc->tcBase());
}}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
- AlphaPseudo::quiesceNs(xc->xcBase(), R16);
+ AlphaPseudo::quiesceNs(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce);
0x03: quiesceCycles({{
- AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
+ AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
}}, IsNonSpeculative, IsQuiesce);
0x04: quiesceTime({{
- R0 = AlphaPseudo::quiesceTime(xc->xcBase());
+ R0 = AlphaPseudo::quiesceTime(xc->tcBase());
}}, IsNonSpeculative);
0x10: ivlb({{
- AlphaPseudo::ivlb(xc->xcBase());
+ AlphaPseudo::ivlb(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x11: ivle({{
- AlphaPseudo::ivle(xc->xcBase());
+ AlphaPseudo::ivle(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x20: m5exit_old({{
- AlphaPseudo::m5exit_old(xc->xcBase());
+ AlphaPseudo::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
- AlphaPseudo::m5exit(xc->xcBase(), R16);
+ AlphaPseudo::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
- 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
+ 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
0x40: resetstats({{
- AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
+ AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
- AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
+ AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
- AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
+ AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
- AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
+ AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
- R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
+ R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
- AlphaPseudo::debugbreak(xc->xcBase());
+ AlphaPseudo::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
- AlphaPseudo::switchcpu(xc->xcBase());
+ AlphaPseudo::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
- AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
+ AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
#include "config/ss_compatible_fp.hh"
-#include "cpu/exec_context.hh" // for Jump::branchTarget()
+#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include <math.h>
#include "arch/alpha/isa_traits.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
#include "sim/process.hh"
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+ TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "alpha");
- name.copyOut(xc->getMemPort());
+ name.copyOut(tc->getMemPort());
return 0;
}
/// different in practice from those used by Tru64 processes.
static SyscallReturn
osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
- // unsigned nbytes = xc->getSyscallArg(2);
+ unsigned op = tc->getSyscallArg(0);
+ // unsigned nbytes = tc->getSyscallArg(2);
switch (op) {
case 45: { // GSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
- fpcr.copyOut(xc->getMemPort());
+ fpcr.copyOut(tc->getMemPort());
return 0;
}
/// Target osf_setsysinfo() handler.
static SyscallReturn
osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
- // unsigned nbytes = xc->getSyscallArg(2);
+ unsigned op = tc->getSyscallArg(0);
+ // unsigned nbytes = tc->getSyscallArg(2);
switch (op) {
case 14: { // SSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
- fpcr.copyIn(xc->getMemPort());
+ fpcr.copyIn(tc->getMemPort());
DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
#include "arch/alpha/linux/threadinfo.hh"
#include "arch/alpha/system.hh"
#include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "dev/platform.hh"
#include "kern/linux/printk.hh"
void
-LinuxAlphaSystem::setDelayLoop(ExecContext *xc)
+LinuxAlphaSystem::setDelayLoop(ThreadContext *tc)
{
Addr addr = 0;
if (kernelSymtab->findAddress("loops_per_jiffy", addr)) {
- Tick cpuFreq = xc->getCpuPtr()->frequency();
+ Tick cpuFreq = tc->getCpuPtr()->frequency();
Tick intrFreq = platform->intrFrequency();
- xc->getVirtPort(xc)->write(addr,
+ tc->getVirtPort(tc)->write(addr,
(uint32_t)((cpuFreq / intrFreq) * 0.9988));
}
}
void
-LinuxAlphaSystem::SkipDelayLoopEvent::process(ExecContext *xc)
+LinuxAlphaSystem::SkipDelayLoopEvent::process(ThreadContext *tc)
{
- SkipFuncEvent::process(xc);
+ SkipFuncEvent::process(tc);
// calculate and set loops_per_jiffy
- ((LinuxAlphaSystem *)xc->getSystemPtr())->setDelayLoop(xc);
+ ((LinuxAlphaSystem *)tc->getSystemPtr())->setDelayLoop(tc);
}
void
-LinuxAlphaSystem::PrintThreadInfo::process(ExecContext *xc)
+LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc)
{
- Linux::ThreadInfo ti(xc);
+ Linux::ThreadInfo ti(tc);
DPRINTF(Thread, "Currently Executing Thread %s, pid %d, started at: %d\n",
ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
#ifndef __ARCH_ALPHA_LINUX_SYSTEM_HH__
#define __ARCH_ALPHA_LINUX_SYSTEM_HH__
-class ExecContext;
+class ThreadContext;
class BreakPCEvent;
class IdleStartEvent;
public:
SkipDelayLoopEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: SkipFuncEvent(q, desc, addr) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
class PrintThreadInfo : public PCEvent
public:
PrintThreadInfo(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
LinuxAlphaSystem(Params *p);
~LinuxAlphaSystem();
- void setDelayLoop(ExecContext *xc);
+ void setDelayLoop(ThreadContext *tc);
};
#endif // __ARCH_ALPHA_LINUX_SYSTEM_HH__
#define __ARCH_ALPHA_LINUX_LINUX_TREADNIFO_HH__
#include "arch/alpha/linux/thread_info.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/sched.hh"
#include "sim/vptr.hh"
class ThreadInfo
{
private:
- ExecContext *xc;
+ ThreadContext *tc;
public:
- ThreadInfo(ExecContext *exec) : xc(exec) {}
+ ThreadInfo(ThreadContext *_tc) : tc(_tc) {}
~ThreadInfo() {}
inline VPtr<thread_info>
* thread_info struct. So we can get the address by masking off
* the lower 14 bits.
*/
- current = xc->readIntReg(TheISA::StackPointerReg) & ~0x3fff;
- return VPtr<thread_info>(xc, current);
+ current = tc->readIntReg(TheISA::StackPointerReg) & ~0x3fff;
+ return VPtr<thread_info>(tc, current);
}
inline VPtr<task_struct>
curTaskInfo()
{
Addr task = curThreadInfo()->task;
- return VPtr<task_struct>(xc, task);
+ return VPtr<task_struct>(tc, task);
}
std::string
#include "arch/alpha/tru64/process.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
{
argsInit(MachineBytes, VMPageSize);
- execContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
+ threadContexts[0]->setIntReg(GlobalPointerReg, objFile->globalPointer());
}
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
namespace AlphaISA
{
MiscReg readReg(int misc_reg);
MiscReg readRegWithEffect(int misc_reg, Fault &fault,
- ExecContext *xc);
+ ThreadContext *tc);
//These functions should be removed once the simplescalar cpu model
//has been replaced.
Fault setReg(int misc_reg, const MiscReg &val);
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
- ExecContext *xc);
+ ThreadContext *tc);
#if FULL_SYSTEM
protected:
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
- InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc);
+ InternalProcReg readIpr(int idx, Fault &fault, ThreadContext *tc);
- Fault setIpr(int idx, InternalProcReg val, ExecContext *xc);
+ Fault setIpr(int idx, InternalProcReg val, ThreadContext *tc);
#endif
friend class RegFile;
};
}
MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ExecContext *xc)
+ Fault &fault, ThreadContext *tc)
{
fault = NoFault;
- return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+ return miscRegFile.readRegWithEffect(miscReg, fault, tc);
}
Fault setMiscReg(int miscReg, const MiscReg &val)
}
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
- ExecContext * xc)
+ ThreadContext * tc)
{
- return miscRegFile.setRegWithEffect(miscReg, val, xc);
+ return miscRegFile.setRegWithEffect(miscReg, val, tc);
}
FloatReg readFloatReg(int floatReg)
}
};
- void copyRegs(ExecContext *src, ExecContext *dest);
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
- void copyMiscRegs(ExecContext *src, ExecContext *dest);
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
#if FULL_SYSTEM
- void copyIprs(ExecContext *src, ExecContext *dest);
+ void copyIprs(ThreadContext *src, ThreadContext *dest);
#endif
} // namespace AlphaISA
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "sim/system.hh"
using namespace std;
using namespace AlphaISA;
-ProcessInfo::ProcessInfo(ExecContext *_xc)
- : xc(_xc)
+ProcessInfo::ProcessInfo(ThreadContext *_tc)
+ : tc(_tc)
{
Addr addr = 0;
- if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
panic("thread info not compiled into kernel\n");
- thread_info_size = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+ thread_info_size = gtoh(tc->getVirtPort()->read<int32_t>(addr));
- if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
panic("thread info not compiled into kernel\n");
- task_struct_size = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+ task_struct_size = gtoh(tc->getVirtPort()->read<int32_t>(addr));
- if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
panic("thread info not compiled into kernel\n");
- task_off = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+ task_off = gtoh(tc->getVirtPort()->read<int32_t>(addr));
- if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
panic("thread info not compiled into kernel\n");
- pid_off = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+ pid_off = gtoh(tc->getVirtPort()->read<int32_t>(addr));
- if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
+ if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
panic("thread info not compiled into kernel\n");
- name_off = gtoh(xc->getVirtPort()->read<int32_t>(addr));
+ name_off = gtoh(tc->getVirtPort()->read<int32_t>(addr));
}
Addr
if (base == ULL(0xfffffc0000000000))
return 0;
- return gtoh(
xc->getVirtPort()->read<Addr>(base + task_off));
+ return gtoh(
tc->getVirtPort()->read<Addr>(base + task_off));
}
int
if (!task)
return -1;
- return gtoh(xc->getVirtPort()->read<uint16_t>(task + pid_off));
+ return gtoh(tc->getVirtPort()->read<uint16_t>(task + pid_off));
}
string
return "console";
char comm[256];
- CopyStringOut(xc, comm, task + name_off, sizeof(comm));
+ CopyStringOut(tc, comm, task + name_off, sizeof(comm));
if (!comm[0])
return "startup";
}
StackTrace::StackTrace()
- : xc(0), stack(64)
+ : tc(0), stack(64)
{
}
-StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst)
- : xc(0), stack(64)
+StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+ : tc(0), stack(64)
{
- trace(_xc, inst);
+ trace(_tc, inst);
}
StackTrace::~StackTrace()
}
void
-StackTrace::trace(ExecContext *_xc, bool is_call)
+StackTrace::trace(ThreadContext *_tc, bool is_call)
{
- xc = _xc;
+ tc = _tc;
- bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+ bool usermode = (tc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
- Addr pc = xc->readNextPC();
- bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
- pc <= xc->getSystemPtr()->kernelEnd;
+ Addr pc = tc->readNextPC();
+ bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+ pc <= tc->getSystemPtr()->kernelEnd;
if (usermode) {
stack.push_back(user);
return;
}
- SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
- Addr ksp = xc->readIntReg(TheISA::StackPointerReg);
+ SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+ Addr ksp = tc->readIntReg(TheISA::StackPointerReg);
Addr bottom = ksp & ~0x3fff;
Addr addr;
panic("could not find address %#x", pc);
stack.push_back(addr);
- pc = xc->readPC();
+ pc = tc->readPC();
}
Addr ra;
return;
}
- bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
- pc <= xc->getSystemPtr()->kernelEnd;
+ bool kernel = tc->getSystemPtr()->kernelStart <= pc &&
+ pc <= tc->getSystemPtr()->kernelEnd;
if (!kernel)
return;
bool
StackTrace::isEntry(Addr addr)
{
- if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp12))
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp12))
return true;
- if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp7))
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp7))
return true;
- if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp11))
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp11))
return true;
- if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp21))
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp21))
return true;
- if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp9))
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp9))
return true;
- if (addr == xc->readMiscReg(AlphaISA::IPR_PALtemp2))
+ if (addr == tc->readMiscReg(AlphaISA::IPR_PALtemp2))
return true;
return false;
for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
MachInst inst;
- CopyOut(xc, (uint8_t *)&inst, pc, sizeof(MachInst));
+ CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
int reg, disp;
if (decodeStack(inst, disp)) {
size += disp;
} else if (decodeSave(inst, reg, disp)) {
if (!ra && reg == ReturnAddressReg) {
- CopyOut(xc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
+ CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
if (!ra) {
// panic("no return address value pc=%#x\n", pc);
return false;
void
StackTrace::dump()
{
- StringWrap name(xc->getCpuPtr()->name());
- SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
+ StringWrap name(tc->getCpuPtr()->name());
+ SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
DPRINTFN("------ Stack ------\n");
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-class ExecContext;
+class ThreadContext;
class StackTrace;
class ProcessInfo
{
private:
- ExecContext *xc;
+ ThreadContext *tc;
int thread_info_size;
int task_struct_size;
int name_off;
public:
- ProcessInfo(ExecContext *_xc);
+ ProcessInfo(ThreadContext *_tc);
Addr task(Addr ksp) const;
int pid(Addr ksp) const;
protected:
typedef TheISA::MachInst MachInst;
private:
- ExecContext *xc;
+ ThreadContext *tc;
std::vector<Addr> stack;
private:
bool decodeSave(MachInst inst, int ®, int &disp);
bool decodeStack(MachInst inst, int &disp);
- void trace(ExecContext *xc, bool is_call);
+ void trace(ThreadContext *tc, bool is_call);
public:
StackTrace();
- StackTrace(ExecContext *xc, StaticInstPtr inst);
+ StackTrace(ThreadContext *tc, StaticInstPtr inst);
~StackTrace();
void clear()
{
- xc = 0;
+ tc = 0;
stack.clear();
}
- bool valid() const { return xc != NULL; }
- bool trace(ExecContext *xc, StaticInstPtr inst);
+ bool valid() const { return tc != NULL; }
+ bool trace(ThreadContext *tc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
};
inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
if (valid())
clear();
- trace(xc, !inst->isReturn());
+ trace(tc, !inst->isReturn());
return true;
}
#include "base/str.hh"
#include "base/trace.hh"
#include "config/alpha_tlaser.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "sim/builder.hh"
using namespace std;
Fault
-AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
+AlphaITB::translate(RequestPtr &req, ThreadContext *tc) const
{
if (AlphaISA::PcPAL(req->getVaddr())) {
// strip off PAL PC marker (lsb is 1)
// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER
- if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
+ if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
// only valid in kernel mode
- if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
+ if (ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM)) !=
AlphaISA::mode_kernel) {
acv++;
return new ItbAcvFault(req->getVaddr());
} else {
// not a physical address: need to look up pte
- int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
+ int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
asn);
// check permissions for this access
if (!(pte->xre &
- (1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
+ (1 << ICM_CM(tc->readMiscReg(AlphaISA::IPR_ICM))))) {
// instruction access fault
acv++;
return new ItbAcvFault(req->getVaddr());
}
Fault
-AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
+AlphaDTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
{
- Addr pc = xc->readPC();
+ Addr pc = tc->readPC();
AlphaISA::mode_type mode =
- (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
+ (AlphaISA::mode_type)DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM));
/**
if (pc & 0x1) {
mode = (req->getFlags() & ALTMODE) ?
(AlphaISA::mode_type)ALT_MODE_AM(
- xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
+ tc->readMiscReg(AlphaISA::IPR_ALT_MODE))
: AlphaISA::mode_kernel;
}
// Check for "superpage" mapping
#if ALPHA_TLASER
- if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
+ if ((MCSR_SP(tc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
// only valid in kernel mode
- if (DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
+ if (DTB_CM_CM(tc->readMiscReg(AlphaISA::IPR_DTB_CM)) !=
AlphaISA::mode_kernel) {
if (write) { write_acv++; } else { read_acv++; }
uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
else
read_accesses++;
- int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
+ int asn = DTB_ASN_ASN(tc->readMiscReg(AlphaISA::IPR_DTB_ASN));
// not a physical address: need to look up pte
AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
#include "mem/request.hh"
#include "sim/sim_object.hh"
-class ExecContext;
+class ThreadContext;
class AlphaTLB : public SimObject
{
AlphaITB(const std::string &name, int size);
virtual void regStats();
- Fault translate(RequestPtr &req, ExecContext *xc) const;
+ Fault translate(RequestPtr &req, ThreadContext *tc) const;
};
class AlphaDTB : public AlphaTLB
AlphaDTB(const std::string &name, int size);
virtual void regStats();
- Fault translate(RequestPtr &req, ExecContext *xc, bool write) const;
+ Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
};
#endif // __ALPHA_MEMORY_HH__
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/tru64/process.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/tru64/tru64.hh"
#include "sim/process.hh"
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- TypedBufferArg<AlphaTru64::utsname> name(xc->getSyscallArg(0));
+ TypedBufferArg<AlphaTru64::utsname> name(tc->getSyscallArg(0));
strcpy(name->sysname, "OSF1");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->version, "732");
strcpy(name->machine, "alpha");
- name.copyOut(xc->getMemPort());
+ name.copyOut(tc->getMemPort());
return 0;
}
/// Target getsysyinfo() handler.
static SyscallReturn
getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
- unsigned nbytes = xc->getSyscallArg(2);
+ unsigned op = tc->getSyscallArg(0);
+ unsigned nbytes = tc->getSyscallArg(2);
switch (op) {
case AlphaTru64::GSI_MAX_CPU: {
- TypedBufferArg<uint32_t> max_cpu(xc->getSyscallArg(1));
+ TypedBufferArg<uint32_t> max_cpu(tc->getSyscallArg(1));
*max_cpu = htog((uint32_t)process->numCpus());
- max_cpu.copyOut(xc->getMemPort());
+ max_cpu.copyOut(tc->getMemPort());
return 1;
}
case AlphaTru64::GSI_CPUS_IN_BOX: {
- TypedBufferArg<uint32_t> cpus_in_box(xc->getSyscallArg(1));
+ TypedBufferArg<uint32_t> cpus_in_box(tc->getSyscallArg(1));
*cpus_in_box = htog((uint32_t)process->numCpus());
- cpus_in_box.copyOut(xc->getMemPort());
+ cpus_in_box.copyOut(tc->getMemPort());
return 1;
}
case AlphaTru64::GSI_PHYSMEM: {
- TypedBufferArg<uint64_t> physmem(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> physmem(tc->getSyscallArg(1));
*physmem = htog((uint64_t)1024 * 1024); // physical memory in KB
- physmem.copyOut(xc->getMemPort());
+ physmem.copyOut(tc->getMemPort());
return 1;
}
case AlphaTru64::GSI_CPU_INFO: {
- TypedBufferArg<AlphaTru64::cpu_info> infop(xc->getSyscallArg(1));
+ TypedBufferArg<AlphaTru64::cpu_info> infop(tc->getSyscallArg(1));
infop->current_cpu = htog(0);
infop->cpus_in_box = htog(process->numCpus());
infop->cpu_ex_binding = htog(0);
infop->mhz = htog(667);
- infop.copyOut(xc->getMemPort());
+ infop.copyOut(tc->getMemPort());
return 1;
}
case AlphaTru64::GSI_PROC_TYPE: {
- TypedBufferArg<uint64_t> proc_type(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> proc_type(tc->getSyscallArg(1));
*proc_type = htog((uint64_t)11);
- proc_type.copyOut(xc->getMemPort());
+ proc_type.copyOut(tc->getMemPort());
return 1;
}
case AlphaTru64::GSI_PLATFORM_NAME: {
- BufferArg bufArg(xc->getSyscallArg(1), nbytes);
+ BufferArg bufArg(tc->getSyscallArg(1), nbytes);
strncpy((char *)bufArg.bufferPtr(),
"COMPAQ Professional Workstation XP1000",
nbytes);
- bufArg.copyOut(xc->getMemPort());
+ bufArg.copyOut(tc->getMemPort());
return 1;
}
case AlphaTru64::GSI_CLK_TCK: {
- TypedBufferArg<uint64_t> clk_hz(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> clk_hz(tc->getSyscallArg(1));
*clk_hz = htog((uint64_t)1024);
- clk_hz.copyOut(xc->getMemPort());
+ clk_hz.copyOut(tc->getMemPort());
return 1;
}
/// Target setsysyinfo() handler.
static SyscallReturn
setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
+ unsigned op = tc->getSyscallArg(0);
switch (op) {
case AlphaTru64::SSI_IEEE_FP_CONTROL:
warn("setsysinfo: ignoring ieee_set_fp_control() arg 0x%x\n",
- xc->getSyscallArg(1));
+ tc->getSyscallArg(1));
break;
default:
/// Target table() handler.
static
SyscallReturn tableFunc(SyscallDesc *desc, int callnum,Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace std;
using namespace TheISA;
- int id = xc->getSyscallArg(0); // table ID
- int index = xc->getSyscallArg(1); // index into table
+ int id = tc->getSyscallArg(0); // table ID
+ int index = tc->getSyscallArg(1); // index into table
// arg 2 is buffer pointer; type depends on table ID
- int nel = xc->getSyscallArg(3); // number of elements
- int lel = xc->getSyscallArg(4); // expected element size
+ int nel = tc->getSyscallArg(3); // number of elements
+ int lel = tc->getSyscallArg(4); // expected element size
switch (id) {
case AlphaTru64::TBL_SYSINFO: {
if (index != 0 || nel != 1 || lel != sizeof(Tru64::tbl_sysinfo))
return -EINVAL;
- TypedBufferArg<Tru64::tbl_sysinfo> elp(xc->getSyscallArg(2));
+ TypedBufferArg<Tru64::tbl_sysinfo> elp(tc->getSyscallArg(2));
const int clk_hz = one_million;
elp->si_user = htog(curTick / (Clock::Frequency / clk_hz));
elp->si_phz = htog(clk_hz);
elp->si_boottime = htog(seconds_since_epoch); // seconds since epoch?
elp->si_max_procs = htog(process->numCpus());
- elp.copyOut(xc->getMemPort());
+ elp.copyOut(tc->getMemPort());
return 0;
}
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/tru64/tru64_events.hh"
#include "kern/system_events.hh"
#include "mem/physical.hh"
#include "arch/isa_traits.hh"
#include "sim/system.hh"
-class ExecContext;
+class ThreadContext;
class BreakPCEvent;
class BadAddrEvent;
/**
* Function to insure ISA semantics about 0 registers.
- * @param xc The execution context.
+ * @param tc The thread context.
*/
- template <class XC>
- void zeroRegisters(XC *xc);
+ template <class TC>
+ void zeroRegisters(TC *tc);
#if FULL_SYSTEM
// Alpha IPR register accessors
RoundPage(Addr addr)
{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
- void initCPU(ExecContext *xc, int cpuId);
- void initIPRs(ExecContext *xc, int cpuId);
+ void initCPU(ThreadContext *tc, int cpuId);
+ void initIPRs(ThreadContext *tc, int cpuId);
/**
* Function to check for and process any interrupts.
- * @param xc The execution context.
+ * @param tc The thread context.
*/
- template <class XC>
- void processInterrupts(XC *xc);
+ template <class TC>
+ void processInterrupts(TC *tc);
#endif
} // namespace AlphaISA
#include "arch/alpha/vtophys.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/vport.hh"
using namespace std;
}
Addr
-AlphaISA::vtophys(ExecContext *xc, Addr addr)
+AlphaISA::vtophys(ThreadContext *tc, Addr addr)
{
AlphaISA::VAddr vaddr = addr;
- Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
+ Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging?
paddr = vaddr;
} else {
AlphaISA::PageTableEntry pte =
- kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr);
+ kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
if (pte.valid())
paddr = pte.paddr() | vaddr.offset();
}
void
-AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
+AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
{
uint8_t *dst = (uint8_t *)dest;
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
vp->readBlob(src, dst, cplen);
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
}
void
-AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
+AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
{
uint8_t *src = (uint8_t *)source;
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
vp->writeBlob(dest, src, cplen);
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
}
void
-AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
+AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
{
int len = 0;
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
do {
vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
len++;
} while (len < maxlen && dst[len] != 0 );
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
dst[len] = 0;
}
void
-AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr)
+AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
{
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
gen.next())
{
vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
src += gen.size();
}
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
}
#include "arch/alpha/isa_traits.hh"
-class ExecContext;
+class ThreadContext;
class FunctionalPort;
namespace AlphaISA {
kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, AlphaISA::VAddr vaddr);
Addr vtophys(Addr vaddr);
-Addr vtophys(ExecContext *xc, Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
-void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
-void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
-void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ExecContext *xc, char *src, Addr vaddr);
+void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
+void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
+void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
};
#endif // __ARCH_ALPHA_VTOPHYS_H__
*/
#include "arch/mips/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
#if FULL_SYSTEM
-void MipsFault::invoke(ExecContext * xc)
+void MipsFault::invoke(ThreadContext * tc)
{
- FaultBase::invoke(xc);
+ FaultBase::invoke(tc);
countStat()++;
// exception restart address
- if (setRestartAddress() || !xc->inPalMode())
- xc->setMiscReg(MipsISA::IPR_EXC_ADDR, xc->readPC());
+ if (setRestartAddress() || !tc->inPalMode())
+ tc->setMiscReg(MipsISA::IPR_EXC_ADDR, tc->readPC());
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
- xc->setMiscReg(MipsISA::IPR_EXC_ADDR,
- xc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
+ tc->setMiscReg(MipsISA::IPR_EXC_ADDR,
+ tc->readMiscReg(MipsISA::IPR_EXC_ADDR) + 4);
}
- xc->setPC(xc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
- xc->setNextPC(xc->readPC() + sizeof(MachInst));
+ tc->setPC(tc->readMiscReg(MipsISA::IPR_PAL_BASE) + vect());
+ tc->setNextPC(tc->readPC() + sizeof(MachInst));
}
-void ArithmeticFault::invoke(ExecContext * xc)
+void ArithmeticFault::invoke(ThreadContext * tc)
{
- FaultBase::invoke(xc);
+ FaultBase::invoke(tc);
panic("Arithmetic traps are unimplemented!");
}
virtual bool setRestartAddress() {return true;}
public:
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
};
void
-MipsISA::copyRegs(ExecContext *src, ExecContext *dest)
+MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
}
void
-MipsISA::MiscRegFile::copyMiscRegs(ExecContext *xc)
+MipsISA::MiscRegFile::copyMiscRegs(ThreadContext *tc)
{
/*fpcr = xc->readMiscReg(MipsISA::Fpcr_DepTag);
uniq = xc->readMiscReg(MipsISA::Uniq_DepTag);
class FastCPU;
class FullCPU;
class Checkpoint;
-class ExecContext;
+class ThreadContext;
namespace LittleEndianGuest {};
/**
* Function to insure ISA semantics about 0 registers.
- * @param xc The execution context.
+ * @param tc The thread context.
*/
- template <class XC>
- void zeroRegisters(XC *xc);
+ template <class TC>
+ void zeroRegisters(TC *tc);
const Addr MaxAddr = (Addr)-1;
- void copyRegs(ExecContext *src, ExecContext *dest);
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
uint64_t fpConvert(double fp_val, ConvertType cvt_type);
double roundFP(double val, int digits);
#include "arch/mips/isa_traits.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
#include "sim/process.hh"
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+ TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "mips");
- name.copyOut(xc->getMemPort());
+ name.copyOut(tc->getMemPort());
return 0;
}
/// different in practice from those used by Tru64 processes.
static SyscallReturn
sys_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
- // unsigned nbytes = xc->getSyscallArg(2);
+ unsigned op = tc->getSyscallArg(0);
+ // unsigned nbytes = tc->getSyscallArg(2);
switch (op) {
case 45: { // GSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
*fpcr = 0;
- fpcr.copyOut(xc->getMemPort());
+ fpcr.copyOut(tc->getMemPort());
return 0;
}
/// Target sys_setsysinfo() handler.
static SyscallReturn
sys_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned op = xc->getSyscallArg(0);
- // unsigned nbytes = xc->getSyscallArg(2);
+ unsigned op = tc->getSyscallArg(0);
+ // unsigned nbytes = tc->getSyscallArg(2);
switch (op) {
case 14: { // SSI_IEEE_FP_CONTROL
- TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
+ TypedBufferArg<uint64_t> fpcr(tc->getSyscallArg(1));
// I don't think this exactly matches the HW FPCR
- fpcr.copyIn(xc->getMemPort());
+ fpcr.copyIn(tc->getMemPort());
DPRINTFR(SyscallVerbose, "sys_setsysinfo(SSI_IEEE_FP_CONTROL): "
" setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
return 0;
#include "arch/mips/linux/process.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
#include "sim/host.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
class Regfile;
namespace MipsISA
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
class Regfile;
namespace MipsISA
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
class Regfile;
namespace MipsISA
int getInstAsid();
int getDataAsid();
- void copyMiscRegs(ExecContext *xc);
+ void copyMiscRegs(ThreadContext *tc);
MiscReg readReg(int misc_reg)
{
return miscRegFile[misc_reg];
}
- MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc)
+ MiscReg readRegWithEffect(int misc_reg, Fault &fault, ThreadContext *tc)
{
return miscRegFile[misc_reg];
}
}
Fault setRegWithEffect(int misc_reg, const MiscReg &val,
- ExecContext *xc)
+ ThreadContext *tc)
{
miscRegFile[misc_reg] = val; return NoFault;
}
InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
private:
- MiscReg readIpr(int idx, Fault &fault, ExecContext *xc) { }
+ MiscReg readIpr(int idx, Fault &fault, ThreadContext *tc) { }
- Fault setIpr(int idx, uint64_t val, ExecContext *xc) { }
+ Fault setIpr(int idx, uint64_t val, ThreadContext *tc) { }
#endif
friend class RegFile;
};
#include "sim/faults.hh"
class Checkpoint;
-class ExecContext;
+class ThreadContext;
namespace MipsISA
{
}
MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ExecContext *xc)
+ Fault &fault, ThreadContext *tc)
{
fault = NoFault;
- return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+ return miscRegFile.readRegWithEffect(miscReg, fault, tc);
}
Fault setMiscReg(int miscReg, const MiscReg &val)
}
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
- ExecContext * xc)
+ ThreadContext * tc)
{
- return miscRegFile.setRegWithEffect(miscReg, val, xc);
+ return miscRegFile.setRegWithEffect(miscReg, val, tc);
}
FloatReg readFloatReg(int floatReg)
}
};
- void copyRegs(ExecContext *src, ExecContext *dest);
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
- void copyMiscRegs(ExecContext *src, ExecContext *dest);
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
#if FULL_SYSTEM
- void copyIprs(ExecContext *src, ExecContext *dest);
+ void copyIprs(ThreadContext *src, ThreadContext *dest);
#endif
} // namespace MipsISA
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-class ExecContext;
+class ThreadContext;
class StackTrace;
class ProcessInfo
{
private:
- ExecContext *xc;
+ ThreadContext *tc;
int thread_info_size;
int task_struct_size;
int name_off;
public:
- ProcessInfo(ExecContext *_xc);
+ ProcessInfo(ThreadContext *_tc);
Addr task(Addr ksp) const;
int pid(Addr ksp) const;
protected:
typedef TheISA::MachInst MachInst;
private:
- ExecContext *xc;
+ ThreadContext *tc;
std::vector<Addr> stack;
private:
bool decodeSave(MachInst inst, int ®, int &disp);
bool decodeStack(MachInst inst, int &disp);
- void trace(ExecContext *xc, bool is_call);
+ void trace(ThreadContext *tc, bool is_call);
public:
StackTrace();
- StackTrace(ExecContext *xc, StaticInstPtr inst);
+ StackTrace(ThreadContext *tc, StaticInstPtr inst);
~StackTrace();
void clear()
{
- xc = 0;
+ tc = 0;
stack.clear();
}
- bool valid() const { return xc != NULL; }
- bool trace(ExecContext *xc, StaticInstPtr inst);
+ bool valid() const { return tc != NULL; }
+ bool trace(ThreadContext *tc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
};
inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
if (valid())
clear();
- trace(xc, !inst->isReturn());
+ trace(tc, !inst->isReturn());
return true;
}
*/
#include "arch/sparc/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "base/trace.hh"
#if FULL_SYSTEM
-void SparcFault::invoke(ExecContext * xc)
+void SparcFault::invoke(ThreadContext * tc)
{
- FaultBase::invoke(xc);
+ FaultBase::invoke(tc);
countStat()++;
//Use the SPARC trap state machine
/*// exception restart address
- if (setRestartAddress() || !xc->inPalMode())
- xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, xc->regs.pc);
+ if (setRestartAddress() || !tc->inPalMode())
+ tc->setMiscReg(AlphaISA::IPR_EXC_ADDR, tc->regs.pc);
if (skipFaultingInstruction()) {
// traps... skip faulting instruction.
- xc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
- xc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
+ tc->setMiscReg(AlphaISA::IPR_EXC_ADDR,
+ tc->readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
}
- if (!xc->inPalMode())
- AlphaISA::swap_palshadow(&(xc->regs), true);
+ if (!tc->inPalMode())
+ AlphaISA::swap_palshadow(&(tc->regs), true);
- xc->regs.pc = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
- xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
+ tc->regs.pc = tc->readMiscReg(AlphaISA::IPR_PAL_BASE) + vect();
+ tc->regs.npc = tc->regs.pc + sizeof(MachInst);*/
}
#endif
#if !FULL_SYSTEM
-void TrapInstruction::invoke(ExecContext * xc)
+void TrapInstruction::invoke(ThreadContext * tc)
{
- xc->syscall(syscall_num);
+ tc->syscall(syscall_num);
}
#endif
{
public:
#if FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
virtual TrapType trapType() = 0;
virtual FaultPriority priority() = 0;
FaultPriority priority() {return _priority;}
FaultStat & countStat() {return _count;}
#if !FULL_SYSTEM
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
#endif
};
#include "config/full_system.hh"
#include "sim/host.hh"
-class ExecContext;
+class ThreadContext;
class FastCPU;
//class FullCPU;
class Checkpoint;
#include "arch/sparc/regfile.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/linux.hh"
#include "sim/process.hh"
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- TypedBufferArg<Linux::utsname> name(xc->getSyscallArg(0));
+ TypedBufferArg<Linux::utsname> name(tc->getSyscallArg(0));
strcpy(name->sysname, "Linux");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "sparc");
- name.copyOut(xc->getMemPort());
+ name.copyOut(tc->getMemPort());
return 0;
}
SyscallReturn SparcISA::getresuidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc)
+ Process *p, ThreadContext *tc)
{
const IntReg id = htog(100);
- Addr ruid = xc->getSyscallArg(0);
- Addr euid = xc->getSyscallArg(1);
- Addr suid = xc->getSyscallArg(2);
+ Addr ruid = tc->getSyscallArg(0);
+ Addr euid = tc->getSyscallArg(1);
+ Addr suid = tc->getSyscallArg(2);
//Handle the EFAULT case
//Set the ruid
if(ruid)
{
BufferArg ruidBuff(ruid, sizeof(IntReg));
memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg));
- ruidBuff.copyOut(xc->getMemPort());
+ ruidBuff.copyOut(tc->getMemPort());
}
//Set the euid
if(euid)
{
BufferArg euidBuff(euid, sizeof(IntReg));
memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg));
- euidBuff.copyOut(xc->getMemPort());
+ euidBuff.copyOut(tc->getMemPort());
}
//Set the suid
if(suid)
{
BufferArg suidBuff(suid, sizeof(IntReg));
memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg));
- suidBuff.copyOut(xc->getMemPort());
+ suidBuff.copyOut(tc->getMemPort());
}
return 0;
}
};
SyscallReturn getresuidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
} // namespace SparcISA
#endif // __ALPHA_LINUX_PROCESS_HH__
#include "arch/sparc/solaris/process.hh"
#include "base/loader/object_file.hh"
#include "base/misc.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
#include "sim/builder.hh"
//From the SPARC ABI
//The process runs in user mode
- execContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
+ threadContexts[0]->setMiscRegWithEffect(MISCREG_PSTATE, 0x02);
//Setup default FP state
- execContexts[0]->setMiscReg(MISCREG_FSR, 0);
+ threadContexts[0]->setMiscReg(MISCREG_FSR, 0);
- execContexts[0]->setMiscReg(MISCREG_TICK, 0);
+ threadContexts[0]->setMiscReg(MISCREG_TICK, 0);
//
/*
* Register window management registers
*/
//No windows contain info from other programs
- execContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
+ threadContexts[0]->setMiscRegWithEffect(MISCREG_OTHERWIN, 0);
//There are no windows to pop
- execContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
+ threadContexts[0]->setMiscRegWithEffect(MISCREG_CANRESTORE, 0);
//All windows are available to save into
- execContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
+ threadContexts[0]->setMiscRegWithEffect(MISCREG_CANSAVE, NWindows - 2);
//All windows are "clean"
- execContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
+ threadContexts[0]->setMiscRegWithEffect(MISCREG_CLEANWIN, NWindows);
//Start with register window 0
- execContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
+ threadContexts[0]->setMiscRegWithEffect(MISCREG_CWP, 0);
}
m5_auxv_t buildAuxVect(int64_t type, int64_t val)
initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
- execContexts[0]->setIntReg(ArgumentReg0, argc);
- execContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
- execContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
+ threadContexts[0]->setIntReg(ArgumentReg0, argc);
+ threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+ threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
Addr prog_entry = objFile->entryPoint();
- execContexts[0]->setPC(prog_entry);
- execContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
- execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
+ threadContexts[0]->setPC(prog_entry);
+ threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
+ threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
// num_processes++;
}
#if FULL_SYSTEM
/** Process a tick compare event and generate an interrupt on the cpu if
* appropriate. */
- void processTickCompare(ExecContext *xc);
- void processSTickCompare(ExecContext *xc);
- void processHSTickCompare(ExecContext *xc);
+ void processTickCompare(ThreadContext *tc);
+ void processSTickCompare(ThreadContext *tc);
+ void processHSTickCompare(ThreadContext *tc);
typedef CpuEventWrapper<MiscRegFile,
&MiscRegFile::processTickCompare> TickCompareEvent;
HSTickCompareEvent *hSTickCompare;
/** Fullsystem only register version of ReadRegWithEffect() */
- MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
+ MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
/** Fullsystem only register version of SetRegWithEffect() */
Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
- ExecContext * xc);
+ ThreadContext * tc);
#endif
public:
* are are readFSRegWithEffect (which is called by readRegWithEffect()).
* Checking is done for permission based on state bits in the miscreg
* file. */
- MiscReg readRegWithEffect(int miscReg, Fault &fault, ExecContext *xc);
+ MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
/** write a value into an either an SE or FS IPR. No checking is done
* about SE vs. FS as this is mostly used to copy the regfile. Thus more
* Checking is done for permission based on state bits in the miscreg
* file. */
Fault setRegWithEffect(int miscReg,
- const MiscReg &val, ExecContext * xc);
+ const MiscReg &val, ThreadContext * tc);
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, const std::string & section);
- void copyMiscRegs(ExecContext * xc);
+ void copyMiscRegs(ThreadContext * tc);
bool isHyperPriv() { return hpstateFields.hpriv; }
bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
}
MiscReg readMiscRegWithEffect(int miscReg,
- Fault &fault, ExecContext *xc)
+ Fault &fault, ThreadContext *tc)
{
- return miscRegFile.readRegWithEffect(miscReg, fault, xc);
+ return miscRegFile.readRegWithEffect(miscReg, fault, tc);
}
Fault setMiscReg(int miscReg, const MiscReg &val)
}
Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
- ExecContext * xc)
+ ThreadContext * tc)
{
- return miscRegFile.setRegWithEffect(miscReg, val, xc);
+ return miscRegFile.setRegWithEffect(miscReg, val, tc);
}
FloatReg readFloatReg(int floatReg, int width)
}
};
- void copyRegs(ExecContext *src, ExecContext *dest);
+ void copyRegs(ThreadContext *src, ThreadContext *dest);
- void copyMiscRegs(ExecContext *src, ExecContext *dest);
+ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
int InterruptLevel(uint64_t softint);
#include "arch/sparc/regfile.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/solaris/solaris.hh"
#include "sim/process.hh"
/// Target uname() handler.
static SyscallReturn
unameFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- TypedBufferArg<Solaris::utsname> name(xc->getSyscallArg(0));
+ TypedBufferArg<Solaris::utsname> name(tc->getSyscallArg(0));
strcpy(name->sysname, "SunOS");
strcpy(name->nodename, "m5.eecs.umich.edu");
strcpy(name->version, "Generic_118558-21");
strcpy(name->machine, "sun4u");
- name.copyOut(xc->getMemPort());
+ name.copyOut(tc->getMemPort());
return 0;
}
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-class ExecContext;
+class ThreadContext;
class StackTrace;
class ProcessInfo
{
private:
- ExecContext *xc;
+ ThreadContext *tc;
int thread_info_size;
int task_struct_size;
int name_off;
public:
- ProcessInfo(ExecContext *_xc);
+ ProcessInfo(ThreadContext *_tc);
Addr task(Addr ksp) const;
int pid(Addr ksp) const;
protected:
typedef TheISA::MachInst MachInst;
private:
- ExecContext *xc;
+ ThreadContext *tc;
std::vector<Addr> stack;
private:
bool decodeSave(MachInst inst, int ®, int &disp);
bool decodeStack(MachInst inst, int &disp);
- void trace(ExecContext *xc, bool is_call);
+ void trace(ThreadContext *tc, bool is_call);
public:
StackTrace();
- StackTrace(ExecContext *xc, StaticInstPtr inst);
+ StackTrace(ThreadContext *tc, StaticInstPtr inst);
~StackTrace();
void clear()
{
- xc = 0;
+ tc = 0;
stack.clear();
}
- bool valid() const { return xc != NULL; }
- bool trace(ExecContext *xc, StaticInstPtr inst);
+ bool valid() const { return tc != NULL; }
+ bool trace(ThreadContext *tc, StaticInstPtr inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
};
inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
if (valid())
clear();
- trace(xc, !inst->isReturn());
+ trace(tc, !inst->isReturn());
return true;
}
Fault
SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
- ExecContext *xc)
+ ThreadContext *tc)
{
int64_t time;
SparcSystem *sys;
setReg(miscReg, val);
if (newLevel > oldLevel)
; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
- //xc->getCpuPtr()->checkInterrupts = true;
+ //tc->getCpuPtr()->checkInterrupts = true;
return NoFault;
case MISCREG_SOFTINT_CLR:
- return setRegWithEffect(miscReg, ~val & softint, xc);
+ return setRegWithEffect(miscReg, ~val & softint, tc);
case MISCREG_SOFTINT_SET:
- return setRegWithEffect(miscReg, val | softint, xc);
+ return setRegWithEffect(miscReg, val | softint, tc);
case MISCREG_TICK_CMPR:
if (isNonPriv())
return new PrivilegedOpcode;
if (tickCompare == NULL)
- tickCompare = new TickCompareEvent(this, xc);
+ tickCompare = new TickCompareEvent(this, tc);
setReg(miscReg, val);
if (tick_cmprFields.int_dis && tickCompare.scheduled())
tickCompare.deschedule();
time = tick_cmprFields.tick_cmpr - tickFields.counter;
if (!tick_cmprFields.int_dis && time > 0)
- tickCompare.schedule(time * xc->getCpuPtr()->cycles(1));
+ tickCompare.schedule(time * tc->getCpuPtr()->cycles(1));
return NoFault;
case MISCREG_STICK:
return new PrivilegedOpcode;
if (isPriv())
return new PrivilegedAction;
- sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
stickFields.npt = val & Bit64 ? 1 : 0;
if (isNonPriv())
return new PrivilegedOpcode;
if (sTickCompare == NULL)
- sTickCompare = new STickCompareEvent(this, xc);
- sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+ sTickCompare = new STickCompareEvent(this, tc);
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
setReg(miscReg, val);
if (stick_cmprFields.int_dis && sTickCompare.scheduled())
case MISCREG_PIL:
if (FULL_SYSTEM) {
setReg(miscReg, val);
- //xc->getCpuPtr()->checkInterrupts;
+ //tc->getCpuPtr()->checkInterrupts;
// MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
return NoFault;
} else
if (isNonPriv())
return new PrivilegedOpcode;
if (hSTickCompare == NULL)
- hSTickCompare = new HSTickCompareEvent(this, xc);
- sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+ hSTickCompare = new HSTickCompareEvent(this, tc);
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
setReg(miscReg, val);
if (hstick_cmprFields.int_dis && hSTickCompare.scheduled())
}
MiscReg
-MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc)
+MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext * tc)
{
switch (miscReg) {
fault = new PrivilegedAction;
return 0;
}
- sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr());
+ sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
assert(sys != NULL);
return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63;
case MISCREG_STICK_CMPR:
}
void
-MiscRegFile::processTickCompare(ExecContext *xc)
+MiscRegFile::processTickCompare(ThreadContext *tc)
{
panic("tick compare not implemented\n");
}
void
-MiscRegFile::processSTickCompare(ExecContext *xc)
+MiscRegFile::processSTickCompare(ThreadContext *tc)
{
panic("tick compare not implemented\n");
}
void
-MiscRegFile::processHSTickCompare(ExecContext *xc)
+MiscRegFile::processHSTickCompare(ThreadContext *tc)
{
panic("tick compare not implemented\n");
}
/**
* Function to insure ISA semantics about 0 registers.
- * @param xc The execution context.
+ * @param tc The thread context.
*/
- template <class XC>
- void zeroRegisters(XC *xc);
+ template <class TC>
+ void zeroRegisters(TC *tc);
} // namespace SparcISA
#include "arch/alpha/vtophys.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/vport.hh"
using namespace std;
}
Addr
-AlphaISA::vtophys(ExecContext *xc, Addr addr)
+AlphaISA::vtophys(ThreadContext *tc, Addr addr)
{
AlphaISA::VAddr vaddr = addr;
- Addr ptbr = xc->readMiscReg(AlphaISA::IPR_PALtemp20);
+ Addr ptbr = tc->readMiscReg(AlphaISA::IPR_PALtemp20);
Addr paddr = 0;
//@todo Andrew couldn't remember why he commented some of this code
//so I put it back in. Perhaps something to do with gdb debugging?
paddr = vaddr;
} else {
AlphaISA::PageTableEntry pte =
- kernel_pte_lookup(xc->getPhysPort(), ptbr, vaddr);
+ kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr);
if (pte.valid())
paddr = pte.paddr() | vaddr.offset();
}
void
-AlphaISA::CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
+AlphaISA::CopyOut(ThreadContext *tc, void *dest, Addr src, size_t cplen)
{
uint8_t *dst = (uint8_t *)dest;
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
vp->readBlob(src, dst, cplen);
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
}
void
-AlphaISA::CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
+AlphaISA::CopyIn(ThreadContext *tc, Addr dest, void *source, size_t cplen)
{
uint8_t *src = (uint8_t *)source;
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
vp->writeBlob(dest, src, cplen);
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
}
void
-AlphaISA::CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
+AlphaISA::CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen)
{
int len = 0;
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
do {
vp->readBlob(vaddr++, (uint8_t*)dst++, 1);
len++;
} while (len < maxlen && dst[len] != 0 );
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
dst[len] = 0;
}
void
-AlphaISA::CopyStringIn(ExecContext *xc, char *src, Addr vaddr)
+AlphaISA::CopyStringIn(ThreadContext *tc, char *src, Addr vaddr)
{
- VirtualPort *vp = xc->getVirtPort(xc);
+ VirtualPort *vp = tc->getVirtPort(tc);
for (ChunkGenerator gen(vaddr, strlen(src), AlphaISA::PageBytes); !gen.done();
gen.next())
{
vp->writeBlob(gen.addr(), (uint8_t*)src, gen.size());
src += gen.size();
}
- xc->delVirtPort(vp);
+ tc->delVirtPort(vp);
}
#include "arch/sparc/isa_traits.hh"
-class ExecContext;
+class ThreadContext;
class FunctionalPort;
namespace SparcISA {
kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
Addr vtophys(Addr vaddr);
-Addr vtophys(ExecContext *xc, Addr vaddr);
+Addr vtophys(ThreadContext *tc, Addr vaddr);
-void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
-void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
-void CopyStringOut(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
-void CopyStringIn(ExecContext *xc, char *src, Addr vaddr);
+void CopyOut(ThreadContext *tc, void *dst, Addr src, size_t len);
+void CopyIn(ThreadContext *tc, Addr dst, void *src, size_t len);
+void CopyStringOut(ThreadContext *tc, char *dst, Addr vaddr, size_t maxlen);
+void CopyStringIn(ThreadContext *tc, char *src, Addr vaddr);
};
#endif // __ARCH_SPARC_VTOPHYS_H__
#include "base/socket.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
gdb->detach();
}
-RemoteGDB::RemoteGDB(System *_system, ExecContext *c)
+RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
: event(NULL), listener(NULL), number(-1), fd(-1),
active(false), attached(false),
system(_system), pmem(_system->physmem), context(c)
}
void
-RemoteGDB::HardBreakpoint::process(ExecContext *xc)
+RemoteGDB::HardBreakpoint::process(ThreadContext *tc)
{
DPRINTF(GDBMisc, "handling hardware breakpoint at %#x\n", pc());
- if (xc == gdb->context)
+ if (tc == gdb->context)
gdb->trap(ALPHA_KENTRY_INT);
}
#include "base/socket.hh"
class System;
-class ExecContext;
+class ThreadContext;
class PhysicalMemory;
class GDBListener;
System *system;
PhysicalMemory *pmem;
- ExecContext *context;
+ ThreadContext *context;
protected:
uint8_t getbyte();
template <class T> void write(Addr addr, T data);
public:
- RemoteGDB(System *system, ExecContext *context);
+ RemoteGDB(System *system, ThreadContext *context);
~RemoteGDB();
- void replaceExecContext(ExecContext *xc) { context = xc; }
+ void replaceThreadContext(ThreadContext *tc) { context = tc; }
void attach(int fd);
void detach();
HardBreakpoint(RemoteGDB *_gdb, Addr addr);
std::string name() { return gdb->name() + ".hwbkpt"; }
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
friend class HardBreakpoint;
#include "base/output.hh"
#include "cpu/base.hh"
#include "cpu/cpuevent.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
#include "cpu/sampler/sampler.hh"
#include "sim/param.hh"
BaseCPU::init()
{
if (!params->deferRegistration)
- registerExecContexts();
+ registerThreadContexts();
}
void
.desc("number of cpu cycles simulated")
;
- int size = execContexts.size();
+ int size = threadContexts.size();
if (size > 1) {
for (int i = 0; i < size; ++i) {
stringstream namestr;
ccprintf(namestr, "%s.ctx%d", name(), i);
- execContexts[i]->regStats(namestr.str());
+ threadContexts[i]->regStats(namestr.str());
}
} else if (size == 1)
- execContexts[0]->regStats(name());
+ threadContexts[0]->regStats(name());
#if FULL_SYSTEM
#endif
void
-BaseCPU::registerExecContexts()
+BaseCPU::registerThreadContexts()
{
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
#if FULL_SYSTEM
int id = params->cpu_id;
if (id != -1)
id += i;
- xc->setCpuId(system->registerExecContext(xc, id));
+ tc->setCpuId(system->registerThreadContext(tc, id));
#else
- xc->setCpuId(xc->getProcessPtr()->registerExecContext(xc));
+ tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc));
#endif
}
}
void
BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
- assert(execContexts.size() == oldCPU->execContexts.size());
+ assert(threadContexts.size() == oldCPU->threadContexts.size());
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *newXC = execContexts[i];
- ExecContext *oldXC = oldCPU->execContexts[i];
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *newTC = threadContexts[i];
+ ThreadContext *oldTC = oldCPU->threadContexts[i];
- newXC->takeOverFrom(oldXC);
+ newTC->takeOverFrom(oldTC);
- CpuEvent::replaceExecContext(oldXC, newXC);
+ CpuEvent::replaceThreadContext(oldTC, newTC);
- assert(newXC->readCpuId() == oldXC->readCpuId());
+ assert(newTC->readCpuId() == oldTC->readCpuId());
#if FULL_SYSTEM
- system->replaceExecContext(newXC, newXC->readCpuId());
+ system->replaceThreadContext(newTC, newTC->readCpuId());
#else
- assert(newXC->getProcessPtr() == oldXC->getProcessPtr());
- newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId());
+ assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
+ newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId());
#endif
}
interrupts[i] = oldCPU->interrupts[i];
intstatus = oldCPU->intstatus;
- for (int i = 0; i < execContexts.size(); ++i)
- execContexts[i]->profileClear();
+ for (int i = 0; i < threadContexts.size(); ++i)
+ threadContexts[i]->profileClear();
if (profileEvent)
profileEvent->schedule(curTick);
void
BaseCPU::ProfileEvent::process()
{
- for (int i = 0, size = cpu->execContexts.size(); i < size; ++i) {
- ExecContext *xc = cpu->execContexts[i];
- xc->profileSample();
+ for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) {
+ ThreadContext *tc = cpu->threadContexts[i];
+ tc->profileSample();
}
schedule(curTick + interval);
class BranchPred;
class CheckerCPU;
-class ExecContext;
+class ThreadContext;
class System;
class BaseCPU : public SimObject
#endif
protected:
- std::vector<ExecContext *> execContexts;
+ std::vector<ThreadContext *> threadContexts;
public:
virtual void activateWhenReady(int tid) {};
- void registerExecContexts();
+ void registerThreadContexts();
/// Prepare for another CPU to take over execution. When it is
/// is ready (drained pipe) it signals the sampler.
/** Pointer to the FullCPU object. */
FullCPU *cpu;
- /** Pointer to the exec context. */
+ /** Pointer to the thread state. */
ImplState *thread;
/** The kind of fault this instruction has generated. */
void setState(ImplState *state) { thread = state; }
- /** Returns the exec context.
- * @todo: Remove this once the ExecContext is no longer used.
+ /** Returns the thread context.
*/
- ExecContext *xcBase() { return thread->getXCProxy(); }
+ ThreadContext *tcBase() { return thread->getTC(); }
private:
/** Instruction effective address.
#include "cpu/base_dyn_inst.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
#include "sim/byteswap.hh"
#include "sim/sim_object.hh"
}
CheckerCPU::CheckerCPU(Params *p)
- : BaseCPU(p), cpuXC(NULL), xcProxy(NULL)
+ : BaseCPU(p), cpuXC(NULL), tc(NULL)
{
memReq = NULL;
cpuXC = new CPUExecContext(this, /* thread_num */ 0, process,
/* asid */ 0, mem);
- cpuXC->setStatus(ExecContext::Suspended);
- xcProxy = cpuXC->getProxy();
- execContexts.push_back(xcProxy);
+ cpuXC->setStatus(ThreadContext::Suspended);
+ tc = cpuXC->getTC();
+ threadContexts.push_back(tc);
#else
if (systemPtr) {
cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
- cpuXC->setStatus(ExecContext::Suspended);
- xcProxy = cpuXC->getProxy();
- execContexts.push_back(xcProxy);
- memReq->xc = xcProxy;
+ cpuXC->setStatus(ThreadContext::Suspended);
+ tc = cpuXC->getTC();
+ threadContexts.push_back(tc);
delete cpuXC->kernelStats;
cpuXC->kernelStats = NULL;
}
if (memPtr) {
cpuXC = new CPUExecContext(this, 0, systemPtr, itb, dtb, memPtr, false);
- cpuXC->setStatus(ExecContext::Suspended);
- xcProxy = cpuXC->getProxy();
- execContexts.push_back(xcProxy);
- memReq->xc = xcProxy;
+ cpuXC->setStatus(ThreadContext::Suspended);
+ tc = cpuXC->getTC();
+ threadContexts.push_back(tc);
delete cpuXC->kernelStats;
cpuXC->kernelStats = NULL;
}
int misc_reg_idx = miscRegIdxs.front();
miscRegIdxs.pop();
- if (inst->xcBase()->readMiscReg(misc_reg_idx) !=
+ if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
cpuXC->readMiscReg(misc_reg_idx)) {
warn("%lli: Misc reg idx %i (side effect) does not match! "
"Inst: %#x, checker: %#x",
curTick, misc_reg_idx,
- inst->xcBase()->readMiscReg(misc_reg_idx),
+ inst->tcBase()->readMiscReg(misc_reg_idx),
cpuXC->readMiscReg(misc_reg_idx));
handleError();
}
#endif // FULL_SYSTEM
template <class>
class BaseDynInst;
-class ExecContext;
+class ThreadContext;
class MemInterface;
class Checkpoint;
class Request;
* the values of uncached accesses. In these cases, and with
* instructions marked as "IsUnverifiable", the checker assumes that
* the value from the main CPU's execution is correct and simply
- * copies that value. It provides a CheckerExecContext (see
+ * copies that value. It provides a CheckerThreadContext (see
* checker/exec_context.hh) that provides hooks for updating the
- * Checker's state through any ExecContext accesses. This allows the
+ * Checker's state through any ThreadContext accesses. This allows the
* checker to be able to correctly verify instructions, even with
- * external accesses to the ExecContext that change state.
+ * external accesses to the ThreadContext that change state.
*/
class CheckerCPU : public BaseCPU
{
// execution context
CPUExecContext *cpuXC;
- ExecContext *xcProxy;
+ ThreadContext *tc;
AlphaITB *itb;
AlphaDTB *dtb;
}
bool checkFlags(Request *req);
- ExecContext *xcBase() { return xcProxy; }
+ ThreadContext *tcBase() { return tc; }
CPUExecContext *cpuXCBase() { return cpuXC; }
Result unverifiedResult;
#include "cpu/checker/cpu.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
class EndQuiesceEvent;
namespace Kernel {
};
/**
- * Derived ExecContext class for use with the Checker. The template
- * parameter is the ExecContext class used by the specific CPU being
- * verified. This CheckerExecContext is then used by the main CPU in
- * place of its usual ExecContext class. It handles updating the
- * checker's state any time state is updated through the ExecContext.
+ * Derived ThreadContext class for use with the Checker. The template
+ * parameter is the ThreadContext class used by the specific CPU being
+ * verified. This CheckerThreadContext is then used by the main CPU in
+ * place of its usual ThreadContext class. It handles updating the
+ * checker's state any time state is updated through the ThreadContext.
*/
-template <class XC>
-class CheckerExecContext : public ExecContext
+template <class TC>
+class CheckerThreadContext : public ThreadContext
{
public:
- CheckerExecContext(XC *actual_xc,
+ CheckerThreadContext(TC *actual_tc,
CheckerCPU *checker_cpu)
- : actualXC(actual_xc), checkerXC(checker_cpu->cpuXC),
+ : actualTC(actual_tc), checkerTC(checker_cpu->cpuXC),
checkerCPU(checker_cpu)
{ }
private:
- XC *actualXC;
- CPUExecContext *checkerXC;
+ TC *actualTC;
+ CPUExecContext *checkerTC;
CheckerCPU *checkerCPU;
public:
- BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
+ BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
void setCpuId(int id)
{
- actualXC->setCpuId(id);
- checkerXC->setCpuId(id);
+ actualTC->setCpuId(id);
+ checkerTC->setCpuId(id);
}
- int readCpuId() { return actualXC->readCpuId(); }
+ int readCpuId() { return actualTC->readCpuId(); }
- TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
+ TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
#if FULL_SYSTEM
- System *getSystemPtr() { return actualXC->getSystemPtr(); }
+ System *getSystemPtr() { return actualTC->getSystemPtr(); }
- PhysicalMemory *getPhysMemPtr() { return actualXC->getPhysMemPtr(); }
+ PhysicalMemory *getPhysMemPtr() { return actualTC->getPhysMemPtr(); }
- AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
+ AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
- AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
+ AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
- Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
+ Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
#else
- Process *getProcessPtr() { return actualXC->getProcessPtr(); }
+ Process *getProcessPtr() { return actualTC->getProcessPtr(); }
#endif
- Status status() const { return actualXC->status(); }
+ Status status() const { return actualTC->status(); }
void setStatus(Status new_status)
{
- actualXC->setStatus(new_status);
- checkerXC->setStatus(new_status);
+ actualTC->setStatus(new_status);
+ checkerTC->setStatus(new_status);
}
/// Set the status to Active. Optional delay indicates number of
/// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualXC->activate(delay); }
+ void activate(int delay = 1) { actualTC->activate(delay); }
/// Set the status to Suspended.
- void suspend() { actualXC->suspend(); }
+ void suspend() { actualTC->suspend(); }
/// Set the status to Unallocated.
- void deallocate() { actualXC->deallocate(); }
+ void deallocate() { actualTC->deallocate(); }
/// Set the status to Halted.
- void halt() { actualXC->halt(); }
+ void halt() { actualTC->halt(); }
#if FULL_SYSTEM
- void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
+ void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
#endif
- void takeOverFrom(ExecContext *oldContext)
+ void takeOverFrom(ThreadContext *oldContext)
{
- actualXC->takeOverFrom(oldContext);
- checkerXC->takeOverFrom(oldContext);
+ actualTC->takeOverFrom(oldContext);
+ checkerTC->takeOverFrom(oldContext);
}
- void regStats(const std::string &name) { actualXC->regStats(name); }
+ void regStats(const std::string &name) { actualTC->regStats(name); }
- void serialize(std::ostream &os) { actualXC->serialize(os); }
+ void serialize(std::ostream &os) { actualTC->serialize(os); }
void unserialize(Checkpoint *cp, const std::string §ion)
- { actualXC->unserialize(cp, section); }
+ { actualTC->unserialize(cp, section); }
#if FULL_SYSTEM
- EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
+ EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
- Tick readLastActivate() { return actualXC->readLastActivate(); }
- Tick readLastSuspend() { return actualXC->readLastSuspend(); }
+ Tick readLastActivate() { return actualTC->readLastActivate(); }
+ Tick readLastSuspend() { return actualTC->readLastSuspend(); }
- void profileClear() { return actualXC->profileClear(); }
- void profileSample() { return actualXC->profileSample(); }
+ void profileClear() { return actualTC->profileClear(); }
+ void profileSample() { return actualTC->profileSample(); }
#endif
- int getThreadNum() { return actualXC->getThreadNum(); }
+ int getThreadNum() { return actualTC->getThreadNum(); }
// @todo: Do I need this?
- MachInst getInst() { return actualXC->getInst(); }
+ MachInst getInst() { return actualTC->getInst(); }
// @todo: Do I need this?
- void copyArchRegs(ExecContext *xc)
+ void copyArchRegs(ThreadContext *tc)
{
- actualXC->copyArchRegs(xc);
- checkerXC->copyArchRegs(xc);
+ actualTC->copyArchRegs(tc);
+ checkerTC->copyArchRegs(tc);
}
void clearArchRegs()
{
- actualXC->clearArchRegs();
- checkerXC->clearArchRegs();
+ actualTC->clearArchRegs();
+ checkerTC->clearArchRegs();
}
//
// New accessors for new decoder.
//
uint64_t readIntReg(int reg_idx)
- { return actualXC->readIntReg(reg_idx); }
+ { return actualTC->readIntReg(reg_idx); }
FloatReg readFloatReg(int reg_idx, int width)
- { return actualXC->readFloatReg(reg_idx, width); }
+ { return actualTC->readFloatReg(reg_idx, width); }
FloatReg readFloatReg(int reg_idx)
- { return actualXC->readFloatReg(reg_idx); }
+ { return actualTC->readFloatReg(reg_idx); }
FloatRegBits readFloatRegBits(int reg_idx, int width)
- { return actualXC->readFloatRegBits(reg_idx, width); }
+ { return actualTC->readFloatRegBits(reg_idx, width); }
FloatRegBits readFloatRegBits(int reg_idx)
- { return actualXC->readFloatRegBits(reg_idx); }
+ { return actualTC->readFloatRegBits(reg_idx); }
void setIntReg(int reg_idx, uint64_t val)
{
- actualXC->setIntReg(reg_idx, val);
- checkerXC->setIntReg(reg_idx, val);
+ actualTC->setIntReg(reg_idx, val);
+ checkerTC->setIntReg(reg_idx, val);
}
void setFloatReg(int reg_idx, FloatReg val, int width)
{
- actualXC->setFloatReg(reg_idx, val, width);
- checkerXC->setFloatReg(reg_idx, val, width);
+ actualTC->setFloatReg(reg_idx, val, width);
+ checkerTC->setFloatReg(reg_idx, val, width);
}
void setFloatReg(int reg_idx, FloatReg val)
{
- actualXC->setFloatReg(reg_idx, val);
- checkerXC->setFloatReg(reg_idx, val);
+ actualTC->setFloatReg(reg_idx, val);
+ checkerTC->setFloatReg(reg_idx, val);
}
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
{
- actualXC->setFloatRegBits(reg_idx, val, width);
- checkerXC->setFloatRegBits(reg_idx, val, width);
+ actualTC->setFloatRegBits(reg_idx, val, width);
+ checkerTC->setFloatRegBits(reg_idx, val, width);
}
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
- actualXC->setFloatRegBits(reg_idx, val);
- checkerXC->setFloatRegBits(reg_idx, val);
+ actualTC->setFloatRegBits(reg_idx, val);
+ checkerTC->setFloatRegBits(reg_idx, val);
}
- uint64_t readPC() { return actualXC->readPC(); }
+ uint64_t readPC() { return actualTC->readPC(); }
void setPC(uint64_t val)
{
- actualXC->setPC(val);
- checkerXC->setPC(val);
+ actualTC->setPC(val);
+ checkerTC->setPC(val);
checkerCPU->recordPCChange(val);
}
- uint64_t readNextPC() { return actualXC->readNextPC(); }
+ uint64_t readNextPC() { return actualTC->readNextPC(); }
void setNextPC(uint64_t val)
{
- actualXC->setNextPC(val);
- checkerXC->setNextPC(val);
+ actualTC->setNextPC(val);
+ checkerTC->setNextPC(val);
checkerCPU->recordNextPCChange(val);
}
- uint64_t readNextNPC() { return actualXC->readNextNPC(); }
+ uint64_t readNextNPC() { return actualTC->readNextNPC(); }
void setNextNPC(uint64_t val)
{
- actualXC->setNextNPC(val);
- checkerXC->setNextNPC(val);
+ actualTC->setNextNPC(val);
+ checkerTC->setNextNPC(val);
checkerCPU->recordNextPCChange(val);
}
MiscReg readMiscReg(int misc_reg)
- { return actualXC->readMiscReg(misc_reg); }
+ { return actualTC->readMiscReg(misc_reg); }
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
- { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
+ { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
- checkerXC->setMiscReg(misc_reg, val);
- return actualXC->setMiscReg(misc_reg, val);
+ checkerTC->setMiscReg(misc_reg, val);
+ return actualTC->setMiscReg(misc_reg, val);
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- checkerXC->setMiscRegWithEffect(misc_reg, val);
- return actualXC->setMiscRegWithEffect(misc_reg, val);
+ checkerTC->setMiscRegWithEffect(misc_reg, val);
+ return actualTC->setMiscRegWithEffect(misc_reg, val);
}
unsigned readStCondFailures()
- { return actualXC->readStCondFailures(); }
+ { return actualTC->readStCondFailures(); }
void setStCondFailures(unsigned sc_failures)
{
- checkerXC->setStCondFailures(sc_failures);
- actualXC->setStCondFailures(sc_failures);
+ checkerTC->setStCondFailures(sc_failures);
+ actualTC->setStCondFailures(sc_failures);
}
#if FULL_SYSTEM
- bool inPalMode() { return actualXC->inPalMode(); }
+ bool inPalMode() { return actualTC->inPalMode(); }
#endif
// @todo: Fix this!
- bool misspeculating() { return actualXC->misspeculating(); }
+ bool misspeculating() { return actualTC->misspeculating(); }
#if !FULL_SYSTEM
- IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
+ IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
// used to shift args for indirect syscall
void setSyscallArg(int i, IntReg val)
{
- checkerXC->setSyscallArg(i, val);
- actualXC->setSyscallArg(i, val);
+ checkerTC->setSyscallArg(i, val);
+ actualTC->setSyscallArg(i, val);
}
void setSyscallReturn(SyscallReturn return_value)
{
- checkerXC->setSyscallReturn(return_value);
- actualXC->setSyscallReturn(return_value);
+ checkerTC->setSyscallReturn(return_value);
+ actualTC->setSyscallReturn(return_value);
}
- Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
+ Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
#endif
void changeRegFileContext(RegFile::ContextParam param,
RegFile::ContextVal val)
{
- actualXC->changeRegFileContext(param, val);
- checkerXC->changeRegFileContext(param, val);
+ actualTC->changeRegFileContext(param, val);
+ checkerTC->changeRegFileContext(param, val);
}
};
#include "arch/isa_traits.hh"
#include "cpu/base.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#if FULL_SYSTEM
#include "base/callback.hh"
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num, System *_sys,
AlphaITB *_itb, AlphaDTB *_dtb,
bool use_kernel_stats)
- : _status(ExecContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
+ : _status(ThreadContext::Unallocated), cpu(_cpu), thread_num(_thread_num),
cpu_id(-1), lastActivate(0), lastSuspend(0), system(_sys), itb(_itb),
dtb(_dtb), profile(NULL), func_exe_inst(0), storeCondFailures(0)
{
- proxy = new ProxyExecContext<CPUExecContext>(this);
+ tc = new ProxyThreadContext<CPUExecContext>(this);
- quiesceEvent = new EndQuiesceEvent(proxy);
+ quiesceEvent = new EndQuiesceEvent(tc);
regs.clear();
#else
CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
Process *_process, int _asid, MemObject* memobj)
- : _status(ExecContext::Unallocated),
+ : _status(ThreadContext::Unallocated),
cpu(_cpu), thread_num(_thread_num), cpu_id(-1), lastActivate(0),
lastSuspend(0), process(_process), asid(_asid),
func_exe_inst(0), storeCondFailures(0)
port->setPeer(mem_port);
regs.clear();
- proxy = new ProxyExecContext<CPUExecContext>(this);
+ tc = new ProxyThreadContext<CPUExecContext>(this);
}
CPUExecContext::CPUExecContext(RegFile *regFile)
func_exe_inst(0), storeCondFailures(0)
{
regs = *regFile;
- proxy = new ProxyExecContext<CPUExecContext>(this);
+ tc = new ProxyThreadContext<CPUExecContext>(this);
}
#endif
CPUExecContext::~CPUExecContext()
{
- delete proxy;
+ delete tc;
}
#if FULL_SYSTEM
CPUExecContext::dumpFuncProfile()
{
std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
- profile->dump(proxy, *os);
+ profile->dump(tc, *os);
}
void
#endif
void
-CPUExecContext::takeOverFrom(ExecContext *oldContext)
+CPUExecContext::takeOverFrom(ThreadContext *oldContext)
{
// some things should already be set up
#if FULL_SYSTEM
#else
EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent();
if (quiesce) {
- // Point the quiesce event's XC at this XC so that it wakes up
+ // Point the quiesce event's TC at this TC so that it wakes up
// the proper CPU.
- quiesce->xc = proxy;
+ quiesce->tc = tc;
}
if (quiesceEvent) {
- quiesceEvent->xc = proxy;
+ quiesceEvent->tc = tc;
}
#endif
storeCondFailures = 0;
- oldContext->setStatus(ExecContext::Unallocated);
+ oldContext->setStatus(ThreadContext::Unallocated);
}
void
void
CPUExecContext::activate(int delay)
{
- if (status() == ExecContext::Active)
+ if (status() == ThreadContext::Active)
return;
lastActivate = curTick;
- if (status() == ExecContext::Unallocated) {
+ if (status() == ThreadContext::Unallocated) {
cpu->activateWhenReady(thread_num);
return;
}
- _status = ExecContext::Active;
+ _status = ThreadContext::Active;
// status() == Suspended
cpu->activateContext(thread_num, delay);
void
CPUExecContext::suspend()
{
- if (status() == ExecContext::Suspended)
+ if (status() == ThreadContext::Suspended)
return;
lastActivate = curTick;
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->check_interrupts()) {
- assert(status() == ExecContext::Active);
+ assert(status() == ThreadContext::Active);
return;
}
#endif
*/
- _status = ExecContext::Suspended;
+ _status = ThreadContext::Suspended;
cpu->suspendContext(thread_num);
}
void
CPUExecContext::deallocate()
{
- if (status() == ExecContext::Unallocated)
+ if (status() == ThreadContext::Unallocated)
return;
- _status = ExecContext::Unallocated;
+ _status = ThreadContext::Unallocated;
cpu->deallocateContext(thread_num);
}
void
CPUExecContext::halt()
{
- if (status() == ExecContext::Halted)
+ if (status() == ThreadContext::Halted)
return;
- _status = ExecContext::Halted;
+ _status = ThreadContext::Halted;
cpu->haltContext(thread_num);
}
}
void
-CPUExecContext::copyArchRegs(ExecContext *xc)
+CPUExecContext::copyArchRegs(ThreadContext *src_tc)
{
- TheISA::copyRegs(xc, proxy);
+ TheISA::copyRegs(src_tc, tc);
}
#if FULL_SYSTEM
VirtualPort*
-CPUExecContext::getVirtPort(ExecContext *xc)
+CPUExecContext::getVirtPort(ThreadContext *src_tc)
{
- if (!xc)
+ if (!src_tc)
return virtPort;
VirtualPort *vp;
Port *mem_port;
- vp = new VirtualPort("xc-vport", xc);
+ vp = new VirtualPort("tc-vport", src_tc);
mem_port = system->physmem->getPort("functional");
mem_port->setPeer(vp);
vp->setPeer(mem_port);
void
CPUExecContext::delVirtPort(VirtualPort *vp)
{
-// assert(!vp->nullExecContext());
+// assert(!vp->nullThreadContext());
delete vp->getPeer();
delete vp;
}
#include "arch/isa_traits.hh"
#include "config/full_system.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/physical.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
public:
- typedef ExecContext::Status Status;
+ typedef ThreadContext::Status Status;
private:
Status _status;
// pointer to CPU associated with this context
BaseCPU *cpu;
- ProxyExecContext<CPUExecContext> *proxy;
+ ProxyThreadContext<CPUExecContext> *tc;
// Current instruction
MachInst inst;
#endif
virtual ~CPUExecContext();
- virtual void takeOverFrom(ExecContext *oldContext);
+ virtual void takeOverFrom(ThreadContext *oldContext);
void regStats(const std::string &name);
BaseCPU *getCpuPtr() { return cpu; }
- ExecContext *getProxy() { return proxy; }
+ ThreadContext *getTC() { return tc; }
int getThreadNum() { return thread_num; }
Fault translateInstReq(RequestPtr &req)
{
- return itb->translate(req, proxy);
+ return itb->translate(req, tc);
}
Fault translateDataReadReq(RequestPtr &req)
{
- return dtb->translate(req, proxy, false);
+ return dtb->translate(req, tc, false);
}
Fault translateDataWriteReq(RequestPtr &req)
{
- return dtb->translate(req, proxy, true);
+ return dtb->translate(req, tc, true);
}
FunctionalPort *getPhysPort() { return physPort; }
- /** Return a virtual port. If no exec context is specified then a static
+ /** Return a virtual port. If no thread context is specified then a static
* port is returned. Otherwise a port is created and returned. It must be
* deleted by deleteVirtPort(). */
- VirtualPort *getVirtPort(ExecContext *xc);
+ VirtualPort *getVirtPort(ThreadContext *tc);
void delVirtPort(VirtualPort *vp);
int readCpuId() { return cpu_id; }
- void copyArchRegs(ExecContext *xc);
+ void copyArchRegs(ThreadContext *tc);
//
// New accessors for new decoder.
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
- return regs.readMiscRegWithEffect(misc_reg, fault, proxy);
+ return regs.readMiscRegWithEffect(misc_reg, fault, tc);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- return regs.setMiscRegWithEffect(misc_reg, val, proxy);
+ return regs.setMiscRegWithEffect(misc_reg, val, tc);
}
unsigned readStCondFailures() { return storeCondFailures; }
void syscall(int64_t callnum)
{
- process->syscall(callnum, proxy);
+ process->syscall(callnum, tc);
}
Counter readFuncExeInst() { return func_exe_inst; }
#include "cpu/cpuevent.hh"
-/** Static list of all CpuEvent objects so we can modify their execution
+/** Static list of all CpuEvent objects so we can modify their thread
* contexts as needed. */
CpuEvent::CpuEventList CpuEvent::cpuEventList;
}
void
-CpuEvent::replaceExecContext(ExecContext *oldXc, ExecContext *newXc)
+CpuEvent::replaceThreadContext(ThreadContext *oldTc, ThreadContext *newTc)
{
CpuEventList::iterator i;
- // Update any events that have the old execution context with the new exec
+ // Update any events that have the old thread context with the new thread
// context
for (i = cpuEventList.begin(); i != cpuEventList.end(); i++) {
- if ((*i)->xc == oldXc)
- (*i)->xc = newXc;
+ if ((*i)->tc == oldTc)
+ (*i)->tc = newTc;
}
}
#include <vector>
#include "sim/eventq.hh"
-class ExecContext;
+class ThreadContext;
/** This class creates a global list of events than need a pointer to an
- * execution context. When a switchover takes place the events can be migrated
- * to the new execution context, otherwise you could have a wake timer interrupt
+ * thread context. When a switchover takes place the events can be migrated
+ * to the new thread context, otherwise you could have a wake timer interrupt
* go off on a switched out cpu or other unfortunate events. This object MUST be
* dynamically allocated to avoid it being deleted after a cpu switch happens.
* */
* happens. */
static CpuEventList cpuEventList;
- /** The execution context that is switched to the new cpus. */
- ExecContext *xc;
+ /** The thread context that is switched to the new cpus. */
+ ThreadContext *tc;
public:
- CpuEvent(EventQueue *q, ExecContext *_xc, Priority p = Default_Pri)
- : Event(q, p), xc(_xc)
+ CpuEvent(EventQueue *q, ThreadContext *_tc, Priority p = Default_Pri)
+ : Event(q, p), tc(_tc)
{ cpuEventList.push_back(this); }
/** delete the cpu event from the global list. */
~CpuEvent();
- /** Update all events switching old xc to new xc.
- * @param oldXc the old exeuction context we are switching from
- * @param newXc the new execution context we are switching to.
+ /** Update all events switching old tc to new tc.
+ * @param oldTc the old thread context we are switching from
+ * @param newTc the new thread context we are switching to.
*/
- static void replaceExecContext(ExecContext *oldXc, ExecContext *newXc);
+ static void replaceThreadContext(ThreadContext *oldTc,
+ ThreadContext *newTc);
};
-template <class T, void (T::* F)(ExecContext *xc)>
+template <class T, void (T::* F)(ThreadContext *tc)>
class CpuEventWrapper : public CpuEvent
{
private:
T *object;
public:
- CpuEventWrapper(T *obj, ExecContext *_xc, EventQueue *q = &mainEventQueue,
+ CpuEventWrapper(T *obj, ThreadContext *_tc, EventQueue *q = &mainEventQueue,
Priority p = Default_Pri)
- : CpuEvent(q, _xc, p), object(obj)
+ : CpuEvent(q, _tc, p), object(obj)
{ }
- void process() { (object->*F)(xc); }
+ void process() { (object->*F)(tc); }
};
#endif // __CPU_CPUEVENT_HH__
+++ /dev/null
-/*
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Kevin Lim
- */
-
-#ifndef __CPU_EXEC_CONTEXT_HH__
-#define __CPU_EXEC_CONTEXT_HH__
-
-#include "config/full_system.hh"
-#include "mem/request.hh"
-#include "sim/faults.hh"
-#include "sim/host.hh"
-#include "sim/serialize.hh"
-#include "sim/byteswap.hh"
-
-// @todo: Figure out a more architecture independent way to obtain the ITB and
-// DTB pointers.
-class AlphaDTB;
-class AlphaITB;
-class BaseCPU;
-class EndQuiesceEvent;
-class Event;
-class TranslatingPort;
-class FunctionalPort;
-class VirtualPort;
-class Process;
-class System;
-namespace Kernel {
- class Statistics;
-};
-
-class ExecContext
-{
- protected:
- typedef TheISA::RegFile RegFile;
- typedef TheISA::MachInst MachInst;
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscRegFile MiscRegFile;
- typedef TheISA::MiscReg MiscReg;
- public:
- enum Status
- {
- /// Initialized but not running yet. All CPUs start in
- /// this state, but most transition to Active on cycle 1.
- /// In MP or SMT systems, non-primary contexts will stay
- /// in this state until a thread is assigned to them.
- Unallocated,
-
- /// Running. Instructions should be executed only when
- /// the context is in this state.
- Active,
-
- /// Temporarily inactive. Entered while waiting for
- /// synchronization, etc.
- Suspended,
-
- /// Permanently shut down. Entered when target executes
- /// m5exit pseudo-instruction. When all contexts enter
- /// this state, the simulation will terminate.
- Halted
- };
-
- virtual ~ExecContext() { };
-
- virtual BaseCPU *getCpuPtr() = 0;
-
- virtual void setCpuId(int id) = 0;
-
- virtual int readCpuId() = 0;
-
-#if FULL_SYSTEM
- virtual System *getSystemPtr() = 0;
-
- virtual AlphaITB *getITBPtr() = 0;
-
- virtual AlphaDTB * getDTBPtr() = 0;
-
- virtual Kernel::Statistics *getKernelStats() = 0;
-
- virtual FunctionalPort *getPhysPort() = 0;
-
- virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
-
- virtual void delVirtPort(VirtualPort *vp) = 0;
-#else
- virtual TranslatingPort *getMemPort() = 0;
-
- virtual Process *getProcessPtr() = 0;
-#endif
-
- virtual Status status() const = 0;
-
- virtual void setStatus(Status new_status) = 0;
-
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- virtual void activate(int delay = 1) = 0;
-
- /// Set the status to Suspended.
- virtual void suspend() = 0;
-
- /// Set the status to Unallocated.
- virtual void deallocate() = 0;
-
- /// Set the status to Halted.
- virtual void halt() = 0;
-
-#if FULL_SYSTEM
- virtual void dumpFuncProfile() = 0;
-#endif
-
- virtual void takeOverFrom(ExecContext *old_context) = 0;
-
- virtual void regStats(const std::string &name) = 0;
-
- virtual void serialize(std::ostream &os) = 0;
- virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
-
-#if FULL_SYSTEM
- virtual EndQuiesceEvent *getQuiesceEvent() = 0;
-
- // Not necessarily the best location for these...
- // Having an extra function just to read these is obnoxious
- virtual Tick readLastActivate() = 0;
- virtual Tick readLastSuspend() = 0;
-
- virtual void profileClear() = 0;
- virtual void profileSample() = 0;
-#endif
-
- virtual int getThreadNum() = 0;
-
- // Also somewhat obnoxious. Really only used for the TLB fault.
- // However, may be quite useful in SPARC.
- virtual TheISA::MachInst getInst() = 0;
-
- virtual void copyArchRegs(ExecContext *xc) = 0;
-
- virtual void clearArchRegs() = 0;
-
- //
- // New accessors for new decoder.
- //
- virtual uint64_t readIntReg(int reg_idx) = 0;
-
- virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
-
- virtual FloatReg readFloatReg(int reg_idx) = 0;
-
- virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
-
- virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
-
- virtual void setIntReg(int reg_idx, uint64_t val) = 0;
-
- virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
-
- virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
-
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
-
- virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
-
- virtual uint64_t readPC() = 0;
-
- virtual void setPC(uint64_t val) = 0;
-
- virtual uint64_t readNextPC() = 0;
-
- virtual void setNextPC(uint64_t val) = 0;
-
- virtual uint64_t readNextNPC() = 0;
-
- virtual void setNextNPC(uint64_t val) = 0;
-
- virtual MiscReg readMiscReg(int misc_reg) = 0;
-
- virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
-
- virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
-
- virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
-
- // Also not necessarily the best location for these two. Hopefully will go
- // away once we decide upon where st cond failures goes.
- virtual unsigned readStCondFailures() = 0;
-
- virtual void setStCondFailures(unsigned sc_failures) = 0;
-
-#if FULL_SYSTEM
- virtual bool inPalMode() = 0;
-#endif
-
- // Only really makes sense for old CPU model. Still could be useful though.
- virtual bool misspeculating() = 0;
-
-#if !FULL_SYSTEM
- virtual IntReg getSyscallArg(int i) = 0;
-
- // used to shift args for indirect syscall
- virtual void setSyscallArg(int i, IntReg val) = 0;
-
- virtual void setSyscallReturn(SyscallReturn return_value) = 0;
-
-
- // Same with st cond failures.
- virtual Counter readFuncExeInst() = 0;
-#endif
-
- virtual void changeRegFileContext(RegFile::ContextParam param,
- RegFile::ContextVal val) = 0;
-};
-
-template <class XC>
-class ProxyExecContext : public ExecContext
-{
- public:
- ProxyExecContext(XC *actual_xc)
- { actualXC = actual_xc; }
-
- private:
- XC *actualXC;
-
- public:
-
- BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
-
- void setCpuId(int id) { actualXC->setCpuId(id); }
-
- int readCpuId() { return actualXC->readCpuId(); }
-
-#if FULL_SYSTEM
- System *getSystemPtr() { return actualXC->getSystemPtr(); }
-
- AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
-
- AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
-
- Kernel::Statistics *getKernelStats() { return actualXC->getKernelStats(); }
-
- FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
-
- VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
-
- void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); }
-#else
- TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
-
- Process *getProcessPtr() { return actualXC->getProcessPtr(); }
-#endif
-
- Status status() const { return actualXC->status(); }
-
- void setStatus(Status new_status) { actualXC->setStatus(new_status); }
-
- /// Set the status to Active. Optional delay indicates number of
- /// cycles to wait before beginning execution.
- void activate(int delay = 1) { actualXC->activate(delay); }
-
- /// Set the status to Suspended.
- void suspend() { actualXC->suspend(); }
-
- /// Set the status to Unallocated.
- void deallocate() { actualXC->deallocate(); }
-
- /// Set the status to Halted.
- void halt() { actualXC->halt(); }
-
-#if FULL_SYSTEM
- void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
-#endif
-
- void takeOverFrom(ExecContext *oldContext)
- { actualXC->takeOverFrom(oldContext); }
-
- void regStats(const std::string &name) { actualXC->regStats(name); }
-
- void serialize(std::ostream &os) { actualXC->serialize(os); }
- void unserialize(Checkpoint *cp, const std::string §ion)
- { actualXC->unserialize(cp, section); }
-
-#if FULL_SYSTEM
- EndQuiesceEvent *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
-
- Tick readLastActivate() { return actualXC->readLastActivate(); }
- Tick readLastSuspend() { return actualXC->readLastSuspend(); }
-
- void profileClear() { return actualXC->profileClear(); }
- void profileSample() { return actualXC->profileSample(); }
-#endif
-
- int getThreadNum() { return actualXC->getThreadNum(); }
-
- // @todo: Do I need this?
- MachInst getInst() { return actualXC->getInst(); }
-
- // @todo: Do I need this?
- void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); }
-
- void clearArchRegs() { actualXC->clearArchRegs(); }
-
- //
- // New accessors for new decoder.
- //
- uint64_t readIntReg(int reg_idx)
- { return actualXC->readIntReg(reg_idx); }
-
- FloatReg readFloatReg(int reg_idx, int width)
- { return actualXC->readFloatReg(reg_idx, width); }
-
- FloatReg readFloatReg(int reg_idx)
- { return actualXC->readFloatReg(reg_idx); }
-
- FloatRegBits readFloatRegBits(int reg_idx, int width)
- { return actualXC->readFloatRegBits(reg_idx, width); }
-
- FloatRegBits readFloatRegBits(int reg_idx)
- { return actualXC->readFloatRegBits(reg_idx); }
-
- void setIntReg(int reg_idx, uint64_t val)
- { actualXC->setIntReg(reg_idx, val); }
-
- void setFloatReg(int reg_idx, FloatReg val, int width)
- { actualXC->setFloatReg(reg_idx, val, width); }
-
- void setFloatReg(int reg_idx, FloatReg val)
- { actualXC->setFloatReg(reg_idx, val); }
-
- void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
- { actualXC->setFloatRegBits(reg_idx, val, width); }
-
- void setFloatRegBits(int reg_idx, FloatRegBits val)
- { actualXC->setFloatRegBits(reg_idx, val); }
-
- uint64_t readPC() { return actualXC->readPC(); }
-
- void setPC(uint64_t val) { actualXC->setPC(val); }
-
- uint64_t readNextPC() { return actualXC->readNextPC(); }
-
- void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
-
- uint64_t readNextNPC() { return actualXC->readNextNPC(); }
-
- void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
-
- MiscReg readMiscReg(int misc_reg)
- { return actualXC->readMiscReg(misc_reg); }
-
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
- { return actualXC->readMiscRegWithEffect(misc_reg, fault); }
-
- Fault setMiscReg(int misc_reg, const MiscReg &val)
- { return actualXC->setMiscReg(misc_reg, val); }
-
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
- { return actualXC->setMiscRegWithEffect(misc_reg, val); }
-
- unsigned readStCondFailures()
- { return actualXC->readStCondFailures(); }
-
- void setStCondFailures(unsigned sc_failures)
- { actualXC->setStCondFailures(sc_failures); }
-#if FULL_SYSTEM
- bool inPalMode() { return actualXC->inPalMode(); }
-#endif
-
- // @todo: Fix this!
- bool misspeculating() { return actualXC->misspeculating(); }
-
-#if !FULL_SYSTEM
- IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
-
- // used to shift args for indirect syscall
- void setSyscallArg(int i, IntReg val)
- { actualXC->setSyscallArg(i, val); }
-
- void setSyscallReturn(SyscallReturn return_value)
- { actualXC->setSyscallReturn(return_value); }
-
-
- Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
-#endif
-
- void changeRegFileContext(RegFile::ContextParam param,
- RegFile::ContextVal val)
- {
- actualXC->changeRegFileContext(param, val);
- }
-};
-
-#endif
#include "sim/host.hh"
#include "cpu/inst_seq.hh" // for InstSeqNum
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
class BaseCPU;
inline
InstRecord *
-getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
+getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu,
const StaticInstPtr staticInst,
Addr pc, int thread = 0)
{
if (DTRACE(InstExec) &&
- (InstRecord::traceMisspec() || !xc->misspeculating())) {
+ (InstRecord::traceMisspec() || !tc->misspeculating())) {
return new InstRecord(cycle, cpu, staticInst, pc,
- xc->misspeculating(), thread);
+ tc->misspeculating(), thread);
}
return NULL;
#include <vector>
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
void
IntrControl::post(int int_num, int index)
{
- std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
- BaseCPU *temp = xcvec[0]->getCpuPtr();
+ std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+ BaseCPU *temp = tcvec[0]->getCpuPtr();
temp->post_interrupt(int_num, index);
}
void
IntrControl::post(int cpu_id, int int_num, int index)
{
- std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
- BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
+ std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+ BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
temp->post_interrupt(int_num, index);
}
void
IntrControl::clear(int int_num, int index)
{
- std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
- BaseCPU *temp = xcvec[0]->getCpuPtr();
+ std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+ BaseCPU *temp = tcvec[0]->getCpuPtr();
temp->clear_interrupt(int_num, index);
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
- std::vector<ExecContext *> &xcvec = cpu->system->execContexts;
- BaseCPU *temp = xcvec[cpu_id]->getCpuPtr();
+ std::vector<ThreadContext *> &tcvec = cpu->system->threadContexts;
+ BaseCPU *temp = tcvec[cpu_id]->getCpuPtr();
temp->clear_interrupt(int_num, index);
}
#include "sim/sim_object.hh"
#include "sim/stats.hh"
-class ExecContext;
+class ThreadContext;
class MemTest : public SimObject
{
public:
#define __CPU_O3_ALPHA_FULL_CPU_HH__
#include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/o3/cpu.hh"
#include "sim/byteswap.hh"
AlphaFullCPU(Params *params);
/**
- * Derived ExecContext class for use with the AlphaFullCPU. It
+ * Derived ThreadContext class for use with the AlphaFullCPU. It
* provides the interface for any external objects to access a
* single thread's state and some general CPU state. Any time
* external objects try to update state through this interface,
* the CPU will create an event to squash all in-flight
* instructions in order to ensure state is maintained correctly.
*/
- class AlphaXC : public ExecContext
+ class AlphaTC : public ThreadContext
{
public:
/** Pointer to the CPU. */
AlphaFullCPU<Impl> *cpu;
- /** Pointer to the thread state that this XC corrseponds to. */
+ /** Pointer to the thread state that this TC corrseponds to. */
O3ThreadState<Impl> *thread;
/** Returns a pointer to this CPU. */
virtual void dumpFuncProfile();
#endif
/** Takes over execution of a thread from another CPU. */
- virtual void takeOverFrom(ExecContext *old_context);
+ virtual void takeOverFrom(ThreadContext *old_context);
- /** Registers statistics associated with this XC. */
+ /** Registers statistics associated with this TC. */
virtual void regStats(const std::string &name);
/** Serializes state. */
*/
virtual TheISA::MachInst getInst();
- /** Copies the architectural registers from another XC into this XC. */
- virtual void copyArchRegs(ExecContext *xc);
+ /** Copies the architectural registers from another TC into this TC. */
+ virtual void copyArchRegs(ThreadContext *tc);
/** Resets all architectural registers to 0. */
virtual void clearArchRegs();
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of
- * state through the XC.
+ * state through the TC.
*/
- void squashFromXC(unsigned tid);
+ void squashFromTC(unsigned tid);
#if FULL_SYSTEM
/** Posts an interrupt. */
// SMT is not supported in FS mode yet.
assert(this->numThreads == 1);
this->thread[i] = new Thread(this, 0, params->mem);
- this->thread[i]->setStatus(ExecContext::Suspended);
+ this->thread[i]->setStatus(ThreadContext::Suspended);
#else
if (i < params->workload.size()) {
DPRINTF(FullCPU, "FullCPU: Workload[%i] process is %#x",
this->thread[i] = new Thread(this, i, params->workload[i],
i, params->mem);
- this->thread[i]->setStatus(ExecContext::Suspended);
+ this->thread[i]->setStatus(ThreadContext::Suspended);
//usedTids[i] = true;
//threadMap[i] = i;
} else {
- //Allocate Empty execution context so M5 can use later
+ //Allocate Empty thread so M5 can use later
//when scheduling threads to CPU
Process* dummy_proc = NULL;
}
#endif // !FULL_SYSTEM
- ExecContext *xc_proxy;
+ ThreadContext *tc;
- // Setup the XC that will serve as the interface to the threads/CPU.
- AlphaXC *alpha_xc = new AlphaXC;
+ // Setup the TC that will serve as the interface to the threads/CPU.
+ AlphaTC *alpha_tc = new AlphaTC;
- // If we're using a checker, then the XC should be the
- // CheckerExecContext.
+ // If we're using a checker, then the TC should be the
+ // CheckerThreadContext.
if (params->checker) {
- xc_proxy = new CheckerExecContext<AlphaXC>(
- alpha_xc, this->checker);
+ tc = new CheckerThreadContext<AlphaTC>(
+ alpha_tc, this->checker);
} else {
- xc_proxy = alpha_xc;
+ tc = alpha_tc;
}
- alpha_xc->cpu = this;
- alpha_xc->thread = this->thread[i];
+ alpha_tc->cpu = this;
+ alpha_tc->thread = this->thread[i];
#if FULL_SYSTEM
// Setup quiesce event.
this->thread[i]->quiesceEvent =
- new EndQuiesceEvent(xc_proxy);
+ new EndQuiesceEvent(tc);
this->thread[i]->lastActivate = 0;
this->thread[i]->lastSuspend = 0;
#endif
- // Give the thread the XC.
- this->thread[i]->xcProxy = xc_proxy;
+ // Give the thread the TC.
+ this->thread[i]->tc = tc;
- // Add the XC to the CPU's list of XC's.
- this->execContexts.push_back(xc_proxy);
+ // Add the TC to the CPU's list of TC's.
+ this->threadContexts.push_back(tc);
}
#if FULL_SYSTEM
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::dumpFuncProfile()
+AlphaFullCPU<Impl>::AlphaTC::dumpFuncProfile()
{
// Currently not supported
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::takeOverFrom(ExecContext *old_context)
+AlphaFullCPU<Impl>::AlphaTC::takeOverFrom(ThreadContext *old_context)
{
// some things should already be set up
assert(getMemPort() == old_context->getMemPort());
#else
EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
if (other_quiesce) {
- // Point the quiesce event's XC at this XC so that it wakes up
+ // Point the quiesce event's TC at this TC so that it wakes up
// the proper CPU.
- other_quiesce->xc = this;
+ other_quiesce->tc = this;
}
if (thread->quiesceEvent) {
- thread->quiesceEvent->xc = this;
+ thread->quiesceEvent->tc = this;
}
// Transfer kernel stats from one CPU to the other.
cpu->lockFlag = false;
#endif
- old_context->setStatus(ExecContext::Unallocated);
+ old_context->setStatus(ThreadContext::Unallocated);
thread->inSyscall = false;
thread->trapPending = false;
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::activate(int delay)
+AlphaFullCPU<Impl>::AlphaTC::activate(int delay)
{
- DPRINTF(FullCPU, "Calling activate on AlphaXC\n");
+ DPRINTF(FullCPU, "Calling activate on AlphaTC\n");
- if (thread->status() == ExecContext::Active)
+ if (thread->status() == ThreadContext::Active)
return;
#if FULL_SYSTEM
thread->lastActivate = curTick;
#endif
- if (thread->status() == ExecContext::Unallocated) {
+ if (thread->status() == ThreadContext::Unallocated) {
cpu->activateWhenReady(thread->tid);
return;
}
- thread->setStatus(ExecContext::Active);
+ thread->setStatus(ThreadContext::Active);
// status() == Suspended
cpu->activateContext(thread->tid, delay);
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::suspend()
+AlphaFullCPU<Impl>::AlphaTC::suspend()
{
- DPRINTF(FullCPU, "Calling suspend on AlphaXC\n");
+ DPRINTF(FullCPU, "Calling suspend on AlphaTC\n");
- if (thread->status() == ExecContext::Suspended)
+ if (thread->status() == ThreadContext::Suspended)
return;
#if FULL_SYSTEM
#if FULL_SYSTEM
// Don't change the status from active if there are pending interrupts
if (cpu->check_interrupts()) {
- assert(status() == ExecContext::Active);
+ assert(status() == ThreadContext::Active);
return;
}
#endif
*/
- thread->setStatus(ExecContext::Suspended);
+ thread->setStatus(ThreadContext::Suspended);
cpu->suspendContext(thread->tid);
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::deallocate()
+AlphaFullCPU<Impl>::AlphaTC::deallocate()
{
- DPRINTF(FullCPU, "Calling deallocate on AlphaXC\n");
+ DPRINTF(FullCPU, "Calling deallocate on AlphaTC\n");
- if (thread->status() == ExecContext::Unallocated)
+ if (thread->status() == ThreadContext::Unallocated)
return;
- thread->setStatus(ExecContext::Unallocated);
+ thread->setStatus(ThreadContext::Unallocated);
cpu->deallocateContext(thread->tid);
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::halt()
+AlphaFullCPU<Impl>::AlphaTC::halt()
{
- DPRINTF(FullCPU, "Calling halt on AlphaXC\n");
+ DPRINTF(FullCPU, "Calling halt on AlphaTC\n");
- if (thread->status() == ExecContext::Halted)
+ if (thread->status() == ThreadContext::Halted)
return;
- thread->setStatus(ExecContext::Halted);
+ thread->setStatus(ThreadContext::Halted);
cpu->haltContext(thread->tid);
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::regStats(const std::string &name)
+AlphaFullCPU<Impl>::AlphaTC::regStats(const std::string &name)
{
#if FULL_SYSTEM
thread->kernelStats = new Kernel::Statistics(cpu->system);
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::serialize(std::ostream &os)
+AlphaFullCPU<Impl>::AlphaTC::serialize(std::ostream &os)
{
#if FULL_SYSTEM
if (thread->kernelStats)
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::unserialize(Checkpoint *cp, const std::string §ion)
+AlphaFullCPU<Impl>::AlphaTC::unserialize(Checkpoint *cp, const std::string §ion)
{
#if FULL_SYSTEM
if (thread->kernelStats)
#if FULL_SYSTEM
template <class Impl>
EndQuiesceEvent *
-AlphaFullCPU<Impl>::AlphaXC::getQuiesceEvent()
+AlphaFullCPU<Impl>::AlphaTC::getQuiesceEvent()
{
return thread->quiesceEvent;
}
template <class Impl>
Tick
-AlphaFullCPU<Impl>::AlphaXC::readLastActivate()
+AlphaFullCPU<Impl>::AlphaTC::readLastActivate()
{
return thread->lastActivate;
}
template <class Impl>
Tick
-AlphaFullCPU<Impl>::AlphaXC::readLastSuspend()
+AlphaFullCPU<Impl>::AlphaTC::readLastSuspend()
{
return thread->lastSuspend;
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::profileClear()
+AlphaFullCPU<Impl>::AlphaTC::profileClear()
{}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::profileSample()
+AlphaFullCPU<Impl>::AlphaTC::profileSample()
{}
#endif
template <class Impl>
TheISA::MachInst
-AlphaFullCPU<Impl>::AlphaXC:: getInst()
+AlphaFullCPU<Impl>::AlphaTC:: getInst()
{
return thread->inst;
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::copyArchRegs(ExecContext *xc)
+AlphaFullCPU<Impl>::AlphaTC::copyArchRegs(ThreadContext *tc)
{
// This function will mess things up unless the ROB is empty and
// there are no instructions in the pipeline.
DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
"now has data %lli.\n",
renamed_reg, cpu->readIntReg(renamed_reg),
- xc->readIntReg(i));
+ tc->readIntReg(i));
- cpu->setIntReg(renamed_reg, xc->readIntReg(i));
+ cpu->setIntReg(renamed_reg, tc->readIntReg(i));
}
// Then loop through the floating point registers.
for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
renamed_reg = cpu->renameMap[tid].lookup(i + AlphaISA::FP_Base_DepTag);
cpu->setFloatRegBits(renamed_reg,
- xc->readFloatRegBits(i));
+ tc->readFloatRegBits(i));
}
// Copy the misc regs.
- copyMiscRegs(xc, this);
+ copyMiscRegs(tc, this);
// Then finally set the PC and the next PC.
- cpu->setPC(xc->readPC(), tid);
- cpu->setNextPC(xc->readNextPC(), tid);
+ cpu->setPC(tc->readPC(), tid);
+ cpu->setNextPC(tc->readNextPC(), tid);
#if !FULL_SYSTEM
- this->thread->funcExeInst = xc->readFuncExeInst();
+ this->thread->funcExeInst = tc->readFuncExeInst();
#endif
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::clearArchRegs()
+AlphaFullCPU<Impl>::AlphaTC::clearArchRegs()
{}
template <class Impl>
uint64_t
-AlphaFullCPU<Impl>::AlphaXC::readIntReg(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readIntReg(int reg_idx)
{
return cpu->readArchIntReg(reg_idx, thread->tid);
}
template <class Impl>
FloatReg
-AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx, int width)
+AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx, int width)
{
switch(width) {
case 32:
template <class Impl>
FloatReg
-AlphaFullCPU<Impl>::AlphaXC::readFloatReg(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readFloatReg(int reg_idx)
{
return cpu->readArchFloatRegSingle(reg_idx, thread->tid);
}
template <class Impl>
FloatRegBits
-AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx, int width)
+AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx, int width)
{
- DPRINTF(Fault, "Reading floatint register through the XC!\n");
+ DPRINTF(Fault, "Reading floatint register through the TC!\n");
return cpu->readArchFloatRegInt(reg_idx, thread->tid);
}
template <class Impl>
FloatRegBits
-AlphaFullCPU<Impl>::AlphaXC::readFloatRegBits(int reg_idx)
+AlphaFullCPU<Impl>::AlphaTC::readFloatRegBits(int reg_idx)
{
return cpu->readArchFloatRegInt(reg_idx, thread->tid);
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setIntReg(int reg_idx, uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setIntReg(int reg_idx, uint64_t val)
{
cpu->setArchIntReg(reg_idx, val, thread->tid);
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val, int width)
+AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width)
{
switch(width) {
case 32:
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setFloatReg(int reg_idx, FloatReg val)
+AlphaFullCPU<Impl>::AlphaTC::setFloatReg(int reg_idx, FloatReg val)
{
cpu->setArchFloatRegSingle(reg_idx, val, thread->tid);
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val,
+AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val,
int width)
{
- DPRINTF(Fault, "Setting floatint register through the XC!\n");
+ DPRINTF(Fault, "Setting floatint register through the TC!\n");
cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setFloatRegBits(int reg_idx, FloatRegBits val)
+AlphaFullCPU<Impl>::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val)
{
cpu->setArchFloatRegInt(reg_idx, val, thread->tid);
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setPC(uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setPC(uint64_t val)
{
cpu->setPC(val, thread->tid);
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setNextPC(uint64_t val)
+AlphaFullCPU<Impl>::AlphaTC::setNextPC(uint64_t val)
{
cpu->setNextPC(val, thread->tid);
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
}
template <class Impl>
Fault
-AlphaFullCPU<Impl>::AlphaXC::setMiscReg(int misc_reg, const MiscReg &val)
+AlphaFullCPU<Impl>::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val)
{
Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->tid);
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
return ret_fault;
template <class Impl>
Fault
-AlphaFullCPU<Impl>::AlphaXC::setMiscRegWithEffect(int misc_reg,
+AlphaFullCPU<Impl>::AlphaTC::setMiscRegWithEffect(int misc_reg,
const MiscReg &val)
{
Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->tid);
// Squash if we're not already in a state update mode.
if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromXC(thread->tid);
+ cpu->squashFromTC(thread->tid);
}
return ret_fault;
template <class Impl>
TheISA::IntReg
-AlphaFullCPU<Impl>::AlphaXC::getSyscallArg(int i)
+AlphaFullCPU<Impl>::AlphaTC::getSyscallArg(int i)
{
return cpu->getSyscallArg(i, thread->tid);
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setSyscallArg(int i, IntReg val)
+AlphaFullCPU<Impl>::AlphaTC::setSyscallArg(int i, IntReg val)
{
cpu->setSyscallArg(i, val, thread->tid);
}
template <class Impl>
void
-AlphaFullCPU<Impl>::AlphaXC::setSyscallReturn(SyscallReturn return_value)
+AlphaFullCPU<Impl>::AlphaTC::setSyscallReturn(SyscallReturn return_value)
{
cpu->setSyscallReturn(return_value, thread->tid);
}
template <class Impl>
void
-AlphaFullCPU<Impl>::squashFromXC(unsigned tid)
+AlphaFullCPU<Impl>::squashFromTC(unsigned tid)
{
this->thread[tid]->inSyscall = true;
- this->commit.generateXCEvent(tid);
+ this->commit.generateTCEvent(tid);
}
#if FULL_SYSTEM
{
BaseCPU::post_interrupt(int_num, index);
- if (this->thread[0]->status() == ExecContext::Suspended) {
+ if (this->thread[0]->status() == ThreadContext::Suspended) {
DPRINTF(IPI,"Suspended Processor awoke\n");
- this->execContexts[0]->activate();
+ this->threadContexts[0]->activate();
}
}
{
if (this->thread[tid]->kernelStats)
this->thread[tid]->kernelStats->callpal(palFunc,
- this->execContexts[tid]);
+ this->threadContexts[tid]);
switch (palFunc) {
case PAL::halt:
void
AlphaFullCPU<Impl>::trap(Fault fault, unsigned tid)
{
- // Pass the thread's XC into the invoke method.
- fault->invoke(this->execContexts[tid]);
+ // Pass the thread's TC into the invoke method.
+ fault->invoke(this->threadContexts[tid]);
}
template <class Impl>
AlphaDynInst<Impl>::execute()
{
// @todo: Pretty convoluted way to avoid squashing from happening
- // when using the XC during an instruction's execution
+ // when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
- // the XC). Fix this.
+ // the TC). Fix this.
bool in_syscall = this->thread->inSyscall;
this->thread->inSyscall = true;
AlphaDynInst<Impl>::initiateAcc()
{
// @todo: Pretty convoluted way to avoid squashing from happening
- // when using the XC during an instruction's execution
+ // when using the TC during an instruction's execution
// (specifically for instructions that have side-effects that use
- // the XC). Fix this.
+ // the TC). Fix this.
bool in_syscall = this->thread->inSyscall;
this->thread->inSyscall = true;
void generateTrapEvent(unsigned tid);
/** Records that commit needs to initiate a squash due to an
- * external state update through the XC.
+ * external state update through the TC.
*/
- void generateXCEvent(unsigned tid);
+ void generateTCEvent(unsigned tid);
private:
/** Updates the overall status of commit with the nextStatus, and
/** Handles squashing due to a trap. */
void squashFromTrap(unsigned tid);
- /** Handles squashing due to an XC write. */
- void squashFromXC(unsigned tid);
+ /** Handles squashing due to an TC write. */
+ void squashFromTC(unsigned tid);
/** Commits as many instructions as possible. */
void commitInsts();
bool trapSquash[Impl::MaxThreads];
/** Records if a thread has to squash this cycle due to an XC write. */
- bool xcSquash[Impl::MaxThreads];
+ bool tcSquash[Impl::MaxThreads];
/** Priority List used for Commit Policy */
std::list<unsigned> priority_list;
commitStatus[i] = Idle;
changedROBNumEntries[i] = false;
trapSquash[i] = false;
- xcSquash[i] = false;
+ tcSquash[i] = false;
PC[i] = nextPC[i] = 0;
}
commitStatus[i] = Idle;
changedROBNumEntries[i] = false;
trapSquash[i] = false;
- xcSquash[i] = false;
+ tcSquash[i] = false;
}
squashCounter = 0;
rob->takeOverFrom();
template <class Impl>
void
-DefaultCommit<Impl>::generateXCEvent(unsigned tid)
+DefaultCommit<Impl>::generateTCEvent(unsigned tid)
{
- DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
+ DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
- xcSquash[tid] = true;
+ tcSquash[tid] = true;
}
template <class Impl>
template <class Impl>
void
-DefaultCommit<Impl>::squashFromXC(unsigned tid)
+DefaultCommit<Impl>::squashFromTC(unsigned tid)
{
squashAll(tid);
- DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
+ DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
thread[tid]->inSyscall = false;
assert(!thread[tid]->trapPending);
commitStatus[tid] = ROBSquashing;
cpu->activityThisCycle();
- xcSquash[tid] = false;
+ tcSquash[tid] = false;
++squashCounter;
}
cpu->check_interrupts() &&
!cpu->inPalMode(readPC()) &&
!trapSquash[0] &&
- !xcSquash[0]) {
+ !tcSquash[0]) {
// Tell fetch that there is an interrupt pending. This will
// make fetch wait until it sees a non PAL-mode PC, at which
// point it stops fetching instructions.
// Not sure which one takes priority. I think if we have
// both, that's a bad sign.
if (trapSquash[tid] == true) {
- assert(!xcSquash[tid]);
+ assert(!tcSquash[tid]);
squashFromTrap(tid);
- } else if (xcSquash[tid] == true) {
- squashFromXC(tid);
+ } else if (tcSquash[tid] == true) {
+ squashFromTC(tid);
}
// Squashed sequence number must be older than youngest valid
#include "cpu/activity.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/o3/alpha_dyn_inst.hh"
#include "cpu/o3/alpha_impl.hh"
#include "cpu/o3/cpu.hh"
FullO3CPU<Impl>::init()
{
if (!deferRegistration) {
- registerExecContexts();
+ registerThreadContexts();
}
// Set inSyscall so that the CPU doesn't squash when initially
for (int tid=0; tid < number_of_threads; tid++) {
#if FULL_SYSTEM
- ExecContext *src_xc = execContexts[tid];
+ ThreadContext *src_tc = threadContexts[tid];
#else
- ExecContext *src_xc = thread[tid]->getXCProxy();
+ ThreadContext *src_tc = thread[tid]->getTC();
#endif
// Threads start in the Suspended State
- if (src_xc->status() != ExecContext::Suspended) {
+ if (src_tc->status() != ThreadContext::Suspended) {
continue;
}
#if FULL_SYSTEM
- TheISA::initCPU(src_xc, src_xc->readCpuId());
+ TheISA::initCPU(src_tc, src_tc->readCpuId());
#endif
}
// and not in the CPUExecContext.
#if 0
#if FULL_SYSTEM
- ExecContext *src_xc = system->execContexts[tid];
+ ThreadContext *src_tc = system->threadContexts[tid];
#else
- CPUExecContext *src_xc = thread[tid];
+ CPUExecContext *src_tc = thread[tid];
#endif
//Bind Int Regs to Rename Map
}
//Copy Thread Data Into RegFile
- this->copyFromXC(tid);
+ this->copyFromTC(tid);
//Set PC/NPC
- regFile.pc[tid] = src_xc->readPC();
- regFile.npc[tid] = src_xc->readNextPC();
+ regFile.pc[tid] = src_tc->readPC();
+ regFile.npc[tid] = src_tc->readNextPC();
- src_xc->setStatus(ExecContext::Active);
+ src_tc->setStatus(ThreadContext::Active);
activateContext(tid,1);
* in the sense that it's finished (exiting)? If the thread is just
* being suspended we might...
*/
-// this->copyToXC(tid);
+// this->copyToTC(tid);
//Squash Throughout Pipeline
fetch.squash(0,tid);
// Set all statuses to active, schedule the CPU's tick event.
// @todo: Fix up statuses so this is handled properly
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
- if (xc->status() == ExecContext::Active && _status != Running) {
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
+ if (tc->status() == ThreadContext::Active && _status != Running) {
_status = Running;
tickEvent.schedule(curTick);
}
template <class>
class Checker;
-class ExecContext;
+class ThreadContext;
class MemObject;
class Process;
int getFreeTid();
public:
- /** Returns a pointer to a thread's exec context. */
- ExecContext *xcBase(unsigned tid)
+ /** Returns a pointer to a thread context. */
+ ThreadContext *tcBase(unsigned tid)
{
- return thread[tid]->getXCProxy();
+ return thread[tid]->getTC();
}
/** The global sequence number counter. */
tid, instruction->staticInst->disassemble(fetch_PC));
instruction->traceData =
- Trace::getInstRecord(curTick, cpu->xcBase(tid), cpu,
+ Trace::getInstRecord(curTick, cpu->tcBase(tid), cpu,
instruction->staticInst,
instruction->readPC(),tid);
unsigned thread_id)
{
return miscRegs[thread_id].readRegWithEffect(misc_reg, fault,
- cpu->xcBase(thread_id));
+ cpu->tcBase(thread_id));
}
Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned thread_id)
unsigned thread_id)
{
return miscRegs[thread_id].setRegWithEffect(misc_reg, val,
- cpu->xcBase(thread_id));
+ cpu->tcBase(thread_id));
}
#if FULL_SYSTEM
#include "arch/faults.hh"
#include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
class Event;
/**
* Class that has various thread state, such as the status, the
* current instruction being processed, whether or not the thread has
- * a trap pending or is being externally updated, the ExecContext
- * proxy pointer, etc. It also handles anything related to a specific
+ * a trap pending or is being externally updated, the ThreadContext
+ * pointer, etc. It also handles anything related to a specific
* thread's process, such as syscalls and checking valid addresses.
*/
template <class Impl>
struct O3ThreadState : public ThreadState {
- typedef ExecContext::Status Status;
+ typedef ThreadContext::Status Status;
typedef typename Impl::FullCPU FullCPU;
/** Current status of the thread. */
{ }
#endif
- /** Pointer to the ExecContext of this thread. @todo: Don't call
- this a proxy.*/
- ExecContext *xcProxy;
+ /** Pointer to the ThreadContext of this thread. */
+ ThreadContext *tc;
- /** Returns a pointer to the XC of this thread. */
- ExecContext *getXCProxy() { return xcProxy; }
+ /** Returns a pointer to the TC of this thread. */
+ ThreadContext *getTC() { return tc; }
/** Returns the status of this thread. */
Status status() const { return _status; }
#if !FULL_SYSTEM
/** Handles the syscall. */
- void syscall(int64_t callnum) { process->syscall(callnum, xcProxy); }
+ void syscall(int64_t callnum) { process->syscall(callnum, tc); }
#endif
};
#include "mem/request.hh"
#include "sim/eventq.hh"
-class ExecContext;
+class ThreadContext;
template <class Impl>
class OzoneThreadState;
void setFrontEnd(FrontEnd *front_end_ptr)
{ frontEnd = front_end_ptr; }
- void setXC(ExecContext *xc_ptr)
- { xc = xc_ptr; }
+ void setTC(ThreadContext *tc_ptr)
+ { tc = tc_ptr; }
void setThreadState(Thread *thread_ptr)
{ thread = thread_ptr; }
void tick();
void squash();
- void squashFromXC();
- bool xcSquash;
+ void squashFromTC();
+ bool tcSquash;
template <class T>
Fault read(RequestPtr req, T &data, int load_idx);
FrontEnd *frontEnd;
- ExecContext *xc;
+ ThreadContext *tc;
Thread *thread;
#include "base/timebuf.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ozone/rename_table.hh"
#include "cpu/ozone/thread_state.hh"
typedef TheISA::MiscReg MiscReg;
public:
- class OzoneXC : public ExecContext {
+ class OzoneTC : public ThreadContext {
public:
OzoneCPU<Impl> *cpu;
void dumpFuncProfile();
#endif
- void takeOverFrom(ExecContext *old_context);
+ void takeOverFrom(ThreadContext *old_context);
void regStats(const std::string &name);
// Also somewhat obnoxious. Really only used for the TLB fault.
TheISA::MachInst getInst();
- void copyArchRegs(ExecContext *xc);
+ void copyArchRegs(ThreadContext *tc);
void clearArchRegs();
{ panic("Not supported on Alpha!"); }
};
- // execution context proxy
- OzoneXC ozoneXC;
- ExecContext *xcProxy;
- ExecContext *checkerXC;
+ // Ozone specific thread context
+ OzoneTC ozoneTC;
+ // Thread context to be used
+ ThreadContext *tc;
+ // Checker thread context; will wrap the OzoneTC if a checker is
+ // being used.
+ ThreadContext *checkerTC;
typedef OzoneThreadState<Impl> ImplState;
// and all other stores (WH64?). Unsuccessful Store
// Conditionals would have returned above, and wouldn't fall
// through.
- for (int i = 0; i < this->system->execContexts.size(); i++){
- xc = this->system->execContexts[i];
+ for (int i = 0; i < this->system->threadContexts.size(); i++){
+ xc = this->system->threadContexts[i];
if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
(req->paddr & ~0xf)) {
xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
InstSeqNum globalSeqNum;
public:
- void squashFromXC();
+ void squashFromTC();
// @todo: This can be a useful debug function. Implement it.
void dumpInsts() { frontEnd->dumpInsts(); }
void setSyscallReturn(SyscallReturn return_value, int tid);
#endif
- ExecContext *xcBase() { return xcProxy; }
+ ThreadContext *tcBase() { return tc; }
bool decoupledFrontEnd;
struct CommStruct {
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/checker/exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/quiesce_event.hh"
#if FULL_SYSTEM
checker->setSystem(p->system);
#endif
- checkerXC = new CheckerExecContext<OzoneXC>(&ozoneXC, checker);
- thread.xcProxy = checkerXC;
- xcProxy = checkerXC;
+ checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
+ thread.tc = checkerTC;
+ tc = checkerXC;
} else {
checker = NULL;
- thread.xcProxy = &ozoneXC;
- xcProxy = &ozoneXC;
+ thread.tc = &ozoneTC;
+ tc = &ozoneTC;
}
- ozoneXC.cpu = this;
- ozoneXC.thread = &thread;
+ ozoneTC.cpu = this;
+ ozoneTC.thread = &thread;
thread.inSyscall = false;
- thread.setStatus(ExecContext::Suspended);
+ thread.setStatus(ThreadContext::Suspended);
#if FULL_SYSTEM
/***** All thread state stuff *****/
thread.cpu = this;
thread.tid = 0;
thread.mem = p->mem;
- thread.quiesceEvent = new EndQuiesceEvent(xcProxy);
+ thread.quiesceEvent = new EndQuiesceEvent(tc);
system = p->system;
itb = p->itb;
if (p->profile) {
thread.profile = new FunctionProfile(p->system->kernelSymtab);
- // @todo: This might be better as an ExecContext instead of OzoneXC
+ // @todo: This might be better as an ThreadContext instead of OzoneTC
Callback *cb =
- new MakeCallback<OzoneXC,
- &OzoneXC::dumpFuncProfile>(&ozoneXC);
+ new MakeCallback<OzoneTC,
+ &OzoneTC::dumpFuncProfile>(&ozoneTC);
registerExitCallback(cb);
}
numInst = 0;
startNumInst = 0;
- execContexts.push_back(xcProxy);
+ threadContexts.push_back(tc);
frontEnd->setCPU(this);
backEnd->setCPU(this);
- frontEnd->setXC(xcProxy);
- backEnd->setXC(xcProxy);
+ frontEnd->setTC(tc);
+ backEnd->setTC(tc);
frontEnd->setThreadState(&thread);
backEnd->setThreadState(&thread);
comm.advance();
}
- // if any of this CPU's ExecContexts are active, mark the CPU as
+ // if any of this CPU's ThreadContexts are active, mark the CPU as
// running and schedule its tick event.
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
- if (xc->status() == ExecContext::Active &&
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
+ if (tc->status() == ThreadContext::Active &&
_status != Running) {
_status = Running;
tickEvent.schedule(curTick);
notIdleFraction++;
scheduleTickEvent(delay);
_status = Running;
- thread._status = ExecContext::Active;
+ thread._status = ThreadContext::Active;
frontEnd->wakeFromQuiesce();
}
// Mark this as in syscall so it won't need to squash
thread.inSyscall = true;
#if FULL_SYSTEM
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(xc, xc->readCpuId());
+ TheISA::initCPU(tc, tc->readCpuId());
}
#endif
frontEnd->renameTable.copyFrom(thread.renameTable);
{
BaseCPU::serialize(os);
SERIALIZE_ENUM(_status);
- nameOut(os, csprintf("%s.xc", name()));
- ozoneXC.serialize(os);
+ nameOut(os, csprintf("%s.tc", name()));
+ ozoneTC.serialize(os);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
}
{
BaseCPU::unserialize(cp, section);
UNSERIALIZE_ENUM(_status);
- ozoneXC.unserialize(cp, csprintf("%s.xc", section));
+ ozoneTC.unserialize(cp, csprintf("%s.tc", section));
tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
}
memReq->reset(src & ~(blk_size - 1), blk_size);
// translate to physical address
- Fault fault = xc->translateDataReadReq(memReq);
+ Fault fault = tc->translateDataReadReq(memReq);
assert(fault != Alignment_Fault);
if (fault == NoFault) {
- xc->copySrcAddr = src;
- xc->copySrcPhysAddr = memReq->paddr + offset;
+ tc->copySrcAddr = src;
+ tc->copySrcPhysAddr = memReq->paddr + offset;
} else {
- xc->copySrcAddr = 0;
- xc->copySrcPhysAddr = 0;
+ tc->copySrcAddr = 0;
+ tc->copySrcPhysAddr = 0;
}
return fault;
#endif
// Only support block sizes of 64 atm.
assert(blk_size == 64);
uint8_t data[blk_size];
- //assert(xc->copySrcAddr);
+ //assert(tc->copySrcAddr);
int offset = dest & (blk_size - 1);
// Make sure block doesn't span page
memReq->reset(dest & ~(blk_size -1), blk_size);
// translate to physical address
- Fault fault = xc->translateDataWriteReq(memReq);
+ Fault fault = tc->translateDataWriteReq(memReq);
assert(fault != Alignment_Fault);
if (fault == NoFault) {
Addr dest_addr = memReq->paddr + offset;
// Need to read straight from memory since we have more than 8 bytes.
- memReq->paddr = xc->copySrcPhysAddr;
- xc->mem->read(memReq, data);
+ memReq->paddr = tc->copySrcPhysAddr;
+ tc->mem->read(memReq, data);
memReq->paddr = dest_addr;
- xc->mem->write(memReq, data);
+ tc->mem->write(memReq, data);
if (dcacheInterface) {
memReq->cmd = Copy;
memReq->completionEvent = NULL;
- memReq->paddr = xc->copySrcPhysAddr;
+ memReq->paddr = tc->copySrcPhysAddr;
memReq->dest = dest_addr;
memReq->size = 64;
memReq->time = curTick;
Addr
OzoneCPU<Impl>::dbg_vtophys(Addr addr)
{
- return vtophys(xcProxy, addr);
+ return vtophys(tcProxy, addr);
}
#endif // FULL_SYSTEM
if (_status == Idle) {
DPRINTF(IPI,"Suspended Processor awoke\n");
// thread.activate();
- // Hack for now. Otherwise might have to go through the xcProxy, or
+ // Hack for now. Otherwise might have to go through the tc, or
// I need to figure out what's the right thing to call.
activateContext(thread.tid, 1);
}
template <class Impl>
void
-OzoneCPU<Impl>::squashFromXC()
+OzoneCPU<Impl>::squashFromTC()
{
thread.inSyscall = true;
- backEnd->generateXCEvent();
+ backEnd->generateTCEvent();
}
#if !FULL_SYSTEM
void
OzoneCPU<Impl>::syscall()
{
- // Not sure this copy is needed, depending on how the XC proxy is made.
+ // Not sure this copy is needed, depending on how the TC proxy is made.
thread.renameTable.copyFrom(backEnd->renameTable);
thread.inSyscall = true;
DPRINTF(OzoneCPU, "FuncExeInst: %i\n", thread.funcExeInst);
- thread.process->syscall(xcProxy);
+ thread.process->syscall(yc);
thread.funcExeInst--;
checker->cpuXCBase()->setMiscReg(IPR_INTID, ipl);
}
Fault fault = new InterruptFault;
- fault->invoke(thread.getXCProxy());
+ fault->invoke(thread.getTC());
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
thread.readMiscReg(IPR_IPLR), ipl, summary);
}
{
// Need to move this to ISA code
// May also need to make this per thread
- thread.kernelStats->callpal(palFunc, xcProxy);
+ thread.kernelStats->callpal(palFunc, tc);
switch (palFunc) {
case PAL::halt:
template <class Impl>
BaseCPU *
-OzoneCPU<Impl>::OzoneXC::getCpuPtr()
+OzoneCPU<Impl>::OzoneTC::getCpuPtr()
{
return cpu;
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setCpuId(int id)
+OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
{
cpu->cpuId = id;
thread->cpuId = id;
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setStatus(Status new_status)
+OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
{
thread->_status = new_status;
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::activate(int delay)
+OzoneCPU<Impl>::OzoneTC::activate(int delay)
{
cpu->activateContext(thread->tid, delay);
}
/// Set the status to Suspended.
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::suspend()
+OzoneCPU<Impl>::OzoneTC::suspend()
{
cpu->suspendContext(thread->tid);
}
/// Set the status to Unallocated.
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::deallocate()
+OzoneCPU<Impl>::OzoneTC::deallocate()
{
cpu->deallocateContext(thread->tid);
}
/// Set the status to Halted.
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::halt()
+OzoneCPU<Impl>::OzoneTC::halt()
{
cpu->haltContext(thread->tid);
}
#if FULL_SYSTEM
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::dumpFuncProfile()
+OzoneCPU<Impl>::OzoneTC::dumpFuncProfile()
{ }
#endif
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::takeOverFrom(ExecContext *old_context)
+OzoneCPU<Impl>::OzoneTC::takeOverFrom(ThreadContext *old_context)
{
// some things should already be set up
assert(getMemPtr() == old_context->getMemPtr());
#else
EndQuiesceEvent *other_quiesce = old_context->getQuiesceEvent();
if (other_quiesce) {
- // Point the quiesce event's XC at this XC so that it wakes up
+ // Point the quiesce event's TC at this TC so that it wakes up
// the proper CPU.
- other_quiesce->xc = this;
+ other_quiesce->tc = this;
}
if (thread->quiesceEvent) {
- thread->quiesceEvent->xc = this;
+ thread->quiesceEvent->tc = this;
}
thread->kernelStats = old_context->getKernelStats();
cpu->lockFlag = false;
#endif
- old_context->setStatus(ExecContext::Unallocated);
+ old_context->setStatus(ThreadContext::Unallocated);
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::regStats(const std::string &name)
+OzoneCPU<Impl>::OzoneTC::regStats(const std::string &name)
{
#if FULL_SYSTEM
thread->kernelStats = new Kernel::Statistics(cpu->system);
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::serialize(std::ostream &os)
+OzoneCPU<Impl>::OzoneTC::serialize(std::ostream &os)
{ }
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::unserialize(Checkpoint *cp, const std::string §ion)
+OzoneCPU<Impl>::OzoneTC::unserialize(Checkpoint *cp, const std::string §ion)
{ }
#if FULL_SYSTEM
template <class Impl>
EndQuiesceEvent *
-OzoneCPU<Impl>::OzoneXC::getQuiesceEvent()
+OzoneCPU<Impl>::OzoneTC::getQuiesceEvent()
{
return thread->quiesceEvent;
}
template <class Impl>
Tick
-OzoneCPU<Impl>::OzoneXC::readLastActivate()
+OzoneCPU<Impl>::OzoneTC::readLastActivate()
{
return thread->lastActivate;
}
template <class Impl>
Tick
-OzoneCPU<Impl>::OzoneXC::readLastSuspend()
+OzoneCPU<Impl>::OzoneTC::readLastSuspend()
{
return thread->lastSuspend;
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::profileClear()
+OzoneCPU<Impl>::OzoneTC::profileClear()
{
if (thread->profile)
thread->profile->clear();
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::profileSample()
+OzoneCPU<Impl>::OzoneTC::profileSample()
{
if (thread->profile)
thread->profile->sample(thread->profileNode, thread->profilePC);
template <class Impl>
int
-OzoneCPU<Impl>::OzoneXC::getThreadNum()
+OzoneCPU<Impl>::OzoneTC::getThreadNum()
{
return thread->tid;
}
// Also somewhat obnoxious. Really only used for the TLB fault.
template <class Impl>
TheISA::MachInst
-OzoneCPU<Impl>::OzoneXC::getInst()
+OzoneCPU<Impl>::OzoneTC::getInst()
{
return thread->inst;
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::copyArchRegs(ExecContext *xc)
+OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
{
- thread->PC = xc->readPC();
- thread->nextPC = xc->readNextPC();
+ thread->PC = tc->readPC();
+ thread->nextPC = tc->readNextPC();
cpu->frontEnd->setPC(thread->PC);
cpu->frontEnd->setNextPC(thread->nextPC);
for (int i = 0; i < TheISA::TotalNumRegs; ++i) {
if (i < TheISA::FP_Base_DepTag) {
- thread->renameTable[i]->setIntResult(xc->readIntReg(i));
+ thread->renameTable[i]->setIntResult(tc->readIntReg(i));
} else if (i < (TheISA::FP_Base_DepTag + TheISA::NumFloatRegs)) {
int fp_idx = i - TheISA::FP_Base_DepTag;
thread->renameTable[i]->setDoubleResult(
- xc->readFloatRegDouble(fp_idx));
+ tc->readFloatRegDouble(fp_idx));
}
}
#if !FULL_SYSTEM
- thread->funcExeInst = xc->readFuncExeInst();
+ thread->funcExeInst = tc->readFuncExeInst();
#endif
- // Need to copy the XC values into the current rename table,
+ // Need to copy the TC values into the current rename table,
// copy the misc regs.
- thread->regs.miscRegs.copyMiscRegs(xc);
+ thread->regs.miscRegs.copyMiscRegs(tc);
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::clearArchRegs()
+OzoneCPU<Impl>::OzoneTC::clearArchRegs()
{
panic("Unimplemented!");
}
template <class Impl>
uint64_t
-OzoneCPU<Impl>::OzoneXC::readIntReg(int reg_idx)
+OzoneCPU<Impl>::OzoneTC::readIntReg(int reg_idx)
{
return thread->renameTable[reg_idx]->readIntResult();
}
template <class Impl>
float
-OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx, int width)
+OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx, int width)
{
int idx = reg_idx + TheISA::FP_Base_DepTag;
switch(width) {
template <class Impl>
double
-OzoneCPU<Impl>::OzoneXC::readFloatReg(int reg_idx)
+OzoneCPU<Impl>::OzoneTC::readFloatReg(int reg_idx)
{
int idx = reg_idx + TheISA::FP_Base_DepTag;
return thread->renameTable[idx]->readFloatResult();
template <class Impl>
uint64_t
-OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx, int width)
+OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx, int width)
{
int idx = reg_idx + TheISA::FP_Base_DepTag;
return thread->renameTable[idx]->readIntResult();
template <class Impl>
uint64_t
-OzoneCPU<Impl>::OzoneXC::readFloatRegBits(int reg_idx)
+OzoneCPU<Impl>::OzoneTC::readFloatRegBits(int reg_idx)
{
int idx = reg_idx + TheISA::FP_Base_DepTag;
return thread->renameTable[idx]->readIntResult();
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setIntReg(int reg_idx, uint64_t val)
+OzoneCPU<Impl>::OzoneTC::setIntReg(int reg_idx, uint64_t val)
{
thread->renameTable[reg_idx]->setIntResult(val);
if (!thread->inSyscall) {
- cpu->squashFromXC();
+ cpu->squashFromTC();
}
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val, int width)
+OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val, int width)
{
int idx = reg_idx + TheISA::FP_Base_DepTag;
switch(width) {
}
if (!thread->inSyscall) {
- cpu->squashFromXC();
+ cpu->squashFromTC();
}
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setFloatReg(int reg_idx, FloatReg val)
+OzoneCPU<Impl>::OzoneTC::setFloatReg(int reg_idx, FloatReg val)
{
int idx = reg_idx + TheISA::FP_Base_DepTag;
thread->renameTable[idx]->setDoubleResult(val);
if (!thread->inSyscall) {
- cpu->squashFromXC();
+ cpu->squashFromTC();
}
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val,
+OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val,
int width)
{
panic("Unimplemented!");
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setFloatRegBits(int reg_idx, FloatRegBits val)
+OzoneCPU<Impl>::OzoneTC::setFloatRegBits(int reg_idx, FloatRegBits val)
{
panic("Unimplemented!");
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setPC(Addr val)
+OzoneCPU<Impl>::OzoneTC::setPC(Addr val)
{
thread->PC = val;
cpu->frontEnd->setPC(val);
if (!thread->inSyscall) {
- cpu->squashFromXC();
+ cpu->squashFromTC();
}
}
template <class Impl>
void
-OzoneCPU<Impl>::OzoneXC::setNextPC(Addr val)
+OzoneCPU<Impl>::OzoneTC::setNextPC(Addr val)
{
thread->nextPC = val;
cpu->frontEnd->setNextPC(val);
if (!thread->inSyscall) {
- cpu->squashFromXC();
+ cpu->squashFromTC();
}
}
template <class Impl>
TheISA::MiscReg
-OzoneCPU<Impl>::OzoneXC::readMiscReg(int misc_reg)
+OzoneCPU<Impl>::OzoneTC::readMiscReg(int misc_reg)
{
return thread->regs.miscRegs.readReg(misc_reg);
}
template <class Impl>
TheISA::MiscReg
-OzoneCPU<Impl>::OzoneXC::readMiscRegWithEffect(int misc_reg, Fault &fault)
+OzoneCPU<Impl>::OzoneTC::readMiscRegWithEffect(int misc_reg, Fault &fault)
{
return thread->regs.miscRegs.readRegWithEffect(misc_reg,
fault, this);
template <class Impl>
Fault
-OzoneCPU<Impl>::OzoneXC::setMiscReg(int misc_reg, const MiscReg &val)
+OzoneCPU<Impl>::OzoneTC::setMiscReg(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
Fault ret_fault = thread->regs.miscRegs.setReg(misc_reg, val);
if (!thread->inSyscall) {
- cpu->squashFromXC();
+ cpu->squashFromTC();
}
return ret_fault;
template <class Impl>
Fault
-OzoneCPU<Impl>::OzoneXC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+OzoneCPU<Impl>::OzoneTC::setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
// Needs to setup a squash event unless we're in syscall mode
Fault ret_fault = thread->regs.miscRegs.setRegWithEffect(misc_reg, val,
this);
if (!thread->inSyscall) {
- cpu->squashFromXC();
+ cpu->squashFromTC();
}
return ret_fault;
#include "sim/eventq.hh"
#include "sim/stats.hh"
-class ExecContext;
+class ThreadContext;
class MemInterface;
template <class>
class OzoneThreadState;
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::BackEnd BackEnd;
- typedef typename Impl::FullCPU::OzoneXC OzoneXC;
+ typedef typename Impl::FullCPU::OzoneTC OzoneTC;
typedef typename Impl::FullCPU::CommStruct CommStruct;
FrontEnd(Params *params);
void setCommBuffer(TimeBuffer<CommStruct> *_comm);
- void setXC(ExecContext *xc_ptr);
+ void setTC(ThreadContext *tc_ptr);
void setThreadState(OzoneThreadState<Impl> *thread_ptr)
{ thread = thread_ptr; }
void doSwitchOut();
- void takeOverFrom(ExecContext *old_xc = NULL);
+ void takeOverFrom(ThreadContext *old_tc = NULL);
bool isSwitchedOut() { return switchedOut; }
BackEnd *backEnd;
- ExecContext *xc;
+ ThreadContext *tc;
OzoneThreadState<Impl> *thread;
#include "arch/faults.hh"
#include "arch/isa_traits.hh"
#include "base/statistics.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/front_end.hh"
#include "mem/mem_interface.hh"
template <class Impl>
void
-FrontEnd<Impl>::setXC(ExecContext *xc_ptr)
+FrontEnd<Impl>::setTC(ThreadContext *tc_ptr)
{
- xc = xc_ptr;
+ tc = tc_ptr;
}
template <class Impl>
memReq->asid = 0;
memReq->thread_num = 0;
memReq->data = new uint8_t[64];
- memReq->xc = xc;
+ memReq->tc = tc;
memReq->cmd = Read;
memReq->reset(fetch_PC, cacheBlkSize, flags);
instruction->staticInst->disassemble(PC));
instruction->traceData =
- Trace::getInstRecord(curTick, xc, cpu,
+ Trace::getInstRecord(curTick, tc, cpu,
instruction->staticInst,
instruction->readPC(), 0);
template <class Impl>
void
-FrontEnd<Impl>::takeOverFrom(ExecContext *old_xc)
+FrontEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
{
assert(freeRegs == numPhysRegs);
fetchCacheLineNextCycle = true;
#include "arch/faults.hh"
#include "base/timebuf.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/inst_seq.hh"
#include "cpu/ozone/rename_table.hh"
#include "cpu/ozone/thread_state.hh"
typedef typename Impl::FullCPU FullCPU;
typedef typename Impl::FrontEnd FrontEnd;
- typedef typename FullCPU::OzoneXC OzoneXC;
+ typedef typename FullCPU::OzoneTC OzoneTC;
typedef typename Impl::FullCPU::CommStruct CommStruct;
InorderBackEnd(Params *params);
void setCommBuffer(TimeBuffer<CommStruct> *_comm)
{ comm = _comm; }
- void setXC(ExecContext *xc_ptr);
+ void setTC(ThreadContext *tc_ptr);
void setThreadState(OzoneThreadState<Impl> *thread_ptr);
private:
void handleFault();
- void setSquashInfoFromXC();
+ void setSquashInfoFromTC();
bool squashPending;
InstSeqNum squashSeqNum;
void switchOut() { panic("Not implemented!"); }
void doSwitchOut() { panic("Not implemented!"); }
- void takeOverFrom(ExecContext *old_xc = NULL) { panic("Not implemented!"); }
+ void takeOverFrom(ThreadContext *old_tc = NULL) { panic("Not implemented!"); }
public:
FullCPU *cpu;
FrontEnd *frontEnd;
- ExecContext *xc;
+ ThreadContext *tc;
OzoneThreadState<Impl> *thread;
template <class>
class Checker;
-class ExecContext;
+class ThreadContext;
template <class Impl>
class OzoneThreadState;
void setFrontEnd(FrontEnd *front_end_ptr)
{ frontEnd = front_end_ptr; }
- void setXC(ExecContext *xc_ptr)
- { xc = xc_ptr; }
+ void setTC(ThreadContext *tc_ptr)
+ { tc = tc_ptr; }
void setThreadState(Thread *thread_ptr)
{ thread = thread_ptr; }
void tick();
void squash();
- void generateXCEvent() { xcSquash = true; }
- void squashFromXC();
+ void generateTCEvent() { tcSquash = true; }
+ void squashFromTC();
void squashFromTrap();
void checkInterrupts();
bool trapSquash;
- bool xcSquash;
+ bool tcSquash;
template <class T>
Fault read(RequestPtr req, T &data, int load_idx);
void switchOut();
void doSwitchOut();
- void takeOverFrom(ExecContext *old_xc = NULL);
+ void takeOverFrom(ThreadContext *old_tc = NULL);
bool isSwitchedOut() { return switchedOut; }
FrontEnd *frontEnd;
- ExecContext *xc;
+ ThreadContext *tc;
Thread *thread;
template <class Impl>
LWBackEnd<Impl>::LWBackEnd(Params *params)
: d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
- trapSquash(false), xcSquash(false), cacheCompletionEvent(this),
+ trapSquash(false), tcSquash(false), cacheCompletionEvent(this),
dcacheInterface(params->dcacheInterface), width(params->backEndWidth),
exactFullStall(true)
{
cpu->check_interrupts() &&
!cpu->inPalMode(thread->readPC()) &&
!trapSquash &&
- !xcSquash) {
+ !tcSquash) {
frontEnd->interruptPending = true;
if (robEmpty() && !LSQ.hasStoresToWB()) {
// Will need to squash all instructions currently in flight and have
// Consider holding onto the trap and waiting until the trap event
// happens for this to be executed.
- fault->invoke(thread->getXCProxy());
+ fault->invoke(thread->getTCProxy());
// Exit state update mode to avoid accidental updating.
thread->inSyscall = false;
checkInterrupts();
if (trapSquash) {
- assert(!xcSquash);
+ assert(!tcSquash);
squashFromTrap();
- } else if (xcSquash) {
- squashFromXC();
+ } else if (tcSquash) {
+ squashFromTC();
}
#endif
assert(!thread->inSyscall && !thread->trapPending);
oldpc = thread->readPC();
cpu->system->pcEventQueue.service(
- thread->getXCProxy());
+ thread->getTCProxy());
count++;
} while (oldpc != thread->readPC());
if (count > 1) {
DPRINTF(BE, "PC skip function event, stopping commit\n");
- xcSquash = true;
+ tcSquash = true;
return false;
}
#endif
template <class Impl>
void
-LWBackEnd<Impl>::squashFromXC()
+LWBackEnd<Impl>::squashFromTC()
{
InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
squash(squashed_inst);
thread->trapPending = false;
thread->inSyscall = false;
- xcSquash = false;
+ tcSquash = false;
commitStatus = Running;
}
switchedOut = true;
switchPending = false;
// Need to get rid of all committed, non-speculative state and write it
- // to memory/XC. In this case this is stores that have committed and not
+ // to memory/TC. In this case this is stores that have committed and not
// yet written back.
assert(robEmpty());
assert(!LSQ.hasStoresToWB());
template <class Impl>
void
-LWBackEnd<Impl>::takeOverFrom(ExecContext *old_xc)
+LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_xc)
{
switchedOut = false;
xcSquash = false;
void switchOut();
- void takeOverFrom(ExecContext *old_xc = NULL);
+ void takeOverFrom(ThreadContext *old_tc = NULL);
bool isSwitchedOut() { return switchedOut; }
template <class Impl>
void
-OzoneLWLSQ<Impl>::takeOverFrom(ExecContext *old_xc)
+OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
{
// Clear out any old state. May be redundant if this is the first time
// the CPU is being used.
#include "arch/faults.hh"
#include "arch/isa_traits.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "sim/process.hh"
// has benefits for SMT; basically serves same use as CPUExecContext.
// Makes the ExecContext proxy easier. Gives organization/central access point
// to state of a thread that can be accessed normally (i.e. not in-flight
-// stuff within a OoO processor). Does this need an XC proxy within it?
+// stuff within a OoO processor). Does this need an TC proxy within it?
template <class Impl>
struct OzoneThreadState : public ThreadState {
- typedef typename ExecContext::Status Status;
+ typedef typename ThreadContext::Status Status;
typedef typename Impl::FullCPU FullCPU;
typedef TheISA::MiscReg MiscReg;
bool trapPending;
- ExecContext *xcProxy;
+ ThreadContext *tc;
- ExecContext *getXCProxy() { return xcProxy; }
+ ThreadContext *getTC() { return tc; }
#if !FULL_SYSTEM
Fault translateInstReq(Request *req)
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
- return regs.readMiscRegWithEffect(misc_reg, fault, xcProxy);
+ return regs.readMiscRegWithEffect(misc_reg, fault, tc);
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
- return regs.setMiscRegWithEffect(misc_reg, val, xcProxy);
+ return regs.setMiscRegWithEffect(misc_reg, val, tc);
}
uint64_t readPC()
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/pc_event.hh"
#include "sim/debug.hh"
#include "sim/root.hh"
}
bool
-PCEventQueue::doService(ExecContext *xc)
+PCEventQueue::doService(ThreadContext *tc)
{
- Addr pc = xc->readPC() & ~0x3;
+ Addr pc = tc->readPC() & ~0x3;
int serviced = 0;
range_t range = equal_range(pc);
for (iterator i = range.first; i != range.second; ++i) {
// another event. This for example, prevents two invocations
// of the SkipFuncEvent. Maybe we should have separate PC
// event queues for each processor?
- if (pc != (xc->readPC() & ~0x3))
+ if (pc != (tc->readPC() & ~0x3))
continue;
DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",
(*i)->pc(), (*i)->descr());
- (*i)->process(xc);
+ (*i)->process(tc);
++serviced;
}
}
void
-BreakPCEvent::process(ExecContext *xc)
+BreakPCEvent::process(ThreadContext *tc)
{
- StringWrap name(xc->getCpuPtr()->name() + ".break_event");
+ StringWrap name(tc->getCpuPtr()->name() + ".break_event");
DPRINTFN("break event %s triggered\n", descr());
debug_break();
if (remove)
#include "base/misc.hh"
-class ExecContext;
+class ThreadContext;
class PCEventQueue;
class PCEvent
Addr pc() const { return evpc; }
bool remove();
- virtual void process(ExecContext *xc) = 0;
+ virtual void process(ThreadContext *tc) = 0;
};
class PCEventQueue
protected:
map_t pc_map;
- bool doService(ExecContext *xc);
+ bool doService(ThreadContext *tc);
public:
PCEventQueue();
bool remove(PCEvent *event);
bool schedule(PCEvent *event);
- bool service(ExecContext *xc)
+ bool service(ThreadContext *tc)
{
if (pc_map.empty())
return false;
- return doService(xc);
+ return doService(tc);
}
range_t equal_range(Addr pc);
public:
BreakPCEvent(PCEventQueue *q, const std::string &desc, Addr addr,
bool del = false);
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
#endif // __PC_EVENT_HH__
#include "base/trace.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
using namespace std;
}
void
-FunctionProfile::dump(ExecContext *xc, ostream &os) const
+FunctionProfile::dump(ThreadContext *tc, ostream &os) const
{
ccprintf(os, ">>>PC data\n");
map<Addr, Counter>::const_iterator i, end = pc_count.end();
#include "sim/host.hh"
#include "arch/stacktrace.hh"
-class ExecContext;
+class ThreadContext;
class ProfileNode
{
FunctionProfile(const SymbolTable *symtab);
~FunctionProfile();
- ProfileNode *consume(ExecContext *xc, StaticInstPtr inst);
+ ProfileNode *consume(ThreadContext *tc, StaticInstPtr inst);
ProfileNode *consume(const std::vector<Addr> &stack);
void clear();
- void dump(ExecContext *xc, std::ostream &out) const;
+ void dump(ThreadContext *tc, std::ostream &out) const;
void sample(ProfileNode *node, Addr pc);
};
inline ProfileNode *
-FunctionProfile::consume(ExecContext *xc, StaticInstPtr inst)
+FunctionProfile::consume(ThreadContext *tc, StaticInstPtr inst)
{
- if (!trace.trace(xc, inst))
+ if (!trace.trace(tc, inst))
return NULL;
trace.dprintf();
return consume(trace.getstack());
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/quiesce_event.hh"
-EndQuiesceEvent::EndQuiesceEvent(ExecContext *_xc)
- : Event(&mainEventQueue), xc(_xc)
+EndQuiesceEvent::EndQuiesceEvent(ThreadContext *_tc)
+ : Event(&mainEventQueue), tc(_tc)
{
}
void
EndQuiesceEvent::process()
{
- xc->activate();
+ tc->activate();
}
const char*
#include "sim/eventq.hh"
-class ExecContext;
+class ThreadContext;
/** Event for timing out quiesce instruction */
struct EndQuiesceEvent : public Event
{
- /** A pointer to the execution context that is quiesced */
- ExecContext *xc;
+ /** A pointer to the thread context that is quiesced */
+ ThreadContext *tc;
- EndQuiesceEvent(ExecContext *_xc);
+ EndQuiesceEvent(ThreadContext *_tc);
/** Event process to occur at interrupt*/
virtual void process();
BaseCPU::init();
#if FULL_SYSTEM
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(xc, xc->readCpuId());
+ TheISA::initCPU(tc, tc->readCpuId());
}
#endif
}
assert(!tickEvent.scheduled());
- // if any of this CPU's ExecContexts are active, mark the CPU as
+ // if any of this CPU's ThreadContexts are active, mark the CPU as
// running and schedule its tick event.
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
- if (xc->status() == ExecContext::Active && _status != Running) {
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
+ if (tc->status() == ThreadContext::Active && _status != Running) {
_status = Running;
tickEvent.schedule(curTick);
break;
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/cpu_exec_context.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/profile.hh"
#include "cpu/sampler/sampler.hh"
/* asid */ 0, mem);
#endif // !FULL_SYSTEM
- cpuXC->setStatus(ExecContext::Suspended);
+ cpuXC->setStatus(ThreadContext::Suspended);
- xcProxy = cpuXC->getProxy();
+ tc = cpuXC->getTC();
numInst = 0;
startNumInst = 0;
lastIcacheStall = 0;
lastDcacheStall = 0;
- execContexts.push_back(xcProxy);
+ threadContexts.push_back(tc);
}
BaseSimpleCPU::~BaseSimpleCPU()
Addr
BaseSimpleCPU::dbg_vtophys(Addr addr)
{
- return vtophys(xcProxy, addr);
+ return vtophys(tc, addr);
}
#endif // FULL_SYSTEM
{
BaseCPU::post_interrupt(int_num, index);
- if (cpuXC->status() == ExecContext::Suspended) {
+ if (cpuXC->status() == ThreadContext::Suspended) {
DPRINTF(IPI,"Suspended Processor awoke\n");
cpuXC->activate();
}
cpuXC->setMiscReg(IPR_ISR, summary);
cpuXC->setMiscReg(IPR_INTID, ipl);
- Fault(new InterruptFault)->invoke(xcProxy);
+ Fault(new InterruptFault)->invoke(tc);
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
inst = gtoh(inst);
curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
- traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
+ traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
cpuXC->readPC());
DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
#if FULL_SYSTEM
if (system->kernelBinning->fnbin) {
assert(cpuXC->getKernelStats());
- system->kernelBinning->execute(xcProxy, inst);
+ system->kernelBinning->execute(tc, inst);
}
if (cpuXC->profile) {
bool usermode =
(cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
- ProfileNode *node = cpuXC->profile->consume(xcProxy, inst);
+ ProfileNode *node = cpuXC->profile->consume(tc, inst);
if (node)
cpuXC->profileNode = node;
}
{
if (fault != NoFault) {
#if FULL_SYSTEM
- fault->invoke(xcProxy);
+ fault->invoke(tc);
#else // !FULL_SYSTEM
fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
#endif // FULL_SYSTEM
Addr oldpc;
do {
oldpc = cpuXC->readPC();
- system->pcEventQueue.service(xcProxy);
+ system->pcEventQueue.service(tc);
} while (oldpc != cpuXC->readPC());
#endif
}
#endif // FULL_SYSTEM
-class ExecContext;
+class ThreadContext;
class Checkpoint;
namespace Trace {
// execution context
CPUExecContext *cpuXC;
- ExecContext *xcProxy;
+ ThreadContext *tc;
#if FULL_SYSTEM
Addr dbg_vtophys(Addr addr);
int readIntrFlag() { return cpuXC->readIntrFlag(); }
void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
bool inPalMode() { return cpuXC->inPalMode(); }
- void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
+ void ev5_trap(Fault fault) { fault->invoke(tc); }
bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
#else
void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
#endif
bool misspeculating() { return cpuXC->misspeculating(); }
- ExecContext *xcBase() { return xcProxy; }
+ ThreadContext *tcBase() { return tc; }
};
#endif // __CPU_SIMPLE_BASE_HH__
BaseCPU::init();
#if FULL_SYSTEM
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(xc, xc->readCpuId());
+ TheISA::initCPU(tc, tc->readCpuId());
}
#endif
}
{
BaseCPU::takeOverFrom(oldCPU);
- // if any of this CPU's ExecContexts are active, mark the CPU as
+ // if any of this CPU's ThreadContexts are active, mark the CPU as
// running and schedule its tick event.
- for (int i = 0; i < execContexts.size(); ++i) {
- ExecContext *xc = execContexts[i];
- if (xc->status() == ExecContext::Active && _status != Running) {
+ for (int i = 0; i < threadContexts.size(); ++i) {
+ ThreadContext *tc = threadContexts[i];
+ if (tc->status() == ThreadContext::Active && _status != Running) {
_status = Running;
break;
}
}
bool
-StaticInst::hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const
+StaticInst::hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const
{
if (isDirectCtrl()) {
tgt = branchTarget(pc);
}
if (isIndirectCtrl()) {
- tgt = branchTarget(xc);
+ tgt = branchTarget(tc);
return true;
}
struct AlphaSimpleImpl;
struct OzoneImpl;
struct SimpleImpl;
-class ExecContext;
+class ThreadContext;
class DynInst;
class Packet;
/**
* Return the target address for an indirect branch (jump). The
- * register value is read from the supplied execution context, so
- * the result is valid only if the execution context is about to
+ * register value is read from the supplied thread context, so
+ * the result is valid only if the thread context is about to
* execute the branch in question. Invalid if not an indirect
* branch (i.e. isIndirectCtrl() should be true).
*/
- virtual Addr branchTarget(ExecContext *xc) const
+ virtual Addr branchTarget(ThreadContext *tc) const
{
panic("StaticInst::branchTarget() called on instruction "
"that is not an indirect branch.");
* Return true if the instruction is a control transfer, and if so,
* return the target address as well.
*/
- bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
+ bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const;
/**
* Return string representation of disassembled instruction.
--- /dev/null
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Kevin Lim
+ */
+
+#ifndef __CPU_THREAD_CONTEXT_HH__
+#define __CPU_THREAD_CONTEXT_HH__
+
+#include "config/full_system.hh"
+#include "mem/request.hh"
+#include "sim/faults.hh"
+#include "sim/host.hh"
+#include "sim/serialize.hh"
+#include "sim/byteswap.hh"
+
+// @todo: Figure out a more architecture independent way to obtain the ITB and
+// DTB pointers.
+class AlphaDTB;
+class AlphaITB;
+class BaseCPU;
+class EndQuiesceEvent;
+class Event;
+class TranslatingPort;
+class FunctionalPort;
+class VirtualPort;
+class Process;
+class System;
+namespace Kernel {
+ class Statistics;
+};
+
+/**
+ * ThreadContext is the external interface to all thread state for
+ * anything outside of the CPU. It provides all accessor methods to
+ * state that might be needed by external objects, ranging from
+ * register values to things such as kernel stats. It is an abstract
+ * base class; the CPU can create its own ThreadContext by either
+ * deriving from it, or using the templated ProxyThreadContext.
+ *
+ * The ThreadContext is slightly different than the ExecContext. The
+ * ThreadContext provides access to an individual thread's state; an
+ * ExecContext provides ISA access to the CPU (meaning it is
+ * implicitly multithreaded on MT systems). Additionally the
+ * ThreadState is an abstract class that exactly defines the
+ * interface; the ExecContext is a more implicit interface that must
+ * be implemented so that the ISA can access whatever state it needs.
+ */
+class ThreadContext
+{
+ protected:
+ typedef TheISA::RegFile RegFile;
+ typedef TheISA::MachInst MachInst;
+ typedef TheISA::IntReg IntReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::FloatRegBits FloatRegBits;
+ typedef TheISA::MiscRegFile MiscRegFile;
+ typedef TheISA::MiscReg MiscReg;
+ public:
+ enum Status
+ {
+ /// Initialized but not running yet. All CPUs start in
+ /// this state, but most transition to Active on cycle 1.
+ /// In MP or SMT systems, non-primary contexts will stay
+ /// in this state until a thread is assigned to them.
+ Unallocated,
+
+ /// Running. Instructions should be executed only when
+ /// the context is in this state.
+ Active,
+
+ /// Temporarily inactive. Entered while waiting for
+ /// synchronization, etc.
+ Suspended,
+
+ /// Permanently shut down. Entered when target executes
+ /// m5exit pseudo-instruction. When all contexts enter
+ /// this state, the simulation will terminate.
+ Halted
+ };
+
+ virtual ~ThreadContext() { };
+
+ virtual BaseCPU *getCpuPtr() = 0;
+
+ virtual void setCpuId(int id) = 0;
+
+ virtual int readCpuId() = 0;
+
+#if FULL_SYSTEM
+ virtual System *getSystemPtr() = 0;
+
+ virtual AlphaITB *getITBPtr() = 0;
+
+ virtual AlphaDTB * getDTBPtr() = 0;
+
+ virtual Kernel::Statistics *getKernelStats() = 0;
+
+ virtual FunctionalPort *getPhysPort() = 0;
+
+ virtual VirtualPort *getVirtPort(ThreadContext *tc = NULL) = 0;
+
+ virtual void delVirtPort(VirtualPort *vp) = 0;
+#else
+ virtual TranslatingPort *getMemPort() = 0;
+
+ virtual Process *getProcessPtr() = 0;
+#endif
+
+ virtual Status status() const = 0;
+
+ virtual void setStatus(Status new_status) = 0;
+
+ /// Set the status to Active. Optional delay indicates number of
+ /// cycles to wait before beginning execution.
+ virtual void activate(int delay = 1) = 0;
+
+ /// Set the status to Suspended.
+ virtual void suspend() = 0;
+
+ /// Set the status to Unallocated.
+ virtual void deallocate() = 0;
+
+ /// Set the status to Halted.
+ virtual void halt() = 0;
+
+#if FULL_SYSTEM
+ virtual void dumpFuncProfile() = 0;
+#endif
+
+ virtual void takeOverFrom(ThreadContext *old_context) = 0;
+
+ virtual void regStats(const std::string &name) = 0;
+
+ virtual void serialize(std::ostream &os) = 0;
+ virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
+
+#if FULL_SYSTEM
+ virtual EndQuiesceEvent *getQuiesceEvent() = 0;
+
+ // Not necessarily the best location for these...
+ // Having an extra function just to read these is obnoxious
+ virtual Tick readLastActivate() = 0;
+ virtual Tick readLastSuspend() = 0;
+
+ virtual void profileClear() = 0;
+ virtual void profileSample() = 0;
+#endif
+
+ virtual int getThreadNum() = 0;
+
+ // Also somewhat obnoxious. Really only used for the TLB fault.
+ // However, may be quite useful in SPARC.
+ virtual TheISA::MachInst getInst() = 0;
+
+ virtual void copyArchRegs(ThreadContext *tc) = 0;
+
+ virtual void clearArchRegs() = 0;
+
+ //
+ // New accessors for new decoder.
+ //
+ virtual uint64_t readIntReg(int reg_idx) = 0;
+
+ virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
+
+ virtual FloatReg readFloatReg(int reg_idx) = 0;
+
+ virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
+
+ virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
+
+ virtual void setIntReg(int reg_idx, uint64_t val) = 0;
+
+ virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
+
+ virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
+
+ virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
+
+ virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
+
+ virtual uint64_t readPC() = 0;
+
+ virtual void setPC(uint64_t val) = 0;
+
+ virtual uint64_t readNextPC() = 0;
+
+ virtual void setNextPC(uint64_t val) = 0;
+
+ virtual uint64_t readNextNPC() = 0;
+
+ virtual void setNextNPC(uint64_t val) = 0;
+
+ virtual MiscReg readMiscReg(int misc_reg) = 0;
+
+ virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
+
+ virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
+
+ virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
+
+ // Also not necessarily the best location for these two. Hopefully will go
+ // away once we decide upon where st cond failures goes.
+ virtual unsigned readStCondFailures() = 0;
+
+ virtual void setStCondFailures(unsigned sc_failures) = 0;
+
+#if FULL_SYSTEM
+ virtual bool inPalMode() = 0;
+#endif
+
+ // Only really makes sense for old CPU model. Still could be useful though.
+ virtual bool misspeculating() = 0;
+
+#if !FULL_SYSTEM
+ virtual IntReg getSyscallArg(int i) = 0;
+
+ // used to shift args for indirect syscall
+ virtual void setSyscallArg(int i, IntReg val) = 0;
+
+ virtual void setSyscallReturn(SyscallReturn return_value) = 0;
+
+
+ // Same with st cond failures.
+ virtual Counter readFuncExeInst() = 0;
+#endif
+
+ virtual void changeRegFileContext(RegFile::ContextParam param,
+ RegFile::ContextVal val) = 0;
+};
+
+template <class TC>
+class ProxyThreadContext : public ThreadContext
+{
+ public:
+ ProxyThreadContext(TC *actual_tc)
+ { actualTC = actual_tc; }
+
+ private:
+ TC *actualTC;
+
+ public:
+
+ BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); }
+
+ void setCpuId(int id) { actualTC->setCpuId(id); }
+
+ int readCpuId() { return actualTC->readCpuId(); }
+
+#if FULL_SYSTEM
+ System *getSystemPtr() { return actualTC->getSystemPtr(); }
+
+ AlphaITB *getITBPtr() { return actualTC->getITBPtr(); }
+
+ AlphaDTB *getDTBPtr() { return actualTC->getDTBPtr(); }
+
+ Kernel::Statistics *getKernelStats() { return actualTC->getKernelStats(); }
+
+ FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); }
+
+ VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return actualTC->getVirtPort(tc); }
+
+ void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
+#else
+ TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
+
+ Process *getProcessPtr() { return actualTC->getProcessPtr(); }
+#endif
+
+ Status status() const { return actualTC->status(); }
+
+ void setStatus(Status new_status) { actualTC->setStatus(new_status); }
+
+ /// Set the status to Active. Optional delay indicates number of
+ /// cycles to wait before beginning execution.
+ void activate(int delay = 1) { actualTC->activate(delay); }
+
+ /// Set the status to Suspended.
+ void suspend() { actualTC->suspend(); }
+
+ /// Set the status to Unallocated.
+ void deallocate() { actualTC->deallocate(); }
+
+ /// Set the status to Halted.
+ void halt() { actualTC->halt(); }
+
+#if FULL_SYSTEM
+ void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
+#endif
+
+ void takeOverFrom(ThreadContext *oldContext)
+ { actualTC->takeOverFrom(oldContext); }
+
+ void regStats(const std::string &name) { actualTC->regStats(name); }
+
+ void serialize(std::ostream &os) { actualTC->serialize(os); }
+ void unserialize(Checkpoint *cp, const std::string §ion)
+ { actualTC->unserialize(cp, section); }
+
+#if FULL_SYSTEM
+ EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); }
+
+ Tick readLastActivate() { return actualTC->readLastActivate(); }
+ Tick readLastSuspend() { return actualTC->readLastSuspend(); }
+
+ void profileClear() { return actualTC->profileClear(); }
+ void profileSample() { return actualTC->profileSample(); }
+#endif
+
+ int getThreadNum() { return actualTC->getThreadNum(); }
+
+ // @todo: Do I need this?
+ MachInst getInst() { return actualTC->getInst(); }
+
+ // @todo: Do I need this?
+ void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
+
+ void clearArchRegs() { actualTC->clearArchRegs(); }
+
+ //
+ // New accessors for new decoder.
+ //
+ uint64_t readIntReg(int reg_idx)
+ { return actualTC->readIntReg(reg_idx); }
+
+ FloatReg readFloatReg(int reg_idx, int width)
+ { return actualTC->readFloatReg(reg_idx, width); }
+
+ FloatReg readFloatReg(int reg_idx)
+ { return actualTC->readFloatReg(reg_idx); }
+
+ FloatRegBits readFloatRegBits(int reg_idx, int width)
+ { return actualTC->readFloatRegBits(reg_idx, width); }
+
+ FloatRegBits readFloatRegBits(int reg_idx)
+ { return actualTC->readFloatRegBits(reg_idx); }
+
+ void setIntReg(int reg_idx, uint64_t val)
+ { actualTC->setIntReg(reg_idx, val); }
+
+ void setFloatReg(int reg_idx, FloatReg val, int width)
+ { actualTC->setFloatReg(reg_idx, val, width); }
+
+ void setFloatReg(int reg_idx, FloatReg val)
+ { actualTC->setFloatReg(reg_idx, val); }
+
+ void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
+ { actualTC->setFloatRegBits(reg_idx, val, width); }
+
+ void setFloatRegBits(int reg_idx, FloatRegBits val)
+ { actualTC->setFloatRegBits(reg_idx, val); }
+
+ uint64_t readPC() { return actualTC->readPC(); }
+
+ void setPC(uint64_t val) { actualTC->setPC(val); }
+
+ uint64_t readNextPC() { return actualTC->readNextPC(); }
+
+ void setNextPC(uint64_t val) { actualTC->setNextPC(val); }
+
+ uint64_t readNextNPC() { return actualTC->readNextNPC(); }
+
+ void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
+
+ MiscReg readMiscReg(int misc_reg)
+ { return actualTC->readMiscReg(misc_reg); }
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ { return actualTC->readMiscRegWithEffect(misc_reg, fault); }
+
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ { return actualTC->setMiscReg(misc_reg, val); }
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ { return actualTC->setMiscRegWithEffect(misc_reg, val); }
+
+ unsigned readStCondFailures()
+ { return actualTC->readStCondFailures(); }
+
+ void setStCondFailures(unsigned sc_failures)
+ { actualTC->setStCondFailures(sc_failures); }
+#if FULL_SYSTEM
+ bool inPalMode() { return actualTC->inPalMode(); }
+#endif
+
+ // @todo: Fix this!
+ bool misspeculating() { return actualTC->misspeculating(); }
+
+#if !FULL_SYSTEM
+ IntReg getSyscallArg(int i) { return actualTC->getSyscallArg(i); }
+
+ // used to shift args for indirect syscall
+ void setSyscallArg(int i, IntReg val)
+ { actualTC->setSyscallArg(i, val); }
+
+ void setSyscallReturn(SyscallReturn return_value)
+ { actualTC->setSyscallReturn(return_value); }
+
+
+ Counter readFuncExeInst() { return actualTC->readFuncExeInst(); }
+#endif
+
+ void changeRegFileContext(RegFile::ContextParam param,
+ RegFile::ContextVal val)
+ {
+ actualTC->changeRegFileContext(param, val);
+ }
+};
+
+#endif
#ifndef __CPU_THREAD_STATE_HH__
#define __CPU_THREAD_STATE_HH__
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
#include "mem/translating_port.hh"
#endif
}
- ExecContext::Status status;
+ ThreadContext::Status status;
int cpuId;
#include "base/str.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "dev/alpha_console.hh"
#include "dev/platform.hh"
#include "dev/simconsole.hh"
#include "arch/alpha/ev5.hh"
#include "base/inet.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "dev/etherlink.hh"
#include "dev/ns_gige.hh"
#include "dev/pciconfigall.hh"
#include <string>
#include "base/inet.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "dev/etherlink.hh"
#include "dev/sinic.hh"
#include "dev/tsunamireg.h"
#include "dev/tsunami.hh"
#include "mem/port.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
void
TsunamiCChip::clearIPI(uint64_t ipintr)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (ipintr) {
void
TsunamiCChip::clearITI(uint64_t itintr)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (itintr) {
void
TsunamiCChip::reqIPI(uint64_t ipreq)
{
- int numcpus = tsunami->intrctrl->cpu->system->execContexts.size();
+ int numcpus = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(numcpus <= Tsunami::Max_CPUs);
if (ipreq) {
void
TsunamiCChip::postRTC()
{
- int size = tsunami->intrctrl->cpu->system->execContexts.size();
+ int size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
for (int i = 0; i < size; i++) {
TsunamiCChip::postDRIR(uint32_t interrupt)
{
uint64_t bitvector = ULL(1) << interrupt;
- uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+ uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
drir |= bitvector;
TsunamiCChip::clearDRIR(uint32_t interrupt)
{
uint64_t bitvector = ULL(1) << interrupt;
- uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+ uint64_t size = tsunami->intrctrl->cpu->system->threadContexts.size();
assert(size <= Tsunami::Max_CPUs);
if (drir & bitvector)
#include "arch/alpha/osfpal.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/kernel_stats.hh"
#include "kern/tru64/tru64_syscalls.hh"
#include "sim/system.hh"
}
void
-Statistics::setIdleProcess(Addr idlepcbb, ExecContext *xc)
+Statistics::setIdleProcess(Addr idlepcbb, ThreadContext *tc)
{
assert(themode == kernel || themode == interrupt);
idleProcess = idlepcbb;
themode = idle;
- changeMode(themode, xc);
+ changeMode(themode, tc);
}
void
-Statistics::changeMode(cpu_mode newmode, ExecContext *xc)
+Statistics::changeMode(cpu_mode newmode, ThreadContext *tc)
{
_mode[newmode]++;
_modeGood[newmode]++;
_modeTicks[themode] += curTick - lastModeTick;
- xc->getSystemPtr()->kernelBinning->changeMode(newmode);
+ tc->getSystemPtr()->kernelBinning->changeMode(newmode);
lastModeTick = curTick;
themode = newmode;
}
void
-Statistics::mode(cpu_mode newmode, ExecContext *xc)
+Statistics::mode(cpu_mode newmode, ThreadContext *tc)
{
- Addr pcbb = xc->readMiscReg(AlphaISA::IPR_PALtemp23);
+ Addr pcbb = tc->readMiscReg(AlphaISA::IPR_PALtemp23);
if ((newmode == kernel || newmode == interrupt) &&
pcbb == idleProcess)
if (bin_int == false && newmode == interrupt)
newmode = kernel;
- changeMode(newmode, xc);
+ changeMode(newmode, tc);
}
void
-Statistics::context(Addr oldpcbb, Addr newpcbb, ExecContext *xc)
+Statistics::context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc)
{
assert(themode != user);
_swap_context++;
- changeMode(newpcbb == idleProcess ? idle : kernel, xc);
+ changeMode(newpcbb == idleProcess ? idle : kernel, tc);
}
void
-Statistics::callpal(int code, ExecContext *xc)
+Statistics::callpal(int code, ThreadContext *tc)
{
if (!PAL::name(code))
return;
switch (code) {
case PAL::callsys: {
- int number = xc->readIntReg(0);
+ int number = tc->readIntReg(0);
if (SystemCalls<Tru64>::validSyscallNumber(number)) {
int cvtnum = SystemCalls<Tru64>::convert(number);
_syscall[cvtnum]++;
} break;
case PAL::swpctx:
- if (xc->getSystemPtr()->kernelBinning)
- xc->getSystemPtr()->kernelBinning->palSwapContext(xc);
+ if (tc->getSystemPtr()->kernelBinning)
+ tc->getSystemPtr()->kernelBinning->palSwapContext(tc);
break;
}
}
#include "cpu/static_inst.hh"
class BaseCPU;
-class ExecContext;
+class ThreadContext;
class FnEvent;
// What does kernel stats expect is included?
class System;
const bool fnbin;
cpu_mode themode;
- void palSwapContext(ExecContext *xc);
- void execute(ExecContext *xc, StaticInstPtr inst);
- void call(ExecContext *xc, Stats::MainBin *myBin);
+ void palSwapContext(ThreadContext *tc);
+ void execute(ThreadContext *tc, StaticInstPtr inst);
+ void call(ThreadContext *tc, Stats::MainBin *myBin);
void changeMode(cpu_mode mode);
public:
Tick lastModeTick;
bool bin_int;
- void changeMode(cpu_mode newmode, ExecContext *xc);
+ void changeMode(cpu_mode newmode, ThreadContext *tc);
private:
Stats::Scalar<> _arm;
void ivle() { _ivle++; }
void hwrei() { _hwrei++; }
void swpipl(int ipl);
- void mode(cpu_mode newmode, ExecContext *xc);
- void context(Addr oldpcbb, Addr newpcbb, ExecContext *xc);
- void callpal(int code, ExecContext *xc);
+ void mode(cpu_mode newmode, ThreadContext *tc);
+ void context(Addr oldpcbb, Addr newpcbb, ThreadContext *tc);
+ void callpal(int code, ThreadContext *tc);
- void setIdleProcess(Addr idle, ExecContext *xc);
+ void setIdleProcess(Addr idle, ThreadContext *tc);
public:
virtual void serialize(std::ostream &os);
#include "arch/arguments.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
#include "kern/system_events.hh"
namespace Linux {
void
-DebugPrintkEvent::process(ExecContext *xc)
+DebugPrintkEvent::process(ThreadContext *tc)
{
if (DTRACE(DebugPrintf)) {
if (!raw) {
- StringWrap name(xc->getSystemPtr()->name() + ".dprintk");
+ StringWrap name(tc->getSystemPtr()->name() + ".dprintk");
DPRINTFN("");
}
- AlphaISA::AlphaArguments args(xc);
+ AlphaISA::AlphaArguments args(tc);
Printk(args);
- SkipFuncEvent::process(xc);
+ SkipFuncEvent::process(tc);
}
}
DebugPrintkEvent(PCEventQueue *q, const std::string &desc, Addr addr,
bool r = false)
: SkipFuncEvent(q, desc, addr), raw(r) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *xc);
};
}
using namespace TheISA;
void
-SkipFuncEvent::process(ExecContext *xc)
+SkipFuncEvent::process(ThreadContext *tc)
{
- Addr newpc = xc->readIntReg(ReturnAddressReg);
+ Addr newpc = tc->readIntReg(ReturnAddressReg);
DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
- xc->readPC(), newpc);
+ tc->readPC(), newpc);
- xc->setPC(newpc);
- xc->setNextPC(xc->readPC() + sizeof(TheISA::MachInst));
+ tc->setPC(newpc);
+ tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst));
/*
- BranchPred *bp = xc->getCpuPtr()->getBranchPred();
+ BranchPred *bp = tc->getCpuPtr()->getBranchPred();
if (bp != NULL) {
- bp->popRAS(xc->getThreadNum());
+ bp->popRAS(tc->getThreadNum());
}
*/
}
}
void
-FnEvent::process(ExecContext *xc)
+FnEvent::process(ThreadContext *tc)
{
- if (xc->misspeculating())
+ if (tc->misspeculating())
return;
- xc->getSystemPtr()->kernelBinning->call(xc, mybin);
+ tc->getSystemPtr()->kernelBinning->call(tc, mybin);
}
void
-IdleStartEvent::process(ExecContext *xc)
+IdleStartEvent::process(ThreadContext *tc)
{
- if (xc->getKernelStats())
- xc->getKernelStats()->setIdleProcess(
- xc->readMiscReg(AlphaISA::IPR_PALtemp23), xc);
+ if (tc->getKernelStats())
+ tc->getKernelStats()->setIdleProcess(
+ tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
remove();
}
void
-InterruptStartEvent::process(ExecContext *xc)
+InterruptStartEvent::process(ThreadContext *tc)
{
- if (xc->getKernelStats())
- xc->getKernelStats()->mode(Kernel::interrupt, xc);
+ if (tc->getKernelStats())
+ tc->getKernelStats()->mode(Kernel::interrupt, tc);
}
void
-InterruptEndEvent::process(ExecContext *xc)
+InterruptEndEvent::process(ThreadContext *tc)
{
// We go back to kernel, if we are user, inside the rti
// pal code we will get switched to user because of the ICM write
- if (xc->getKernelStats())
- xc->getKernelStats()->mode(Kernel::kernel, xc);
+ if (tc->getKernelStats())
+ tc->getKernelStats()->mode(Kernel::kernel, tc);
}
SkipFuncEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr)
{}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
class FnEvent : public PCEvent
public:
FnEvent(PCEventQueue *q, const std::string &desc, Addr addr,
Stats::MainBin *bin);
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
std::string myname() const { return _name; }
private:
IdleStartEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr)
{}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
class InterruptStartEvent : public PCEvent
InterruptStartEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr)
{}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
class InterruptEndEvent : public PCEvent
InterruptEndEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr)
{}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "base/loader/symtab.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "kern/tru64/mbuf.hh"
#include "sim/host.hh"
#include "sim/system.hh"
void
DumpMbuf(AlphaArguments args)
{
- ExecContext *xc = args.getExecContext();
+ ThreadContext *tc = args.getThreadContext();
Addr addr = (Addr)args;
struct mbuf m;
- CopyOut(xc, &m, addr, sizeof(m));
+ CopyOut(tc, &m, addr, sizeof(m));
int count = m.m_pkthdr.len;
ccprintf(DebugOut(), "m=%#lx, m->m_data=%#lx, m->m_len=%d\n",
addr, m.m_data, m.m_len);
char *buffer = new char[m.m_len];
- CopyOut(xc, buffer, m.m_data, m.m_len);
- Trace::dataDump(curTick, xc->getSystemPtr()->name(), (uint8_t *)buffer,
+ CopyOut(tc, buffer, m.m_data, m.m_len);
+ Trace::dataDump(curTick, tc->getSystemPtr()->name(), (uint8_t *)buffer,
m.m_len);
delete [] buffer;
if (!m.m_next)
break;
- CopyOut(xc, &m, m.m_next, sizeof(m));
+ CopyOut(tc, &m, m.m_next, sizeof(m));
}
}
/// Target getdirentries() handler.
static SyscallReturn
getdirentriesFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace TheISA;
#ifdef __CYGWIN__
panic("getdirent not implemented on cygwin!");
#else
- int fd = process->sim_fd(xc->getSyscallArg(0));
- Addr tgt_buf = xc->getSyscallArg(1);
- int tgt_nbytes = xc->getSyscallArg(2);
- Addr tgt_basep = xc->getSyscallArg(3);
+ int fd = process->sim_fd(tc->getSyscallArg(0));
+ Addr tgt_buf = tc->getSyscallArg(1);
+ int tgt_nbytes = tc->getSyscallArg(2);
+ Addr tgt_basep = tc->getSyscallArg(3);
char * const host_buf = new char[tgt_nbytes];
// just pass basep through uninterpreted.
TypedBufferArg<int64_t> basep(tgt_basep);
- basep.copyIn(xc->getMemPort());
+ basep.copyIn(tc->getMemPort());
long host_basep = (off_t)htog((int64_t)*basep);
int host_result = getdirentries(fd, host_buf, tgt_nbytes, &host_basep);
tgt_dp->d_reclen = tgt_bufsize;
tgt_dp->d_namlen = namelen;
strcpy(tgt_dp->d_name, host_dp->d_name);
- tgt_dp.copyOut(xc->getMemPort());
+ tgt_dp.copyOut(tc->getMemPort());
tgt_buf_ptr += tgt_bufsize;
host_buf_ptr += host_dp->d_reclen;
delete [] host_buf;
*basep = htog((int64_t)host_basep);
- basep.copyOut(xc->getMemPort());
+ basep.copyOut(tc->getMemPort());
return tgt_buf_ptr - tgt_buf;
#endif
/// Target sigreturn() handler.
static SyscallReturn
sigreturnFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace TheISA;
using TheISA::RegFile;
- TypedBufferArg<Tru64::sigcontext> sc(xc->getSyscallArg(0));
+ TypedBufferArg<Tru64::sigcontext> sc(tc->getSyscallArg(0));
- sc.copyIn(xc->getMemPort());
+ sc.copyIn(tc->getMemPort());
// Restore state from sigcontext structure.
// Note that we'll advance PC <- NPC before the end of the cycle,
// so we need to restore the desired PC into NPC.
// The current regs->pc will get clobbered.
- xc->setNextPC(htog(sc->sc_pc));
+ tc->setNextPC(htog(sc->sc_pc));
for (int i = 0; i < 31; ++i) {
- xc->setIntReg(i, htog(sc->sc_regs[i]));
- xc->setFloatRegBits(i, htog(sc->sc_fpregs[i]));
+ tc->setIntReg(i, htog(sc->sc_regs[i]));
+ tc->setFloatRegBits(i, htog(sc->sc_fpregs[i]));
}
- xc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr));
+ tc->setMiscReg(TheISA::Fpcr_DepTag, htog(sc->sc_fpcr));
return 0;
}
/// Create a stack region for a thread.
static SyscallReturn
stack_createFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace TheISA;
- TypedBufferArg<Tru64::vm_stack> argp(xc->getSyscallArg(0));
+ TypedBufferArg<Tru64::vm_stack> argp(tc->getSyscallArg(0));
- argp.copyIn(xc->getMemPort());
+ argp.copyIn(tc->getMemPort());
// if the user chose an address, just let them have it. Otherwise
// pick one for them.
int stack_size = (htog(argp->rsize) + htog(argp->ysize) +
htog(argp->gsize));
process->next_thread_stack_base -= stack_size;
- argp.copyOut(xc->getMemPort());
+ argp.copyOut(tc->getMemPort());
}
return 0;
/// region has several structs, some global, some per-RAD, some per-VP.
static SyscallReturn
nxm_task_initFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace std;
using namespace TheISA;
- TypedBufferArg<Tru64::nxm_task_attr> attrp(xc->getSyscallArg(0));
- TypedBufferArg<Addr> configptr_ptr(xc->getSyscallArg(1));
+ TypedBufferArg<Tru64::nxm_task_attr> attrp(tc->getSyscallArg(0));
+ TypedBufferArg<Addr> configptr_ptr(tc->getSyscallArg(1));
- attrp.copyIn(xc->getMemPort());
+ attrp.copyIn(tc->getMemPort());
if (gtoh(attrp->nxm_version) != NXM_LIB_VERSION) {
cerr << "nxm_task_init: thread library version mismatch! "
config->nxm_slot_state = htog(slot_state_addr);
config->nxm_rad[0] = htog(rad_state_addr);
- config.copyOut(xc->getMemPort());
+ config.copyOut(tc->getMemPort());
// initialize the slot_state array and copy it out
TypedBufferArg<Tru64::nxm_slot_state_t> slot_state(slot_state_addr,
(i == 0) ? Tru64::NXM_SLOT_BOUND : Tru64::NXM_SLOT_AVAIL;
}
- slot_state.copyOut(xc->getMemPort());
+ slot_state.copyOut(tc->getMemPort());
// same for the per-RAD "shared" struct. Note that we need to
// allocate extra bytes for the per-VP array which is embedded at
ssp->nxm_sysevent = htog(0);
if (i == 0) {
- uint64_t uniq = xc->readMiscReg(TheISA::Uniq_DepTag);
+ uint64_t uniq = tc->readMiscReg(TheISA::Uniq_DepTag);
ssp->nxm_u.pth_id = htog(uniq + gtoh(attrp->nxm_uniq_offset));
ssp->nxm_u.nxm_active = htog(uniq | 1);
}
}
}
- rad_state.copyOut(xc->getMemPort());
+ rad_state.copyOut(tc->getMemPort());
//
// copy pointer to shared config area out to user
//
*configptr_ptr = htog(config_addr);
- configptr_ptr.copyOut(xc->getMemPort());
+ configptr_ptr.copyOut(tc->getMemPort());
// Register this as a valid address range with the process
process->nxm_start = base_addr;
return 0;
}
- /// Initialize execution context.
+ /// Initialize thread context.
static void
- init_exec_context(ExecContext *ec,
+ init_thread_context(ThreadContext *tc,
Tru64::nxm_thread_attr *attrp, uint64_t uniq_val)
{
using namespace TheISA;
- ec->clearArchRegs();
+ tc->clearArchRegs();
- ec->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0));
- ec->setIntReg(27/*t12*/, gtoh(attrp->registers.pc));
- ec->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp));
- ec->setMiscReg(TheISA::Uniq_DepTag, uniq_val);
+ tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0));
+ tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc));
+ tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp));
+ tc->setMiscReg(TheISA::Uniq_DepTag, uniq_val);
- ec->setPC(gtoh(attrp->registers.pc));
- ec->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst));
+ tc->setPC(gtoh(attrp->registers.pc));
+ tc->setNextPC(gtoh(attrp->registers.pc) + sizeof(TheISA::MachInst));
- ec->activate();
+ tc->activate();
}
/// Create thread.
static SyscallReturn
nxm_thread_createFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace std;
using namespace TheISA;
- TypedBufferArg<Tru64::nxm_thread_attr> attrp(xc->getSyscallArg(0));
- TypedBufferArg<uint64_t> kidp(xc->getSyscallArg(1));
- int thread_index = xc->getSyscallArg(2);
+ TypedBufferArg<Tru64::nxm_thread_attr> attrp(tc->getSyscallArg(0));
+ TypedBufferArg<uint64_t> kidp(tc->getSyscallArg(1));
+ int thread_index = tc->getSyscallArg(2);
// get attribute args
- attrp.copyIn(xc->getMemPort());
+ attrp.copyIn(tc->getMemPort());
if (gtoh(attrp->version) != NXM_LIB_VERSION) {
cerr << "nxm_thread_create: thread library version mismatch! "
TypedBufferArg<Tru64::nxm_shared> rad_state(0x14000,
rad_state_size);
- rad_state.copyIn(xc->getMemPort());
+ rad_state.copyIn(tc->getMemPort());
uint64_t uniq_val = gtoh(attrp->pthid) - gtoh(rad_state->nxm_uniq_offset);
// This is supposed to be a port number. Make something up.
*kidp = htog(99);
- kidp.copyOut(xc->getMemPort());
+ kidp.copyOut(tc->getMemPort());
return 0;
} else if (gtoh(attrp->type) == Tru64::NXM_TYPE_VP) {
ssp->nxm_u.pth_id = attrp->pthid;
ssp->nxm_u.nxm_active = htog(uniq_val | 1);
- rad_state.copyOut(xc->getMemPort());
+ rad_state.copyOut(tc->getMemPort());
Addr slot_state_addr = 0x12000 + sizeof(Tru64::nxm_config_info);
int slot_state_size =
slot_state(slot_state_addr,
slot_state_size);
- slot_state.copyIn(xc->getMemPort());
+ slot_state.copyIn(tc->getMemPort());
if (slot_state[thread_index] != Tru64::NXM_SLOT_AVAIL) {
cerr << "nxm_thread_createFunc: requested VP slot "
// doesn't work anyway
slot_state[thread_index] = Tru64::NXM_SLOT_BOUND;
- slot_state.copyOut(xc->getMemPort());
+ slot_state.copyOut(tc->getMemPort());
- // Find a free simulator execution context.
+ // Find a free simulator thread context.
for (int i = 0; i < process->numCpus(); ++i) {
- ExecContext *xc = process->execContexts[i];
+ ThreadContext *tc = process->threadContexts[i];
- if (xc->status() == ExecContext::Suspended) {
+ if (tc->status() == ThreadContext::Suspended) {
// inactive context... grab it
- init_exec_context(xc, attrp, uniq_val);
+ init_thread_context(tc, attrp, uniq_val);
// This is supposed to be a port number, but we'll try
// and get away with just sticking the thread index
// here.
*kidp = htog(thread_index);
- kidp.copyOut(xc->getMemPort());
+ kidp.copyOut(tc->getMemPort());
return 0;
}
/// Thread idle call (like yield()).
static SyscallReturn
nxm_idleFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
return 0;
}
/// Block thread.
static SyscallReturn
nxm_thread_blockFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace std;
- uint64_t tid = xc->getSyscallArg(0);
- uint64_t secs = xc->getSyscallArg(1);
- uint64_t flags = xc->getSyscallArg(2);
- uint64_t action = xc->getSyscallArg(3);
- uint64_t usecs = xc->getSyscallArg(4);
+ uint64_t tid = tc->getSyscallArg(0);
+ uint64_t secs = tc->getSyscallArg(1);
+ uint64_t flags = tc->getSyscallArg(2);
+ uint64_t action = tc->getSyscallArg(3);
+ uint64_t usecs = tc->getSyscallArg(4);
- cout << xc->getCpuPtr()->name() << ": nxm_thread_block " << tid << " "
+ cout << tc->getCpuPtr()->name() << ": nxm_thread_block " << tid << " "
<< secs << " " << flags << " " << action << " " << usecs << endl;
return 0;
/// block.
static SyscallReturn
nxm_blockFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace std;
- Addr uaddr = xc->getSyscallArg(0);
- uint64_t val = xc->getSyscallArg(1);
- uint64_t secs = xc->getSyscallArg(2);
- uint64_t usecs = xc->getSyscallArg(3);
- uint64_t flags = xc->getSyscallArg(4);
+ Addr uaddr = tc->getSyscallArg(0);
+ uint64_t val = tc->getSyscallArg(1);
+ uint64_t secs = tc->getSyscallArg(2);
+ uint64_t usecs = tc->getSyscallArg(3);
+ uint64_t flags = tc->getSyscallArg(4);
- BaseCPU *cpu = xc->getCpuPtr();
+ BaseCPU *cpu = tc->getCpuPtr();
cout << cpu->name() << ": nxm_block "
<< hex << uaddr << dec << " " << val
/// Unblock thread.
static SyscallReturn
nxm_unblockFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace std;
- Addr uaddr = xc->getSyscallArg(0);
+ Addr uaddr = tc->getSyscallArg(0);
- cout << xc->getCpuPtr()->name() << ": nxm_unblock "
+ cout << tc->getCpuPtr()->name() << ": nxm_unblock "
<< hex << uaddr << dec << endl;
return 0;
/// Switch thread priority.
static SyscallReturn
swtch_priFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
// Attempts to switch to another runnable thread (if there is
// one). Returns false if there are no other threads to run
}
- /// Activate exec context waiting on a channel. Just activate one
+ /// Activate thread context waiting on a channel. Just activate one
/// by default.
static int
activate_waiting_context(Addr uaddr, Process *process,
while (i != end && (num_activated == 0 || activate_all)) {
if (i->waitChan == uaddr) {
// found waiting process: make it active
- ExecContext *newCtx = i->waitingContext;
- assert(newCtx->status() == ExecContext::Suspended);
+ ThreadContext *newCtx = i->waitingContext;
+ assert(newCtx->status() == ThreadContext::Suspended);
newCtx->activate();
// get rid of this record
/// M5 hacked-up lock acquire.
static void
- m5_lock_mutex(Addr uaddr, Process *process, ExecContext *xc)
+ m5_lock_mutex(Addr uaddr, Process *process, ThreadContext *tc)
{
using namespace TheISA;
TypedBufferArg<uint64_t> lockp(uaddr);
- lockp.copyIn(xc->getMemPort());
+ lockp.copyIn(tc->getMemPort());
if (gtoh(*lockp) == 0) {
// lock is free: grab it
*lockp = htog(1);
- lockp.copyOut(xc->getMemPort());
+ lockp.copyOut(tc->getMemPort());
} else {
// lock is busy: disable until free
- process->waitList.push_back(Process::WaitRec(uaddr, xc));
- xc->suspend();
+ process->waitList.push_back(Process::WaitRec(uaddr, tc));
+ tc->suspend();
}
}
/// M5 unlock call.
static void
- m5_unlock_mutex(Addr uaddr, Process *process, ExecContext *xc)
+ m5_unlock_mutex(Addr uaddr, Process *process, ThreadContext *tc)
{
TypedBufferArg<uint64_t> lockp(uaddr);
- lockp.copyIn(xc->getMemPort());
+ lockp.copyIn(tc->getMemPort());
assert(*lockp != 0);
// Check for a process waiting on the lock.
// clear lock field if no waiting context is taking over the lock
if (num_waiting == 0) {
*lockp = 0;
- lockp.copyOut(xc->getMemPort());
+ lockp.copyOut(tc->getMemPort());
}
}
/// Lock acquire syscall handler.
static SyscallReturn
m5_mutex_lockFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- Addr uaddr = xc->getSyscallArg(0);
+ Addr uaddr = tc->getSyscallArg(0);
- m5_lock_mutex(uaddr, process, xc);
+ m5_lock_mutex(uaddr, process, tc);
// Return 0 since we will always return to the user with the lock
// acquired. We will just keep the context inactive until that is
/// Try lock (non-blocking).
static SyscallReturn
m5_mutex_trylockFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace TheISA;
- Addr uaddr = xc->getSyscallArg(0);
+ Addr uaddr = tc->getSyscallArg(0);
TypedBufferArg<uint64_t> lockp(uaddr);
- lockp.copyIn(xc->getMemPort());
+ lockp.copyIn(tc->getMemPort());
if (gtoh(*lockp) == 0) {
// lock is free: grab it
*lockp = htog(1);
- lockp.copyOut(xc->getMemPort());
+ lockp.copyOut(tc->getMemPort());
return 0;
} else {
return 1;
/// Unlock syscall handler.
static SyscallReturn
m5_mutex_unlockFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- Addr uaddr = xc->getSyscallArg(0);
+ Addr uaddr = tc->getSyscallArg(0);
- m5_unlock_mutex(uaddr, process, xc);
+ m5_unlock_mutex(uaddr, process, tc);
return 0;
}
/// Signal ocndition.
static SyscallReturn
m5_cond_signalFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- Addr cond_addr = xc->getSyscallArg(0);
+ Addr cond_addr = tc->getSyscallArg(0);
// Wake up one process waiting on the condition variable.
activate_waiting_context(cond_addr, process);
/// Wake up all processes waiting on the condition variable.
static SyscallReturn
m5_cond_broadcastFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- Addr cond_addr = xc->getSyscallArg(0);
+ Addr cond_addr = tc->getSyscallArg(0);
activate_waiting_context(cond_addr, process, true);
/// Wait on a condition.
static SyscallReturn
m5_cond_waitFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
using namespace TheISA;
- Addr cond_addr = xc->getSyscallArg(0);
- Addr lock_addr = xc->getSyscallArg(1);
+ Addr cond_addr = tc->getSyscallArg(0);
+ Addr lock_addr = tc->getSyscallArg(1);
TypedBufferArg<uint64_t> condp(cond_addr);
TypedBufferArg<uint64_t> lockp(lock_addr);
// user is supposed to acquire lock before entering
- lockp.copyIn(xc->getMemPort());
+ lockp.copyIn(tc->getMemPort());
assert(gtoh(*lockp) != 0);
- m5_unlock_mutex(lock_addr, process, xc);
+ m5_unlock_mutex(lock_addr, process, tc);
- process->waitList.push_back(Process::WaitRec(cond_addr, xc));
- xc->suspend();
+ process->waitList.push_back(Process::WaitRec(cond_addr, tc));
+ tc->suspend();
return 0;
}
/// Thread exit.
static SyscallReturn
m5_thread_exitFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- assert(xc->status() == ExecContext::Active);
- xc->deallocate();
+ assert(tc->status() == ThreadContext::Active);
+ tc->deallocate();
return 0;
}
/// Indirect syscall invocation (call #0).
static SyscallReturn
indirectSyscallFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int new_callnum = xc->getSyscallArg(0);
+ int new_callnum = tc->getSyscallArg(0);
LiveProcess *lp = dynamic_cast<LiveProcess*>(process);
assert(lp);
for (int i = 0; i < 5; ++i)
- xc->setSyscallArg(i, xc->getSyscallArg(i+1));
+ tc->setSyscallArg(i, tc->getSyscallArg(i+1));
SyscallDesc *new_desc = lp->getDesc(new_callnum);
if (desc == NULL)
fatal("Syscall %d out of range", callnum);
- new_desc->doSyscall(new_callnum, process, xc);
+ new_desc->doSyscall(new_callnum, process, tc);
return 0;
}
* Lisa Hsu
*/
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "kern/system_events.hh"
#include "kern/tru64/tru64_events.hh"
using namespace TheISA;
-//void SkipFuncEvent::process(ExecContext *xc);
+//void SkipFuncEvent::process(ExecContext *tc);
void
-BadAddrEvent::process(ExecContext *xc)
+BadAddrEvent::process(ThreadContext *tc)
{
// The following gross hack is the equivalent function to the
// annotation for vmunix::badaddr in:
// simos/simulation/apps/tcl/osf/tlaser.tcl
- uint64_t a0 = xc->readIntReg(ArgumentReg0);
+ uint64_t a0 = tc->readIntReg(ArgumentReg0);
AddrRangeList resp;
AddrRangeList snoop;
AddrRangeIter iter;
bool found = false;
- xc->getPhysPort()->getPeerAddressRanges(resp, snoop);
+ tc->getPhysPort()->getPeerAddressRanges(resp, snoop);
for(iter = resp.begin(); iter != resp.end(); iter++)
{
if (*iter == (TheISA::K0Seg2Phys(a0) & EV5::PAddrImplMask))
if (!TheISA::IsK0Seg(a0) || found ) {
DPRINTF(BADADDR, "badaddr arg=%#x bad\n", a0);
- xc->setIntReg(ReturnValueReg, 0x1);
- SkipFuncEvent::process(xc);
+ tc->setIntReg(ReturnValueReg, 0x1);
+ SkipFuncEvent::process(tc);
}
else
DPRINTF(BADADDR, "badaddr arg=%#x good\n", a0);
}
void
-PrintfEvent::process(ExecContext *xc)
+PrintfEvent::process(ThreadContext *tc)
{
if (DTRACE(Printf)) {
- DebugOut() << curTick << ": " << xc->getCpuPtr()->name() << ": ";
+ DebugOut() << curTick << ": " << tc->getCpuPtr()->name() << ": ";
- AlphaArguments args(xc);
+ AlphaArguments args(tc);
tru64::Printf(args);
}
}
void
-DebugPrintfEvent::process(ExecContext *xc)
+DebugPrintfEvent::process(ThreadContext *tc)
{
if (DTRACE(DebugPrintf)) {
if (!raw)
- DebugOut() << curTick << ": " << xc->getCpuPtr()->name() << ": ";
+ DebugOut() << curTick << ": " << tc->getCpuPtr()->name() << ": ";
- AlphaArguments args(xc);
+ AlphaArguments args(tc);
tru64::Printf(args);
}
}
void
-DumpMbufEvent::process(ExecContext *xc)
+DumpMbufEvent::process(ThreadContext *tc)
{
if (DTRACE(DebugPrintf)) {
- AlphaArguments args(xc);
+ AlphaArguments args(tc);
tru64::DumpMbuf(args);
}
}
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
-class ExecContext;
+class ThreadContext;
class BadAddrEvent : public SkipFuncEvent
{
public:
BadAddrEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: SkipFuncEvent(q, desc, addr) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
class PrintfEvent : public PCEvent
public:
PrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
class DebugPrintfEvent : public PCEvent
DebugPrintfEvent(PCEventQueue *q, const std::string &desc, Addr addr,
bool r = false)
: PCEvent(q, desc, addr), raw(r) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
class DebugPrintfrEvent : public DebugPrintfEvent
public:
DumpMbufEvent(PCEventQueue *q, const std::string &desc, Addr addr)
: PCEvent(q, desc, addr) {}
- virtual void process(ExecContext *xc);
+ virtual void process(ThreadContext *tc);
};
#endif // __TRU64_EVENTS_HH__
for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
gen.next())
{
- if (xc)
- paddr = TheISA::vtophys(xc,gen.addr());
+ if (tc)
+ paddr = TheISA::vtophys(tc,gen.addr());
else
paddr = TheISA::vtophys(gen.addr());
for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
gen.next())
{
- if (xc)
- paddr = TheISA::vtophys(xc,gen.addr());
+ if (tc)
+ paddr = TheISA::vtophys(tc,gen.addr());
else
paddr = TheISA::vtophys(gen.addr());
/** A class that translates a virtual address to a physical address and then
- * calls the above read/write functions. If an execution context is provided the
+ * calls the above read/write functions. If a thread context is provided the
* address can alway be translated, If not it can only be translated if it is a
* simple address masking operation (such as alpha super page accesses).
*/
class VirtualPort : public FunctionalPort
{
private:
- ExecContext *xc;
+ ThreadContext *tc;
public:
- VirtualPort(const std::string &_name, ExecContext *_xc = NULL)
- : FunctionalPort(_name), xc(_xc)
+ VirtualPort(const std::string &_name, ThreadContext *_tc = NULL)
+ : FunctionalPort(_name), tc(_tc)
{}
- /** Return true if we have an exec context. This is used to prevent someone
- * from accidently deleting the cpus statically allocated vport.
- * @return true if an execution context isn't valid
+ /** Return true if we have an thread context. This is used to
+ * prevent someone from accidently deleting the cpus statically
+ * allocated vport.
+ * @return true if a thread context isn't valid
*/
- bool nullExecContext() { return xc != NULL; }
+ bool nullThreadContext() { return tc != NULL; }
/** Version of readblob that translates virt->phys and deals
* with page boundries. */
#include "base/misc.hh"
#include "sim/faults.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#if !FULL_SYSTEM
-void FaultBase::invoke(ExecContext * xc)
+void FaultBase::invoke(ThreadContext * tc)
{
- fatal("fault (%s) detected @ PC 0x%08p", name(), xc->readPC());
+ fatal("fault (%s) detected @ PC 0x%08p", name(), tc->readPC());
}
#else
-void FaultBase::invoke(ExecContext * xc)
+void FaultBase::invoke(ThreadContext * tc)
{
- DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), xc->readPC());
- xc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
+ DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), tc->readPC());
+ tc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
- assert(!xc->misspeculating());
+ assert(!tc->misspeculating());
}
#endif
-void UnimpFault::invoke(ExecContext * xc)
+void UnimpFault::invoke(ThreadContext * tc)
{
panic("Unimpfault: %s\n", panicStr.c_str());
}
#include "sim/stats.hh"
#include "config/full_system.hh"
-class ExecContext;
+class ThreadContext;
class FaultBase;
typedef RefCountingPtr<FaultBase> Fault;
public:
virtual FaultName name() = 0;
#if FULL_SYSTEM
- virtual void invoke(ExecContext * xc);
+ virtual void invoke(ThreadContext * tc);
#else
- virtual void invoke(ExecContext * xc);
+ virtual void invoke(ThreadContext * tc);
#endif
// template<typename T>
// bool isA() {return dynamic_cast<T *>(this);}
{ }
FaultName name() {return "Unimplemented simulator feature";}
- void invoke(ExecContext * xc);
+ void invoke(ThreadContext * tc);
};
#endif // __FAULTS_HH__
#include "base/loader/symtab.hh"
#include "base/statistics.hh"
#include "config/full_system.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "mem/physical.hh"
#include "mem/translating_port.hh"
int
-Process::registerExecContext(ExecContext *xc)
+Process::registerThreadContext(ThreadContext *tc)
{
// add to list
- int myIndex = execContexts.size();
- execContexts.push_back(xc);
+ int myIndex = threadContexts.size();
+ threadContexts.push_back(tc);
// return CPU number to caller
return myIndex;
void
Process::startup()
{
- if (execContexts.empty())
+ if (threadContexts.empty())
fatal("Process %s is not associated with any CPUs!\n", name());
- // first exec context for this process... initialize & enable
- ExecContext *xc = execContexts[0];
+ // first thread context for this process... initialize & enable
+ ThreadContext *tc = threadContexts[0];
// mark this context as active so it will start ticking.
- xc->activate(0);
+ tc->activate(0);
Port *mem_port;
mem_port = system->physmem->getPort("functional");
}
void
-Process::replaceExecContext(ExecContext *xc, int xcIndex)
+Process::replaceThreadContext(ThreadContext *tc, int tcIndex)
{
- if (xcIndex >= execContexts.size()) {
- panic("replaceExecContext: bad xcIndex, %d >= %d\n",
- xcIndex, execContexts.size());
+ if (tcIndex >= threadContexts.size()) {
+ panic("replaceThreadContext: bad tcIndex, %d >= %d\n",
+ tcIndex, threadContexts.size());
}
- execContexts[xcIndex] = xc;
+ threadContexts[tcIndex] = tc;
}
// map simulator fd sim_fd to target fd tgt_fd
copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
- execContexts[0]->setIntReg(ArgumentReg0, argc);
- execContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
- execContexts[0]->setIntReg(StackPointerReg, stack_min);
+ threadContexts[0]->setIntReg(ArgumentReg0, argc);
+ threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+ threadContexts[0]->setIntReg(StackPointerReg, stack_min);
Addr prog_entry = objFile->entryPoint();
- execContexts[0]->setPC(prog_entry);
- execContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
- execContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
+ threadContexts[0]->setPC(prog_entry);
+ threadContexts[0]->setNextPC(prog_entry + sizeof(MachInst));
+ threadContexts[0]->setNextNPC(prog_entry + (2 * sizeof(MachInst)));
num_processes++;
}
void
-LiveProcess::syscall(int64_t callnum, ExecContext *xc)
+LiveProcess::syscall(int64_t callnum, ThreadContext *tc)
{
num_syscalls++;
if (desc == NULL)
fatal("Syscall %d out of range", callnum);
- desc->doSyscall(callnum, this, xc);
+ desc->doSyscall(callnum, this, tc);
}
DEFINE_SIM_OBJECT_CLASS_NAME("LiveProcess", LiveProcess);
#include "sim/sim_object.hh"
class CPUExecContext;
-class ExecContext;
+class ThreadContext;
class SyscallDesc;
class PageTable;
class TranslatingPort;
/// running on.
System *system;
- // have we initialized an execution context from this process? If
+ // have we initialized a thread context from this process? If
// yes, subsequent contexts are assumed to be for dynamically
// created threads and are not initialized.
bool initialContextLoaded;
- // execution contexts associated with this process
- std::vector<ExecContext *> execContexts;
+ // thread contexts associated with this process
+ std::vector<ThreadContext *> threadContexts;
// number of CPUs (esxec contexts, really) assigned to this process.
- unsigned int numCpus() { return execContexts.size(); }
+ unsigned int numCpus() { return threadContexts.size(); }
// record of blocked context
struct WaitRec
{
Addr waitChan;
- ExecContext *waitingContext;
+ ThreadContext *waitingContext;
- WaitRec(Addr chan, ExecContext *ctx)
+ WaitRec(Addr chan, ThreadContext *ctx)
: waitChan(chan), waitingContext(ctx)
{ }
};
// override of virtual SimObject method: register statistics
virtual void regStats();
- // register an execution context for this process.
- // returns xc's cpu number (index into execContexts[])
- int registerExecContext(ExecContext *xc);
+ // register a thread context for this process.
+ // returns tc's cpu number (index into threadContexts[])
+ int registerThreadContext(ThreadContext *tc);
- void replaceExecContext(ExecContext *xc, int xcIndex);
+ void replaceThreadContext(ThreadContext *tc, int tcIndex);
// map simulator fd sim_fd to target fd tgt_fd
void dup_fd(int sim_fd, int tgt_fd);
// look up simulator fd for given target fd
int sim_fd(int tgt_fd);
- virtual void syscall(int64_t callnum, ExecContext *xc) = 0;
+ virtual void syscall(int64_t callnum, ThreadContext *tc) = 0;
};
//
virtual void argsInit(int intSize, int pageSize);
public:
- virtual void syscall(int64_t callnum, ExecContext *xc);
+ virtual void syscall(int64_t callnum, ThreadContext *tc);
virtual SyscallDesc* getDesc(int callnum) = 0;
};
#include "arch/vtophys.hh"
#include "cpu/base.hh"
#include "cpu/sampler/sampler.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/quiesce_event.hh"
#include "kern/kernel_stats.hh"
#include "sim/param.hh"
bool doQuiesce;
void
- arm(ExecContext *xc)
+ arm(ThreadContext *tc)
{
- if (xc->getKernelStats())
- xc->getKernelStats()->arm();
+ if (tc->getKernelStats())
+ tc->getKernelStats()->arm();
}
void
- quiesce(ExecContext *xc)
+ quiesce(ThreadContext *tc)
{
if (!doQuiesce)
return;
- xc->suspend();
- if (xc->getKernelStats())
- xc->getKernelStats()->quiesce();
+ tc->suspend();
+ if (tc->getKernelStats())
+ tc->getKernelStats()->quiesce();
}
void
- quiesceNs(ExecContext *xc, uint64_t ns)
+ quiesceNs(ThreadContext *tc, uint64_t ns)
{
if (!doQuiesce || ns == 0)
return;
- EndQuiesceEvent *quiesceEvent = xc->getQuiesceEvent();
+ EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(curTick + Clock::Int::ns * ns);
else
quiesceEvent->schedule(curTick + Clock::Int::ns * ns);
- xc->suspend();
- if (xc->getKernelStats())
- xc->getKernelStats()->quiesce();
+ tc->suspend();
+ if (tc->getKernelStats())
+ tc->getKernelStats()->quiesce();
}
void
- quiesceCycles(ExecContext *xc, uint64_t cycles)
+ quiesceCycles(ThreadContext *tc, uint64_t cycles)
{
if (!doQuiesce || cycles == 0)
return;
- EndQuiesceEvent *quiesceEvent = xc->getQuiesceEvent();
+ EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
if (quiesceEvent->scheduled())
quiesceEvent->reschedule(curTick +
- xc->getCpuPtr()->cycles(cycles));
+ tc->getCpuPtr()->cycles(cycles));
else
quiesceEvent->schedule(curTick +
- xc->getCpuPtr()->cycles(cycles));
+ tc->getCpuPtr()->cycles(cycles));
- xc->suspend();
- if (xc->getKernelStats())
- xc->getKernelStats()->quiesce();
+ tc->suspend();
+ if (tc->getKernelStats())
+ tc->getKernelStats()->quiesce();
}
uint64_t
- quiesceTime(ExecContext *xc)
+ quiesceTime(ThreadContext *tc)
{
- return (xc->readLastActivate() - xc->readLastSuspend()) / Clock::Int::ns;
+ return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns;
}
void
- ivlb(ExecContext *xc)
+ ivlb(ThreadContext *tc)
{
- if (xc->getKernelStats())
- xc->getKernelStats()->ivlb();
+ if (tc->getKernelStats())
+ tc->getKernelStats()->ivlb();
}
void
- ivle(ExecContext *xc)
+ ivle(ThreadContext *tc)
{
}
void
- m5exit_old(ExecContext *xc)
+ m5exit_old(ThreadContext *tc)
{
SimExit(curTick, "m5_exit_old instruction encountered");
}
void
- m5exit(ExecContext *xc, Tick delay)
+ m5exit(ThreadContext *tc, Tick delay)
{
Tick when = curTick + delay * Clock::Int::ns;
SimExit(when, "m5_exit instruction encountered");
}
void
- resetstats(ExecContext *xc, Tick delay, Tick period)
+ resetstats(ThreadContext *tc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
}
void
- dumpstats(ExecContext *xc, Tick delay, Tick period)
+ dumpstats(ThreadContext *tc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
}
void
- addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr)
+ addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
{
char symb[100];
- CopyStringOut(xc, symb, symbolAddr, 100);
+ CopyStringOut(tc, symb, symbolAddr, 100);
std::string symbol(symb);
DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
- xc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
+ tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
}
void
- dumpresetstats(ExecContext *xc, Tick delay, Tick period)
+ dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
{
if (!doStatisticsInsts)
return;
}
void
- m5checkpoint(ExecContext *xc, Tick delay, Tick period)
+ m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
{
if (!doCheckpointInsts)
return;
}
uint64_t
- readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset)
+ readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
{
- const string &file = xc->getCpuPtr()->system->params()->readfile;
+ const string &file = tc->getCpuPtr()->system->params()->readfile;
if (file.empty()) {
return ULL(0);
}
}
close(fd);
- CopyIn(xc, vaddr, buf, result);
+ CopyIn(tc, vaddr, buf, result);
delete [] buf;
return result;
}
doCheckpointInsts = __checkpoint;
}
- void debugbreak(ExecContext *xc)
+ void debugbreak(ThreadContext *tc)
{
debug_break();
}
- void switchcpu(ExecContext *xc)
+ void switchcpu(ThreadContext *tc)
{
if (SampCPU)
SampCPU->switchCPUs();
* Authors: Nathan Binkert
*/
-class ExecContext;
+class ThreadContext;
//We need the "Tick" data type from here
#include "sim/host.hh"
extern bool doCheckpointInsts;
extern bool doQuiesce;
- void arm(ExecContext *xc);
- void quiesce(ExecContext *xc);
- void quiesceNs(ExecContext *xc, uint64_t ns);
- void quiesceCycles(ExecContext *xc, uint64_t cycles);
- uint64_t quiesceTime(ExecContext *xc);
- void ivlb(ExecContext *xc);
- void ivle(ExecContext *xc);
- void m5exit(ExecContext *xc, Tick delay);
- void m5exit_old(ExecContext *xc);
- void resetstats(ExecContext *xc, Tick delay, Tick period);
- void dumpstats(ExecContext *xc, Tick delay, Tick period);
- void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
- void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
- uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
- void debugbreak(ExecContext *xc);
- void switchcpu(ExecContext *xc);
- void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
+ void arm(ThreadContext *tc);
+ void quiesce(ThreadContext *tc);
+ void quiesceNs(ThreadContext *tc, uint64_t ns);
+ void quiesceCycles(ThreadContext *tc, uint64_t cycles);
+ uint64_t quiesceTime(ThreadContext *tc);
+ void ivlb(ThreadContext *tc);
+ void ivle(ThreadContext *tc);
+ void m5exit(ThreadContext *tc, Tick delay);
+ void m5exit_old(ThreadContext *tc);
+ void resetstats(ThreadContext *tc, Tick delay, Tick period);
+ void dumpstats(ThreadContext *tc, Tick delay, Tick period);
+ void dumpresetstats(ThreadContext *tc, Tick delay, Tick period);
+ void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
+ uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset);
+ void debugbreak(ThreadContext *tc);
+ void switchcpu(ThreadContext *tc);
+ void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr);
}
#include "sim/syscall_emul.hh"
#include "base/chunk_generator.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "cpu/base.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
using namespace TheISA;
void
-SyscallDesc::doSyscall(int callnum, Process *process, ExecContext *xc)
+SyscallDesc::doSyscall(int callnum, Process *process, ThreadContext *tc)
{
DPRINTFR(SyscallVerbose, "%d: %s: syscall %s called w/arguments %d,%d,%d,%d\n",
- curTick,xc->getCpuPtr()->name(), name,
- xc->getSyscallArg(0),xc->getSyscallArg(1),
- xc->getSyscallArg(2),xc->getSyscallArg(3));
+ curTick,tc->getCpuPtr()->name(), name,
+ tc->getSyscallArg(0),tc->getSyscallArg(1),
+ tc->getSyscallArg(2),tc->getSyscallArg(3));
- SyscallReturn retval = (*funcPtr)(this, callnum, process, xc);
+ SyscallReturn retval = (*funcPtr)(this, callnum, process, tc);
DPRINTFR(SyscallVerbose, "%d: %s: syscall %s returns %d\n",
- curTick,xc->getCpuPtr()->name(), name, retval.value());
+ curTick,tc->getCpuPtr()->name(), name, retval.value());
if (!(flags & SyscallDesc::SuppressReturnValue))
- xc->setSyscallReturn(retval);
+ tc->setSyscallReturn(retval);
}
SyscallReturn
unimplementedFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
fatal("syscall %s (#%d) unimplemented.", desc->name, callnum);
SyscallReturn
ignoreFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
warn("ignoring syscall %s(%d, %d, ...)", desc->name,
- xc->getSyscallArg(0), xc->getSyscallArg(1));
+ tc->getSyscallArg(0), tc->getSyscallArg(1));
return 0;
}
SyscallReturn
exitFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- new SimExitEvent("target called exit()", xc->getSyscallArg(0) & 0xff);
+ new SimExitEvent("target called exit()", tc->getSyscallArg(0) & 0xff);
return 1;
}
SyscallReturn
-getpagesizeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+getpagesizeFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
return (int)VMPageSize;
}
SyscallReturn
-obreakFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+obreakFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
Addr junk;
// change brk addr to first arg
- Addr new_brk = xc->getSyscallArg(0);
+ Addr new_brk = tc->getSyscallArg(0);
if (new_brk != 0) {
for (ChunkGenerator gen(p->brk_point, new_brk - p->brk_point,
VMPageSize); !gen.done(); gen.next()) {
SyscallReturn
-closeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+closeFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
- int target_fd = xc->getSyscallArg(0);
+ int target_fd = tc->getSyscallArg(0);
int status = close(p->sim_fd(target_fd));
if (status >= 0)
p->free_fd(target_fd);
SyscallReturn
-readFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+readFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
- int fd = p->sim_fd(xc->getSyscallArg(0));
- int nbytes = xc->getSyscallArg(2);
- BufferArg bufArg(xc->getSyscallArg(1), nbytes);
+ int fd = p->sim_fd(tc->getSyscallArg(0));
+ int nbytes = tc->getSyscallArg(2);
+ BufferArg bufArg(tc->getSyscallArg(1), nbytes);
int bytes_read = read(fd, bufArg.bufferPtr(), nbytes);
if (bytes_read != -1)
- bufArg.copyOut(xc->getMemPort());
+ bufArg.copyOut(tc->getMemPort());
return bytes_read;
}
SyscallReturn
-writeFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+writeFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
- int fd = p->sim_fd(xc->getSyscallArg(0));
- int nbytes = xc->getSyscallArg(2);
- BufferArg bufArg(xc->getSyscallArg(1), nbytes);
+ int fd = p->sim_fd(tc->getSyscallArg(0));
+ int nbytes = tc->getSyscallArg(2);
+ BufferArg bufArg(tc->getSyscallArg(1), nbytes);
- bufArg.copyIn(xc->getMemPort());
+ bufArg.copyIn(tc->getMemPort());
int bytes_written = write(fd, bufArg.bufferPtr(), nbytes);
SyscallReturn
-lseekFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+lseekFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
- int fd = p->sim_fd(xc->getSyscallArg(0));
- uint64_t offs = xc->getSyscallArg(1);
- int whence = xc->getSyscallArg(2);
+ int fd = p->sim_fd(tc->getSyscallArg(0));
+ uint64_t offs = tc->getSyscallArg(1);
+ int whence = tc->getSyscallArg(2);
off_t result = lseek(fd, offs, whence);
SyscallReturn
-munmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+munmapFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
// given that we don't really implement mmap, munmap is really easy
return 0;
const char *hostname = "m5.eecs.umich.edu";
SyscallReturn
-gethostnameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+gethostnameFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
- int name_len = xc->getSyscallArg(1);
- BufferArg name(xc->getSyscallArg(0), name_len);
+ int name_len = tc->getSyscallArg(1);
+ BufferArg name(tc->getSyscallArg(0), name_len);
strncpy((char *)name.bufferPtr(), hostname, name_len);
- name.copyOut(xc->getMemPort());
+ name.copyOut(tc->getMemPort());
return 0;
}
SyscallReturn
-unlinkFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+unlinkFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return (TheISA::IntReg)-EFAULT;
int result = unlink(path.c_str());
}
SyscallReturn
-renameFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+renameFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
string old_name;
- if (!xc->getMemPort()->tryReadString(old_name, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(old_name, tc->getSyscallArg(0)))
return -EFAULT;
string new_name;
- if (!xc->getMemPort()->tryReadString(new_name, xc->getSyscallArg(1)))
+ if (!tc->getMemPort()->tryReadString(new_name, tc->getSyscallArg(1)))
return -EFAULT;
int64_t result = rename(old_name.c_str(), new_name.c_str());
}
SyscallReturn
-truncateFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+truncateFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
- off_t length = xc->getSyscallArg(1);
+ off_t length = tc->getSyscallArg(1);
int result = truncate(path.c_str(), length);
return (result == -1) ? -errno : result;
}
SyscallReturn
-ftruncateFunc(SyscallDesc *desc, int num, Process *process, ExecContext *xc)
+ftruncateFunc(SyscallDesc *desc, int num, Process *process, ThreadContext *tc)
{
- int fd = process->sim_fd(xc->getSyscallArg(0));
+ int fd = process->sim_fd(tc->getSyscallArg(0));
if (fd < 0)
return -EBADF;
- off_t length = xc->getSyscallArg(1);
+ off_t length = tc->getSyscallArg(1);
int result = ftruncate(fd, length);
return (result == -1) ? -errno : result;
}
SyscallReturn
-chownFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+chownFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
/* XXX endianess */
- uint32_t owner = xc->getSyscallArg(1);
+ uint32_t owner = tc->getSyscallArg(1);
uid_t hostOwner = owner;
- uint32_t group = xc->getSyscallArg(2);
+ uint32_t group = tc->getSyscallArg(2);
gid_t hostGroup = group;
int result = chown(path.c_str(), hostOwner, hostGroup);
}
SyscallReturn
-fchownFunc(SyscallDesc *desc, int num, Process *process, ExecContext *xc)
+fchownFunc(SyscallDesc *desc, int num, Process *process, ThreadContext *tc)
{
- int fd = process->sim_fd(xc->getSyscallArg(0));
+ int fd = process->sim_fd(tc->getSyscallArg(0));
if (fd < 0)
return -EBADF;
/* XXX endianess */
- uint32_t owner = xc->getSyscallArg(1);
+ uint32_t owner = tc->getSyscallArg(1);
uid_t hostOwner = owner;
- uint32_t group = xc->getSyscallArg(2);
+ uint32_t group = tc->getSyscallArg(2);
gid_t hostGroup = group;
int result = fchown(fd, hostOwner, hostGroup);
SyscallReturn
fcntlFunc(SyscallDesc *desc, int num, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int fd = xc->getSyscallArg(0);
+ int fd = tc->getSyscallArg(0);
if (fd < 0 || process->sim_fd(fd) < 0)
return -EBADF;
- int cmd = xc->getSyscallArg(1);
+ int cmd = tc->getSyscallArg(1);
switch (cmd) {
case 0: // F_DUPFD
// if we really wanted to support this, we'd need to do it
SyscallReturn
pipePseudoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
int fds[2], sim_fds[2];
int pipe_retval = pipe(fds);
// Alpha Linux convention for pipe() is that fd[0] is returned as
// the return value of the function, and fd[1] is returned in r20.
- xc->setIntReg(SyscallPseudoReturnReg, sim_fds[1]);
+ tc->setIntReg(SyscallPseudoReturnReg, sim_fds[1]);
return sim_fds[0];
}
SyscallReturn
getpidPseudoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
// Make up a PID. There's no interprocess communication in
// fake_syscall mode, so there's no way for a process to know it's
// not getting a unique value.
- xc->setIntReg(SyscallPseudoReturnReg, 99);
+ tc->setIntReg(SyscallPseudoReturnReg, 99);
return 100;
}
SyscallReturn
getuidPseudoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
// Make up a UID and EUID... it shouldn't matter, and we want the
// simulation to be deterministic.
// EUID goes in r20.
- xc->setIntReg(SyscallPseudoReturnReg, 100); //EUID
+ tc->setIntReg(SyscallPseudoReturnReg, 100); //EUID
return 100; // UID
}
SyscallReturn
getgidPseudoFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
// Get current group ID. EGID goes in r20.
- xc->setIntReg(SyscallPseudoReturnReg, 100); //EGID
+ tc->setIntReg(SyscallPseudoReturnReg, 100); //EGID
return 100;
}
SyscallReturn
setuidFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
// can't fathom why a benchmark would call this.
- warn("Ignoring call to setuid(%d)\n", xc->getSyscallArg(0));
+ warn("Ignoring call to setuid(%d)\n", tc->getSyscallArg(0));
return 0;
}
SyscallReturn
getpidFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
// Make up a PID. There's no interprocess communication in
// fake_syscall mode, so there's no way for a process to know it's
// not getting a unique value.
- xc->setIntReg(SyscallPseudoReturnReg, 99); //PID
+ tc->setIntReg(SyscallPseudoReturnReg, 99); //PID
return 100;
}
SyscallReturn
getppidFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
return 99;
}
SyscallReturn
getuidFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
return 100; // UID
}
SyscallReturn
geteuidFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
return 100; // UID
}
SyscallReturn
getgidFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
return 100;
}
SyscallReturn
getegidFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
return 100;
}
#include "base/misc.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/translating_port.hh"
#include "mem/page_table.hh"
#include "sim/process.hh"
/// Typedef for target syscall handler functions.
typedef SyscallReturn (*FuncPtr)(SyscallDesc *, int num,
- Process *, ExecContext *);
+ Process *, ThreadContext *);
const char *name; //!< Syscall name (e.g., "open").
FuncPtr funcPtr; //!< Pointer to emulation function.
enum Flags {
/// Don't set return regs according to funcPtr return value.
/// Used for syscalls with non-standard return conventions
- /// that explicitly set the ExecContext regs (e.g.,
+ /// that explicitly set the ThreadContext regs (e.g.,
/// sigreturn).
SuppressReturnValue = 1
};
}
/// Emulate the syscall. Public interface for calling through funcPtr.
- void doSyscall(int callnum, Process *proc, ExecContext *xc);
+ void doSyscall(int callnum, Process *proc, ThreadContext *tc);
};
/// Handler for unimplemented syscalls that we haven't thought about.
SyscallReturn unimplementedFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Handler for unimplemented syscalls that we never intend to
/// implement (signal handling, etc.) and should not affect the correct
/// behavior of the program. Print a warning only if the appropriate
/// trace flag is enabled. Return success to the target program.
SyscallReturn ignoreFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target exit() handler: terminate simulation.
SyscallReturn exitFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getpagesize() handler.
SyscallReturn getpagesizeFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target obreak() handler: set brk address.
SyscallReturn obreakFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target close() handler.
SyscallReturn closeFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target read() handler.
SyscallReturn readFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target write() handler.
SyscallReturn writeFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target lseek() handler.
SyscallReturn lseekFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target munmap() handler.
SyscallReturn munmapFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target gethostname() handler.
SyscallReturn gethostnameFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target unlink() handler.
SyscallReturn unlinkFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target rename() handler.
SyscallReturn renameFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target truncate() handler.
SyscallReturn truncateFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target ftruncate() handler.
SyscallReturn ftruncateFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target chown() handler.
SyscallReturn chownFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target fchown() handler.
SyscallReturn fchownFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target fnctl() handler.
SyscallReturn fcntlFunc(SyscallDesc *desc, int num,
- Process *process, ExecContext *xc);
+ Process *process, ThreadContext *tc);
/// Target setuid() handler.
SyscallReturn setuidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getpid() handler.
SyscallReturn getpidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getuid() handler.
SyscallReturn getuidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getgid() handler.
SyscallReturn getgidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getppid() handler.
SyscallReturn getppidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target geteuid() handler.
SyscallReturn geteuidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getegid() handler.
SyscallReturn getegidFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Pseudo Funcs - These functions use a different return convension,
/// returning a second value in a register other than the normal return register
SyscallReturn pipePseudoFunc(SyscallDesc *desc, int num,
- Process *process, ExecContext *xc);
+ Process *process, ThreadContext *tc);
/// Target getpidPseudo() handler.
SyscallReturn getpidPseudoFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getuidPseudo() handler.
SyscallReturn getuidPseudoFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// Target getgidPseudo() handler.
SyscallReturn getgidPseudoFunc(SyscallDesc *desc, int num,
- Process *p, ExecContext *xc);
+ Process *p, ThreadContext *tc);
/// This struct is used to build an target-OS-dependent table that
template <class OS>
SyscallReturn
ioctlFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int fd = xc->getSyscallArg(0);
- unsigned req = xc->getSyscallArg(1);
+ int fd = tc->getSyscallArg(0);
+ unsigned req = tc->getSyscallArg(1);
DPRINTF(SyscallVerbose, "ioctl(%d, 0x%x, ...)\n", fd, req);
default:
fatal("Unsupported ioctl call: ioctl(%d, 0x%x, ...) @ 0x%llx\n",
- fd, req, xc->readPC());
+ fd, req, tc->readPC());
}
}
template <class OS>
SyscallReturn
openFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
std::string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
if (path == "/dev/sysdev0") {
return -ENOENT;
}
- int tgtFlags = xc->getSyscallArg(1);
- int mode = xc->getSyscallArg(2);
+ int tgtFlags = tc->getSyscallArg(1);
+ int mode = tc->getSyscallArg(2);
int hostFlags = 0;
// translate open flags
template <class OS>
SyscallReturn
chmodFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
std::string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
- uint32_t mode = xc->getSyscallArg(1);
+ uint32_t mode = tc->getSyscallArg(1);
mode_t hostMode = 0;
// XXX translate mode flags via OS::something???
template <class OS>
SyscallReturn
fchmodFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int fd = xc->getSyscallArg(0);
+ int fd = tc->getSyscallArg(0);
if (fd < 0 || process->sim_fd(fd) < 0) {
// doesn't map to any simulator fd: not a valid target fd
return -EBADF;
}
- uint32_t mode = xc->getSyscallArg(1);
+ uint32_t mode = tc->getSyscallArg(1);
mode_t hostMode = 0;
// XXX translate mode flags via OS::someting???
template <class OS>
SyscallReturn
statFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
std::string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
struct stat hostBuf;
if (result < 0)
return -errno;
- OS::copyOutStatBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf);
+ OS::copyOutStatBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf);
return 0;
}
template <class OS>
SyscallReturn
fstat64Func(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int fd = xc->getSyscallArg(0);
+ int fd = tc->getSyscallArg(0);
if (fd < 0 || process->sim_fd(fd) < 0) {
// doesn't map to any simulator fd: not a valid target fd
return -EBADF;
if (result < 0)
return -errno;
- OS::copyOutStat64Buf(xc->getMemPort(), fd, xc->getSyscallArg(1), &hostBuf);
+ OS::copyOutStat64Buf(tc->getMemPort(), fd, tc->getSyscallArg(1), &hostBuf);
return 0;
}
template <class OS>
SyscallReturn
lstatFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
std::string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
struct stat hostBuf;
if (result < 0)
return -errno;
- OS::copyOutStatBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf);
+ OS::copyOutStatBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf);
return 0;
}
template <class OS>
SyscallReturn
lstat64Func(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
std::string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
#if BSD_HOST
if (result < 0)
return -errno;
- OS::copyOutStat64Buf(xc->getMemPort(), -1, xc->getSyscallArg(1), &hostBuf);
+ OS::copyOutStat64Buf(tc->getMemPort(), -1, tc->getSyscallArg(1), &hostBuf);
return 0;
}
template <class OS>
SyscallReturn
fstatFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int fd = process->sim_fd(xc->getSyscallArg(0));
+ int fd = process->sim_fd(tc->getSyscallArg(0));
DPRINTF(SyscallVerbose, "fstat(%d, ...)\n", fd);
if (result < 0)
return -errno;
- OS::copyOutStatBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf);
+ OS::copyOutStatBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf);
return 0;
}
template <class OS>
SyscallReturn
statfsFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
std::string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
struct statfs hostBuf;
if (result < 0)
return -errno;
- OS::copyOutStatfsBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf);
+ OS::copyOutStatfsBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf);
return 0;
}
template <class OS>
SyscallReturn
fstatfsFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int fd = process->sim_fd(xc->getSyscallArg(0));
+ int fd = process->sim_fd(tc->getSyscallArg(0));
if (fd < 0)
return -EBADF;
if (result < 0)
return -errno;
- OS::copyOutStatfsBuf(xc->getMemPort(), xc->getSyscallArg(1), &hostBuf);
+ OS::copyOutStatfsBuf(tc->getMemPort(), tc->getSyscallArg(1), &hostBuf);
return 0;
}
template <class OS>
SyscallReturn
writevFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int fd = xc->getSyscallArg(0);
+ int fd = tc->getSyscallArg(0);
if (fd < 0 || process->sim_fd(fd) < 0) {
// doesn't map to any simulator fd: not a valid target fd
return -EBADF;
}
- TranslatingPort *p = xc->getMemPort();
- uint64_t tiov_base = xc->getSyscallArg(1);
- size_t count = xc->getSyscallArg(2);
+ TranslatingPort *p = tc->getMemPort();
+ uint64_t tiov_base = tc->getSyscallArg(1);
+ size_t count = tc->getSyscallArg(2);
struct iovec hiov[count];
for (int i = 0; i < count; ++i)
{
/// anything else.
template <class OS>
SyscallReturn
-mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
+mmapFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
- Addr start = xc->getSyscallArg(0);
- uint64_t length = xc->getSyscallArg(1);
- // int prot = xc->getSyscallArg(2);
- int flags = xc->getSyscallArg(3);
- // int fd = p->sim_fd(xc->getSyscallArg(4));
- // int offset = xc->getSyscallArg(5);
+ Addr start = tc->getSyscallArg(0);
+ uint64_t length = tc->getSyscallArg(1);
+ // int prot = tc->getSyscallArg(2);
+ int flags = tc->getSyscallArg(3);
+ // int fd = p->sim_fd(tc->getSyscallArg(4));
+ // int offset = tc->getSyscallArg(5);
if ((start % TheISA::VMPageSize) != 0 ||
(length % TheISA::VMPageSize) != 0) {
if (!(flags & OS::TGT_MAP_ANONYMOUS)) {
warn("allowing mmap of file @ fd %d. "
- "This will break if not /dev/zero.", xc->getSyscallArg(4));
+ "This will break if not /dev/zero.", tc->getSyscallArg(4));
}
return start;
template <class OS>
SyscallReturn
getrlimitFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- unsigned resource = xc->getSyscallArg(0);
- TypedBufferArg<typename OS::rlimit> rlp(xc->getSyscallArg(1));
+ unsigned resource = tc->getSyscallArg(0);
+ TypedBufferArg<typename OS::rlimit> rlp(tc->getSyscallArg(1));
switch (resource) {
case OS::TGT_RLIMIT_STACK:
break;
}
- rlp.copyOut(xc->getMemPort());
+ rlp.copyOut(tc->getMemPort());
return 0;
}
template <class OS>
SyscallReturn
gettimeofdayFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- TypedBufferArg<typename OS::timeval> tp(xc->getSyscallArg(0));
+ TypedBufferArg<typename OS::timeval> tp(tc->getSyscallArg(0));
getElapsedTime(tp->tv_sec, tp->tv_usec);
tp->tv_sec += seconds_since_epoch;
tp->tv_sec = htog(tp->tv_sec);
tp->tv_usec = htog(tp->tv_usec);
- tp.copyOut(xc->getMemPort());
+ tp.copyOut(tc->getMemPort());
return 0;
}
template <class OS>
SyscallReturn
utimesFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
std::string path;
- if (!xc->getMemPort()->tryReadString(path, xc->getSyscallArg(0)))
+ if (!tc->getMemPort()->tryReadString(path, tc->getSyscallArg(0)))
return -EFAULT;
- TypedBufferArg<typename OS::timeval [2]> tp(xc->getSyscallArg(1));
- tp.copyIn(xc->getMemPort());
+ TypedBufferArg<typename OS::timeval [2]> tp(tc->getSyscallArg(1));
+ tp.copyIn(tc->getMemPort());
struct timeval hostTimeval[2];
for (int i = 0; i < 2; ++i)
template <class OS>
SyscallReturn
getrusageFunc(SyscallDesc *desc, int callnum, Process *process,
- ExecContext *xc)
+ ThreadContext *tc)
{
- int who = xc->getSyscallArg(0); // THREAD, SELF, or CHILDREN
- TypedBufferArg<typename OS::rusage> rup(xc->getSyscallArg(1));
+ int who = tc->getSyscallArg(0); // THREAD, SELF, or CHILDREN
+ TypedBufferArg<typename OS::rusage> rup(tc->getSyscallArg(1));
if (who != OS::TGT_RUSAGE_SELF) {
// don't really handle THREAD or CHILDREN, but just warn and
rup->ru_nvcsw = 0;
rup->ru_nivcsw = 0;
- rup.copyOut(xc->getMemPort());
+ rup.copyOut(tc->getMemPort());
return 0;
}
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
-#include "cpu/exec_context.hh"
+#include "cpu/thread_context.hh"
#include "mem/mem_object.hh"
#include "mem/physical.hh"
#include "sim/builder.hh"
#endif // FULL_SYSTEM
int
-System::registerExecContext(ExecContext *xc, int id)
+System::registerThreadContext(ThreadContext *tc, int id)
{
if (id == -1) {
- for (id = 0; id < execContexts.size(); id++) {
- if (!execContexts[id])
+ for (id = 0; id < threadContexts.size(); id++) {
+ if (!threadContexts[id])
break;
}
}
- if (execContexts.size() <= id)
- execContexts.resize(id + 1);
+ if (threadContexts.size() <= id)
+ threadContexts.resize(id + 1);
- if (execContexts[id])
+ if (threadContexts[id])
panic("Cannot have two CPUs with the same id (%d)\n", id);
- execContexts[id] = xc;
+ threadContexts[id] = tc;
numcpus++;
#if FULL_SYSTEM
- RemoteGDB *rgdb = new RemoteGDB(this, xc);
+ RemoteGDB *rgdb = new RemoteGDB(this, tc);
GDBListener *gdbl = new GDBListener(rgdb, 7000 + id);
gdbl->listen();
/**
System::startup()
{
int i;
- for (i = 0; i < execContexts.size(); i++)
- execContexts[i]->activate(0);
+ for (i = 0; i < threadContexts.size(); i++)
+ threadContexts[i]->activate(0);
}
void
-System::replaceExecContext(ExecContext *xc, int id)
+System::replaceThreadContext(ThreadContext *tc, int id)
{
- if (id >= execContexts.size()) {
- panic("replaceExecContext: bad id, %d >= %d\n",
- id, execContexts.size());
+ if (id >= threadContexts.size()) {
+ panic("replaceThreadContext: bad id, %d >= %d\n",
+ id, threadContexts.size());
}
- execContexts[id] = xc;
+ threadContexts[id] = tc;
#if FULL_SYSTEM
- remoteGDB[id]->replaceExecContext(xc);
+ remoteGDB[id]->replaceThreadContext(tc);
#endif // FULL_SYSTEM
}
#endif
class BaseCPU;
-class ExecContext;
+class ThreadContext;
class ObjectFile;
class PhysicalMemory;
PhysicalMemory *physmem;
PCEventQueue pcEventQueue;
- std::vector<ExecContext *> execContexts;
+ std::vector<ThreadContext *> threadContexts;
int numcpus;
int getNumCPUs()
{
- if (numcpus != execContexts.size())
+ if (numcpus != threadContexts.size())
panic("cpu array not fully populated!");
return numcpus;
#endif // FULL_SYSTEM
- int registerExecContext(ExecContext *xc, int xcIndex);
- void replaceExecContext(ExecContext *xc, int xcIndex);
+ int registerThreadContext(ThreadContext *tc, int tcIndex);
+ void replaceThreadContext(ThreadContext *tc, int tcIndex);
void regStats();
void serialize(std::ostream &os);
#include "arch/vtophys.hh"
#include "arch/isa_traits.hh"
-class ExecContext;
+class ThreadContext;
template <class T>
class VPtr
typedef T Type;
private:
- ExecContext *xc;
+ ThreadContext *tc;
Addr ptr;
public:
- ExecContext *GetXC() const { return xc; }
+ ThreadContext *GetTC() const { return tc; }
Addr GetPointer() const { return ptr; }
public:
- explicit VPtr(ExecContext *_xc, Addr p = 0) : xc(_xc), ptr(p) { }
+ explicit VPtr(ThreadContext *_tc, Addr p = 0) : tc(_tc), ptr(p) { }
template <class U>
- VPtr(const VPtr<U> &vp) : xc(vp.GetXC()), ptr(vp.GetPointer()) {}
+ VPtr(const VPtr<U> &vp) : tc(vp.GetTC()), ptr(vp.GetPointer()) {}
~VPtr() {}
bool operator!() const
template <class U>
const VPtr<T> &operator=(const VPtr<U> &vp)
{
- xc = vp.GetXC();
+ tc = vp.GetTC();
ptr = vp.GetPointer();
return *this;
operator T *()
{
panic("Needs to be rewritten\n");
-/* void *addr = vtomem(xc, ptr, sizeof(T));
+/* void *addr = vtomem(tc, ptr, sizeof(T));
return (T *)addr;
*/
}
T *operator->()
{
panic("Needs to be rewritten\n");
-/* void *addr = vtomem(xc, ptr, sizeof(T));
+/* void *addr = vtomem(tc, ptr, sizeof(T));
return (T *)addr;
*/
}
T &operator*()
{
panic("Needs to be rewritten\n");
-/* void *addr = vtomem(xc, ptr, sizeof(T));
+/* void *addr = vtomem(tc, ptr, sizeof(T));
return *(T *)addr;
*/
}
projects / gem5.git / commitdiff