Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV...

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2389d7d313f49820b68ab274c4c186743dba7bb8..63cf646e9f1fea11acaaf17b8f0b70cdff3e8cc1 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -881,9 +881,15 @@ param_decl_list:
 
 single_param_decl:
        TOK_ID '=' expr {
-               if (astbuf1 == nullptr)
-                       frontend_verilog_yyerror("syntax error");
-               AstNode *node = astbuf1->clone();
+               AstNode *node;
+               if (astbuf1 == nullptr) {
+                       if (!sv_mode)
+                               frontend_verilog_yyerror("syntax error");
+                       node = new AstNode(AST_PARAMETER);
+                       node->children.push_back(AstNode::mkconst_int(0, true));
+               } else {
+                       node = astbuf1->clone();
+               }
                node->str = *$1;
                delete node->children[0];
                node->children[0] = $3;