MIPS/BFD: Simplify register index calculation in BZ16_REG_FIELD

Just mask higher bits off, which returns the same set of 3-bit register
encodings of { 0, 1, 2, 3, 4, 5, 6, 7 } for the allowed 5-bit encodings
of { 16, 17, 2, 3, 4, 5, 6, 7 }.  Input has already been validated with
OP16_VALID_REG.

	bfd/
	* elfxx-mips.c (BZ16_REG_FIELD): Simplify calculation.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 2e4f3b3c8cfb6666d5caae177a4cf704ce11db32..abf583be18bc3bc5c7c1dd70fef110c9d6adfd28 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,7 @@
+2016-01-24  Maciej W. Rozycki  <macro@imgtec.com>
+
+       * elfxx-mips.c (BZ16_REG_FIELD): Simplify calculation.
+
 2016-01-24  Maciej W. Rozycki  <macro@imgtec.com>
 
        * elfxx-mips.c (BZ16_REG): Correct calculation.

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 176970a82c3f8398aa1a6d3839753a0fad494120..fa14e8dd343f95d0bc7a68cb835628b9678b296c 100644 (file)
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -13111,8 +13111,7 @@ static const struct opcode_descriptor bz_insns_16[] = {
 /* Switch between a 5-bit register index and its 3-bit shorthand.  */
 
 #define BZ16_REG(opcode) ((((((opcode) >> 7) & 7) + 0x1e) & 0xf) + 2)
-#define BZ16_REG_FIELD(r) \
-  (((2 <= (r) && (r) <= 7) ? (r) : ((r) - 16)) << 7)
+#define BZ16_REG_FIELD(r) (((r) & 7) << 7)
 
 
 /* 32-bit instructions with a delay slot.  */