break;
}
+ if (ir3_shader_gpuid(so->shader) >= 400) {
+ /* a4xx seems to have *no* sam.p */
+ lconfig.lower_TXP = ~0; /* lower all txp */
+ } else {
+ /* a3xx just needs to avoid sam.p for 3d tex */
+ lconfig.lower_TXP = (1 << TGSI_TEXTURE_3D);
+ }
+
ctx->tokens = tgsi_transform_lowering(&lconfig, tokens, &ctx->info);
ctx->free_tokens = !!ctx->tokens;
if (!ctx->tokens) {
assemble_variant(struct ir3_shader_variant *v)
{
struct fd_context *ctx = fd_context(v->shader->pctx);
+ uint32_t gpu_id = ir3_shader_gpuid(v->shader);
uint32_t sz, *bin;
- bin = ir3_assemble(v->ir, &v->info, ctx->screen->gpu_id);
+ bin = ir3_assemble(v->ir, &v->info, gpu_id);
sz = v->info.sizedwords * 4;
v->bo = fd_bo_new(ctx->dev, sz,
free(bin);
- if (ctx->screen->gpu_id >= 400) {
+ if (gpu_id >= 400) {
v->instrlen = v->info.sizedwords / (2 * 16);
} else {
v->instrlen = v->info.sizedwords / (2 * 4);
return NULL;
}
+uint32_t
+ir3_shader_gpuid(struct ir3_shader *shader)
+{
+ struct fd_context *ctx = fd_context(shader->pctx);
+ return ctx->screen->gpu_id;
+}
+
struct ir3_shader_variant *
ir3_shader_variant(struct ir3_shader *shader, struct ir3_shader_key key)
{
struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
const struct tgsi_token *tokens, enum shader_t type);
void ir3_shader_destroy(struct ir3_shader *shader);
-
+uint32_t ir3_shader_gpuid(struct ir3_shader *shader);
struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,
struct ir3_shader_key key);