Fix extremely stupid typo

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 3f5cf3f5f0e8dbf8e5de7c1709ed8c3cc8c0617f..306bc5d82f9d08a3ff3676b2fc47d843a1a4deba 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -774,7 +774,7 @@ struct VerificImporter
 
                                SigBit outsig = net_map.at(out);
                                log_assert(outsig.wire && GetSize(outsig.wire) == 1);
-                               outsig.wire->attributes["\\init"] == Const(0, 1);
+                               outsig.wire->attributes["\\init"] = Const(0, 1);
 
                                module->addDff(NEW_ID, net_map.at(clk), net_map.at(in2), net_map.at(out));
                                continue;