ppc-opc: support grevi and grevi. instructions

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 429152d4006deed04f94b2346b3360f31d60f285..6bea447313a1f66981a3ddce87748281be6bad28 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3668,6 +3668,7 @@ const struct powerpc_operand powerpc_operands[] =
   /* The DCM and DGM fields in a Z form instruction.  */
 #define DCM SH16
 #define DGM DCM
+#define XBI6 SH16
   { 0x3f, 10, NULL, NULL, 0 },
 
   /* The EH field in larx instruction.  */
@@ -4708,6 +4709,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
    | (((uint64_t)(rc)) & 1))
 #define XBM5_MASK      XBM5 (0x3f, 0x3ff, 1)
 
+/* An XBM6 form instruction. */
+#define XBM6(op, xop, rc)                      \
+  (OP (op)                                     \
+   | ((((uint64_t)(xop)) & 0x1ff) << 1)                \
+   | (((uint64_t)(rc)) & 1))
+#define XBM6_MASK      XBM6 (0x3f, 0x1ff, 1)
+
 /* The BO encodings used in extended conditional branch mnemonics.  */
 #define BODNZF (0x0)
 #define BODNZFP        (0x1)
@@ -5863,6 +5871,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"grev",       XBM5(5,150,0),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA, RB}},
 {"grev.",      XBM5(5,150,1),  XBM5_MASK,      DRAFT,  PPCVLE, {RT, RA, RB}},
+{"grevi",      XBM6(5,214,0),  XBM6_MASK,      DRAFT,  PPCVLE, {RT, RA, XBI6}},
+{"grevi.",     XBM6(5,214,1),  XBM6_MASK,      DRAFT,  PPCVLE, {RT, RA, XBI6}},
 
 {"lxvp",       DQXP(6,0),      DQXP_MASK,   POWER10,   PPCVLE,         {XTP, DQ, RA0}},
 {"stxvp",      DQXP(6,1),      DQXP_MASK,   POWER10,   PPCVLE,         {XTP, DQ, RA0}},