(no commit message)

diff --git a/cole.mdwn b/cole.mdwn
index 9e90ed46b97a2a9bdd8aa53b81ed2757430b52fc..d5514f1ec7b23ead839cbf211ceb79653d07b6a7 100644 (file)
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -47,14 +47,13 @@ move things along from one stage to the next
 
 submitted but not confirmed paid:
 
+## Paid
+
+# wishbone 2019-10-043 1-OCT-2020
+
 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG
   - EUR 150
 
-- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
-  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=404> Adding nmigen-soc as a dependency needs documentation updated
   - EUR 100
 
@@ -67,6 +66,9 @@ submitted but not confirmed paid:
 - <https://bugs.libre-soc.org/show_bug.cgi?id=351> Virtual Regfile port
   - EUR 200. shared, lkcl (50%, EUR 100), cole (50%, EUR 100)
 
-### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
+# coriolis2 2019-10-029 1-OCT-2020
 
-## Paid
+- Coriolis2 documentation and setup scripts, (documentation budget, EUR 200)
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=291>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=178>
+  - <https://bugs.libre-soc.org/show_bug.cgi?id=320>