* simops.c (OP_40): Delete. Move code to...

* v850-igen.c (): ...Here. Sign extend the first operand.
* simops.h (OP_40): Remove prototype.

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 9dcfd052785fb65baf990983c6069be2ed260ec7..134f0fdcc6f7ff1afd0237eabc2fc26fe3abf969 100644 (file)
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,9 @@
+2003-04-06  Nick Clifton  <nickc@redhat.com>
+
+       * simops.c (OP_40): Delete.  Move code to:
+       * v850-igen.c (): Here. Sign extend the first operand.
+       * simops.h (OP_40): Remove prototype.
+
 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 
        * interp.c (sim_open, sim_create_inferior): Rename _bfd to bfd.

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index fd0172ead78eea0de2c17aff6fd4c40e0e27c029..87868f5b7486d89262095a9c0a348baf6d8d2a1d 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -771,50 +771,6 @@ OP_6E0 ()
   return 4;
 }
 
-/* divh reg1, reg2 */
-int
-OP_40 ()
-{
-  unsigned int op0, op1, result, ov, s, z;
-  int temp;
-
-  trace_input ("divh", OP_REG_REG, 0);
-
-  /* Compute the result.  */
-  temp = EXTEND16 (State.regs[ OP[0] ]);
-  op0 = temp;
-  op1 = State.regs[OP[1]];
-  
-  if (op0 == 0xffffffff && op1 == 0x80000000)
-    {
-      result = 0x80000000;
-      ov = 1;
-    }
-  else if (op0 != 0)
-    {
-      result = op1 / op0;
-      ov = 0;
-    }
-  else
-    {
-      result = 0x0;
-      ov = 1;
-    }
-  
-  /* Compute the condition codes.  */
-  z = (result == 0);
-  s = (result & 0x80000000);
-  
-  /* Store the result and condition codes.  */
-  State.regs[OP[1]] = result;
-  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
-         | (ov ? PSW_OV : 0));
-  trace_output (OP_REG_REG);
-
-  return 2;
-}
-
 /* cmp reg, reg */
 int
 OP_1E0 ()

diff --git a/sim/v850/simops.h b/sim/v850/simops.h
index d4c0792bf5e6c5f4c155c24c64e3db2c78a13a3b..750fb700e478890b407b742e3dcf02a92e7c00ba 100644 (file)
--- a/sim/v850/simops.h
+++ b/sim/v850/simops.h
@@ -17,7 +17,6 @@ int OP_180 (void);
 int OP_E0 (void);
 int OP_2E0 (void);
 int OP_6E0 (void);
-int OP_40 (void);
 int OP_1E0 (void);
 int OP_260 (void);
 int OP_7E0 (void);

diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 0a4c08a30f00c8cc43651768477c2c966bcc84e6..3f14957965abcfb6ec79a74ce2635e816a99a40e 100644 (file)
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -332,7 +332,48 @@ rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 rrrrr!0,000010,RRRRR!0:I:::divh
 "divh r<reg1>, r<reg2>"
 {
-  COMPAT_1 (OP_40 ());
+  unsigned32 ov, s, z;
+  signed long int op0, op1, result;
+
+  trace_input ("divh", OP_REG_REG, 0);
+
+  PC = cia;
+  OP[0] = instruction_0 & 0x1f;
+  OP[1] = (instruction_0 >> 11) & 0x1f;
+
+  /* Compute the result.  */
+  op0 = EXTEND16 (State.regs[OP[0]]);
+  op1 = State.regs[OP[1]];
+  
+  if (op0 == 0xffffffff && op1 == 0x80000000)
+    {
+      result = 0x80000000;
+      ov = 1;
+    }
+  else if (op0 != 0)
+    {
+      result = op1 / op0;
+      ov = 0;
+    }
+  else
+    {
+      result = 0x0;
+      ov = 1;
+    }
+  
+  /* Compute the condition codes.  */
+  z = (result == 0);
+  s = (result & 0x80000000);
+  
+  /* Store the result and condition codes.  */
+  State.regs[OP[1]] = result;
+  PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+  PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
+
+  trace_output (OP_REG_REG);
+
+  PC += 2;
+  nia = PC;
 }
 
 rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh