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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index a28f8cfe9cc4a1b9c90f5e3e671faa22f2b9ee03..da038b714b279271038db69ab94658d219204778 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -7,7 +7,8 @@ The harmonised RVP register file is divided into a lower bank of Vector[INT8] an
 | Register           | Andes ISA                              | Harmonised RVP ISA            |
 | ------------------ | -------------------------              | -------------------           |
 | v0                 | Hardwired zero                         | Hardwired zero                |
-| v1                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate masks               |
+| v1                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | Predicate mask                |
+| |  |  |
 | v2                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
 | v3                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
 | v4                 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xSINT8]  |
@@ -37,6 +38,7 @@ The harmonised RVP register file is divided into a lower bank of Vector[INT8] an
 | v27                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
 | v28                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
 | v29                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xUINT16] |
+| |  |  |
 | v30                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |
 | v31                | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[1xSINT32] |