+++ /dev/null
-From 0a59aa440a4c125b81504c777b066ae4eb1f09f0 Mon Sep 17 00:00:00 2001
-From: Max Filippov <jcmvbkbc@gmail.com>
-Date: Tue, 24 Sep 2019 04:15:17 -0700
-Subject: [PATCH] xtensa: fix PR target/91880
-
-Xtensa hwloop_optimize segfaults when zero overhead loop is about to be
-inserted as the first instruction of the function.
-Insert zero overhead loop instruction into new basic block before the
-loop when basic block that precedes the loop is empty.
-
-2019-09-26 Max Filippov <jcmvbkbc@gmail.com>
-gcc/
- * config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead
- loop instruction into new basic block before the loop when basic
- block that precedes the loop is empty.
-
-Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
-Backported from: r276166
-
- gcc/config/xtensa/xtensa.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
-index ee5612441e2..2527468d57d 100644
---- a/gcc/config/xtensa/xtensa.c
-+++ b/gcc/config/xtensa/xtensa.c
-@@ -4235,7 +4235,9 @@ hwloop_optimize (hwloop_info loop)
-
- seq = get_insns ();
-
-- if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1)
-+ entry_after = BB_END (entry_bb);
-+ if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1
-+ || !entry_after)
- {
- basic_block new_bb;
- edge e;
-@@ -4256,7 +4258,6 @@ hwloop_optimize (hwloop_info loop)
- }
- else
- {
-- entry_after = BB_END (entry_bb);
- while (DEBUG_INSN_P (entry_after)
- || (NOTE_P (entry_after)
- && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK))
---
-2.24.1
-
+++ /dev/null
-From 1383012ae409ed91903b2b76ee15137bc1f89900 Mon Sep 17 00:00:00 2001
-From: shorne <shorne@138bc75d-0d04-0410-961f-82ee72b054a4>
-Date: Sat, 31 Aug 2019 06:00:56 +0000
-Subject: [PATCH] or1k: Fix issue with set_got clobbering LR (r9)
-
-When compiling glibc we found that the GOT register was being allocated
-r9 when the instruction was still set_got_tmp. That is a problem
-because r9 is the Link Register (LR) in OpenRISC which is used/clobbered
-in set_got. We cannot use r9 as the GOT register. Also, we cannot
-simply say set_got_tmp clobbers r9 as this is the reason for having the
-temporary set_got_tmp.
-
-Fix by using a register class constraint that does not allow r9 during
-register allocation.
-
-gcc/ChangeLog:
-
- * config/or1k/constraints.md (t): New constraint.
- * config/or1k/or1k.h (GOT_REGS): New register class.
- * config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint.
-
-git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@275242 138bc75d-0d04-0410-961f-82ee72b054a4
-(cherry picked from commit 5b9471ffca25d39635680516ba2ff85295480fc3)
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
----
- gcc/config/or1k/constraints.md | 4 ++++
- gcc/config/or1k/or1k.h | 3 +++
- gcc/config/or1k/or1k.md | 4 ++--
- 3 files changed, 9 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md
-index 93da8c058c6..a16b749008f 100644
---- a/gcc/config/or1k/constraints.md
-+++ b/gcc/config/or1k/constraints.md
-@@ -24,6 +24,7 @@
-
- ; We use:
- ; c - sibcall registers
-+; t - got address registers (excludes LR (r9) which is clobbered by set_got)
- ; I - constant signed 16-bit
- ; K - constant unsigned 16-bit
- ; M - constant signed 16-bit shifted left 16-bits (l.movhi)
-@@ -32,6 +33,9 @@
- (define_register_constraint "c" "SIBCALL_REGS"
- "Registers which can hold a sibling call address")
-
-+(define_register_constraint "t" "GOT_REGS"
-+ "Registers which can be used to store the Global Offset Table (GOT) address.")
-+
- ;; Immediates
- (define_constraint "I"
- "A signed 16-bit immediate in the range -32768 to 32767."
-diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
-index 6dda230f217..feee702d89c 100644
---- a/gcc/config/or1k/or1k.h
-+++ b/gcc/config/or1k/or1k.h
-@@ -189,6 +189,7 @@ enum reg_class
- {
- NO_REGS,
- SIBCALL_REGS,
-+ GOT_REGS,
- GENERAL_REGS,
- FLAG_REGS,
- ALL_REGS,
-@@ -200,6 +201,7 @@ enum reg_class
- #define REG_CLASS_NAMES { \
- "NO_REGS", \
- "SIBCALL_REGS", \
-+ "GOT_REGS", \
- "GENERAL_REGS", \
- "FLAG_REGS", \
- "ALL_REGS" }
-@@ -212,6 +214,7 @@ enum reg_class
- #define REG_CLASS_CONTENTS \
- { { 0x00000000, 0x00000000 }, \
- { SIBCALL_REGS_MASK, 0 }, \
-+ { 0xfffffdff, 0x00000000 }, \
- { 0xffffffff, 0x00000003 }, \
- { 0x00000000, 0x00000004 }, \
- { 0xffffffff, 0x00000007 } \
-diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
-index 2dad51cd46b..88f3f02630f 100644
---- a/gcc/config/or1k/or1k.md
-+++ b/gcc/config/or1k/or1k.md
-@@ -595,7 +595,7 @@
- ;; set_got pattern below. This works because the set_got_tmp insn is the
- ;; first insn in the stream and that it isn't moved during RA.
- (define_insn "set_got_tmp"
-- [(set (match_operand:SI 0 "register_operand" "=r")
-+ [(set (match_operand:SI 0 "register_operand" "=t")
- (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))]
- ""
- {
-@@ -604,7 +604,7 @@
-
- ;; The insn to initialize the GOT.
- (define_insn "set_got"
-- [(set (match_operand:SI 0 "register_operand" "=r")
-+ [(set (match_operand:SI 0 "register_operand" "=t")
- (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
- (clobber (reg:SI LR_REGNUM))]
- ""
---
-2.24.1
-
+++ /dev/null
-From 2aefc4ee703ce3ff70ad25915005cacfbaae0c49 Mon Sep 17 00:00:00 2001
-From: Bernd Kuhls <bernd.kuhls@t-online.de>
-Date: Fri, 27 Mar 2020 21:23:53 +0100
-Subject: [PATCH] gcc: define _REENTRANT for OpenRISC when -pthread is passed
-
-The detection of pthread support fails on OpenRISC unless _REENTRANT
-is defined. Added the CPP_SPEC definition to correct this.
-
-Patch sent upstream: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94372
-
-Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de>
----
- gcc/config/or1k/linux.h | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/gcc/config/or1k/linux.h b/gcc/config/or1k/linux.h
-index 4b2f7b6e1fd..b00d23ddfa0 100644
---- a/gcc/config/or1k/linux.h
-+++ b/gcc/config/or1k/linux.h
-@@ -32,6 +32,8 @@
- #undef MUSL_DYNAMIC_LINKER
- #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-or1k.so.1"
-
-+#define CPP_SPEC "%{pthread:-D_REENTRANT}"
-+
- #undef LINK_SPEC
- #define LINK_SPEC "%{h*} \
- %{static:-Bstatic} \
---
-2.21.0
-
+++ /dev/null
-From 811c8d628045c3d248144fc560a4bf80209ca16e Mon Sep 17 00:00:00 2001
-From: Romain Naour <romain.naour@gmail.com>
-Date: Thu, 21 May 2020 15:58:02 +0200
-Subject: [PATCH] gcc/Makefile.in: move SELFTEST_DEPS before including language
- makefile fragments
-
-As reported by several Buildroot users [1][2][3], the gcc build
-may fail while running selftests makefile target.
-
-The problem only occurs when ccache is used with gcc 9 and 10,
-probably due to a race condition.
-
-While debuging with "make -p" we can notice that s-selftest-c target
-contain only "cc1" as dependency instead of cc1 and SELFTEST_DEPS [4].
-
- s-selftest-c: cc1
-
-While the build is failing, the s-selftest-c dependencies recipe is
-still running and reported as a bug by make.
-
- "Dependencies recipe running (THIS IS A BUG)."
-
-A change [5] in gcc 9 seems to introduce the problem since we can't
-reproduce this problem with gcc 8.
-
-As suggested by Yann E. MORIN [6], move SELFTEST_DEPS before
-including language makefile fragments.
-
-With the fix applied, the s-seltest-c dependency contains
-SELFTEST_DEPS value.
-
- s-selftest-c: cc1 xgcc specs stmp-int-hdrs ../../gcc/testsuite/selftests
-
-[1] http://lists.busybox.net/pipermail/buildroot/2020-May/282171.html
-[2] http://lists.busybox.net/pipermail/buildroot/2020-May/282766.html
-[3] https://github.com/cirosantilli/linux-kernel-module-cheat/issues/108
-[4] https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=gcc/c/Make-lang.in;h=bfae6fd2549c4f728816cd355fa9739dcc08fcde;hb=033eb5671769a4c681a44aad08a454e667e08502#l120
-[5] https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=033eb5671769a4c681a44aad08a454e667e08502
-[6] http://lists.busybox.net/pipermail/buildroot/2020-May/283213.html
-
-Upstream status: https://gcc.gnu.org/pipermail/gcc-patches/2020-May/546248.html
-
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
-Cc: Ben Dakin-Norris <ben.dakin-norris@navtechradar.com>
-Cc: Maxim Kochetkov <fido_max@inbox.ru>
-Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-Cc: Yann E. MORIN <yann.morin.1998@free.fr>
-Cc: Cc: David Malcolm <dmalcolm@gcc.gnu.org>
----
-This patch should be backported to gcc 10 and gcc 9.
----
- gcc/Makefile.in | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/Makefile.in b/gcc/Makefile.in
-index abae872cd63..e2ef3c46afc 100644
---- a/gcc/Makefile.in
-+++ b/gcc/Makefile.in
-@@ -1686,6 +1686,10 @@ $(FULL_DRIVER_NAME): ./xgcc
- rm -f $@
- $(LN_S) $< $@
-
-+# SELFTEST_DEPS need to be set before including language makefile fragments.
-+# Otherwise $(SELFTEST_DEPS) is empty when used from various <LANG>/Make-lang.in.
-+SELFTEST_DEPS = $(GCC_PASSES) stmp-int-hdrs $(srcdir)/testsuite/selftests
-+
- #\f
- # Language makefile fragments.
-
-@@ -1950,8 +1954,6 @@ DEVNULL=$(if $(findstring mingw,$(build)),nul,/dev/null)
- SELFTEST_FLAGS = -nostdinc $(DEVNULL) -S -o $(DEVNULL) \
- -fself-test=$(srcdir)/testsuite/selftests
-
--SELFTEST_DEPS = $(GCC_PASSES) stmp-int-hdrs $(srcdir)/testsuite/selftests
--
- # Run the selftests during the build once we have a driver and the frontend,
- # so that self-test failures are caught as early as possible.
- # Use "s-selftest-FE" to ensure that we only run the selftests if the
---
-2.25.4
-
+++ /dev/null
-From 0d7fe4806d9dce76367c193d5199df6a2b98009f Mon Sep 17 00:00:00 2001
-From: Romain Naour <romain.naour@gmail.com>
-Date: Wed, 20 Jan 2021 23:22:16 +0100
-Subject: [PATCH] Revert "re PR target/92095 (internal error with -O1
- -mcpu=niagara2 -fPIE)"
-
-This reverts commit 6bf2990842388101897b6f465524cbc295ee8cf9.
-
-Building the Buildroot defconfig qemu_sparc_ss10_defconfig using
-gcc 8.4, 9.3 and 10 produce a broken rootfs that trigger illegal
-instruction messages.
-
-gcc 8.3, 9.2 are the latest working gcc version.
-git bisect between gcc 8.4 and 8.4 allowed to identify
-the commit that introcuce the regression.
-
-Reverting this patch allowed to produce a working rootfs.
-
-Signed-off-by: Romain Naour <romain.naour@gmail.com>
-Cc: Eric Botcazou <ebotcazou@gcc.gnu.org>
----
- gcc/config/sparc/sparc-protos.h | 1 -
- gcc/config/sparc/sparc.c | 121 +++++++-----------
- gcc/config/sparc/sparc.md | 5 +-
- .../gcc.c-torture/compile/20191108-1.c | 14 --
- gcc/testsuite/gcc.target/sparc/overflow-3.c | 2 +-
- gcc/testsuite/gcc.target/sparc/overflow-4.c | 2 +-
- gcc/testsuite/gcc.target/sparc/overflow-5.c | 2 +-
- 7 files changed, 53 insertions(+), 94 deletions(-)
- delete mode 100644 gcc/testsuite/gcc.c-torture/compile/20191108-1.c
-
-diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
-index ef1adb69ede..9bdae7b9faa 100644
---- a/gcc/config/sparc/sparc-protos.h
-+++ b/gcc/config/sparc/sparc-protos.h
-@@ -69,7 +69,6 @@ extern void sparc_split_reg_mem (rtx, rtx, machine_mode);
- extern void sparc_split_mem_reg (rtx, rtx, machine_mode);
- extern int sparc_split_reg_reg_legitimate (rtx, rtx);
- extern void sparc_split_reg_reg (rtx, rtx, machine_mode);
--extern const char *output_load_pcrel_sym (rtx *);
- extern const char *output_ubranch (rtx, rtx_insn *);
- extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *);
- extern const char *output_return (rtx_insn *);
-diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
-index a993aab7639..2974d174e93 100644
---- a/gcc/config/sparc/sparc.c
-+++ b/gcc/config/sparc/sparc.c
-@@ -4205,6 +4205,13 @@ eligible_for_sibcall_delay (rtx_insn *trial)
- static bool
- sparc_cannot_force_const_mem (machine_mode mode, rtx x)
- {
-+ /* After IRA has run in PIC mode, it is too late to put anything into the
-+ constant pool if the PIC register hasn't already been initialized. */
-+ if ((lra_in_progress || reload_in_progress)
-+ && flag_pic
-+ && !crtl->uses_pic_offset_table)
-+ return true;
-+
- switch (GET_CODE (x))
- {
- case CONST_INT:
-@@ -4240,11 +4247,9 @@ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
- }
- \f
- /* Global Offset Table support. */
--static GTY(()) rtx got_symbol_rtx = NULL_RTX;
--static GTY(()) rtx got_register_rtx = NULL_RTX;
- static GTY(()) rtx got_helper_rtx = NULL_RTX;
--
--static GTY(()) bool got_helper_needed = false;
-+static GTY(()) rtx got_register_rtx = NULL_RTX;
-+static GTY(()) rtx got_symbol_rtx = NULL_RTX;
-
- /* Return the SYMBOL_REF for the Global Offset Table. */
-
-@@ -4257,6 +4262,27 @@ sparc_got (void)
- return got_symbol_rtx;
- }
-
-+#ifdef HAVE_GAS_HIDDEN
-+# define USE_HIDDEN_LINKONCE 1
-+#else
-+# define USE_HIDDEN_LINKONCE 0
-+#endif
-+
-+static void
-+get_pc_thunk_name (char name[32], unsigned int regno)
-+{
-+ const char *reg_name = reg_names[regno];
-+
-+ /* Skip the leading '%' as that cannot be used in a
-+ symbol name. */
-+ reg_name += 1;
-+
-+ if (USE_HIDDEN_LINKONCE)
-+ sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
-+ else
-+ ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
-+}
-+
- /* Wrapper around the load_pcrel_sym{si,di} patterns. */
-
- static rtx
-@@ -4276,78 +4302,30 @@ gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
- return insn;
- }
-
--/* Output the load_pcrel_sym{si,di} patterns. */
--
--const char *
--output_load_pcrel_sym (rtx *operands)
--{
-- if (flag_delayed_branch)
-- {
-- output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands);
-- output_asm_insn ("call\t%a2", operands);
-- output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands);
-- }
-- else
-- {
-- output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands);
-- output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands);
-- output_asm_insn ("call\t%a2", operands);
-- output_asm_insn (" nop", NULL);
-- }
--
-- if (operands[2] == got_helper_rtx)
-- got_helper_needed = true;
--
-- return "";
--}
--
--#ifdef HAVE_GAS_HIDDEN
--# define USE_HIDDEN_LINKONCE 1
--#else
--# define USE_HIDDEN_LINKONCE 0
--#endif
--
- /* Emit code to load the GOT register. */
-
- void
- load_got_register (void)
- {
-- rtx insn;
-+ if (!got_register_rtx)
-+ got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
-
- if (TARGET_VXWORKS_RTP)
-- {
-- if (!got_register_rtx)
-- got_register_rtx = pic_offset_table_rtx;
--
-- insn = gen_vxworks_load_got ();
-- }
-+ emit_insn (gen_vxworks_load_got ());
- else
- {
-- if (!got_register_rtx)
-- got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
--
- /* The GOT symbol is subject to a PC-relative relocation so we need a
- helper function to add the PC value and thus get the final value. */
- if (!got_helper_rtx)
- {
- char name[32];
--
-- /* Skip the leading '%' as that cannot be used in a symbol name. */
-- if (USE_HIDDEN_LINKONCE)
-- sprintf (name, "__sparc_get_pc_thunk.%s",
-- reg_names[REGNO (got_register_rtx)] + 1);
-- else
-- ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC",
-- REGNO (got_register_rtx));
--
-+ get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
- got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
- }
-
-- insn
-- = gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
-+ emit_insn (gen_load_pcrel_sym (got_register_rtx, sparc_got (),
-+ got_helper_rtx));
- }
--
-- emit_insn (insn);
- }
-
- /* Ensure that we are not using patterns that are not OK with PIC. */
-@@ -5512,7 +5490,7 @@ save_local_or_in_reg_p (unsigned int regno, int leaf_function)
- return true;
-
- /* GOT register (%l7) if needed. */
-- if (got_register_rtx && regno == REGNO (got_register_rtx))
-+ if (regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx)
- return true;
-
- /* If the function accesses prior frames, the frame pointer and the return
-@@ -12555,9 +12533,10 @@ static void
- sparc_file_end (void)
- {
- /* If we need to emit the special GOT helper function, do so now. */
-- if (got_helper_needed)
-+ if (got_helper_rtx)
- {
- const char *name = XSTR (got_helper_rtx, 0);
-+ const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
- #ifdef DWARF2_UNWIND_INFO
- bool do_cfi;
- #endif
-@@ -12594,22 +12573,17 @@ sparc_file_end (void)
- #ifdef DWARF2_UNWIND_INFO
- do_cfi = dwarf2out_do_cfi_asm ();
- if (do_cfi)
-- output_asm_insn (".cfi_startproc", NULL);
-+ fprintf (asm_out_file, "\t.cfi_startproc\n");
- #endif
- if (flag_delayed_branch)
-- {
-- output_asm_insn ("jmp\t%%o7+8", NULL);
-- output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx);
-- }
-+ fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
-+ reg_name, reg_name);
- else
-- {
-- output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx);
-- output_asm_insn ("jmp\t%%o7+8", NULL);
-- output_asm_insn (" nop", NULL);
-- }
-+ fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
-+ reg_name, reg_name);
- #ifdef DWARF2_UNWIND_INFO
- if (do_cfi)
-- output_asm_insn (".cfi_endproc", NULL);
-+ fprintf (asm_out_file, "\t.cfi_endproc\n");
- #endif
- }
-
-@@ -13115,10 +13089,7 @@ sparc_init_pic_reg (void)
- edge entry_edge;
- rtx_insn *seq;
-
-- /* In PIC mode, we need to always initialize the PIC register if optimization
-- is enabled, because we are called from IRA and LRA may later force things
-- to the constant pool for optimization purposes. */
-- if (!flag_pic || (!crtl->uses_pic_offset_table && !optimize))
-+ if (!crtl->uses_pic_offset_table)
- return;
-
- start_sequence ();
-diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
-index 0a6e27ffa83..7af62d599b9 100644
---- a/gcc/config/sparc/sparc.md
-+++ b/gcc/config/sparc/sparc.md
-@@ -1604,7 +1604,10 @@
- (clobber (reg:P O7_REG))]
- "REGNO (operands[0]) == INTVAL (operands[3])"
- {
-- return output_load_pcrel_sym (operands);
-+ if (flag_delayed_branch)
-+ return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
-+ else
-+ return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
- }
- [(set (attr "type") (const_string "multi"))
- (set (attr "length")
-diff --git a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c b/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
-deleted file mode 100644
-index 7929751bb06..00000000000
---- a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
-+++ /dev/null
-@@ -1,14 +0,0 @@
--/* PR target/92095 */
--/* Testcase by Sergei Trofimovich <slyfox@inbox.ru> */
--
--typedef union {
-- double a;
-- int b[2];
--} c;
--
--double d(int e)
--{
-- c f;
-- (&f)->b[0] = 15728640;
-- return e ? -(&f)->a : (&f)->a;
--}
-diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c
-index 52d6ab2b688..86dddfb09e6 100644
---- a/gcc/testsuite/gcc.target/sparc/overflow-3.c
-+++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target lp64 } */
--/* { dg-options "-O -fno-pie" } */
-+/* { dg-options "-O" } */
-
- #include <stdbool.h>
- #include <stdint.h>
-diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c
-index c6121b958c3..019feee335c 100644
---- a/gcc/testsuite/gcc.target/sparc/overflow-4.c
-+++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target lp64 } */
--/* { dg-options "-O -fno-pie -mno-vis3 -mno-vis4" } */
-+/* { dg-options "-O -mno-vis3 -mno-vis4" } */
-
- #include <stdbool.h>
- #include <stdint.h>
-diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c
-index f00283f6e7b..67d4ac38095 100644
---- a/gcc/testsuite/gcc.target/sparc/overflow-5.c
-+++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c
-@@ -1,6 +1,6 @@
- /* { dg-do compile } */
- /* { dg-require-effective-target lp64 } */
--/* { dg-options "-O -fno-pie -mvis3" } */
-+/* { dg-options "-O -mvis3" } */
-
- #include <stdbool.h>
- #include <stdint.h>
---
-2.25.4
-
+++ /dev/null
-From 1af3ab7fc3e4f2ae835c976486e8af0762674af3 Mon Sep 17 00:00:00 2001
-From: Stafford Horne <shorne@gmail.com>
-Date: Sun, 2 May 2021 06:11:44 +0900
-Subject: [PATCH] or1k: Add mcmodel option to handle large GOTs
-
-When building libgeos we get an error with:
-
- linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux':
- crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 against symbol `__cxa_finalize' defined in .text section in
- /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so.
-
-This is caused by GOT code having a limit of 64k. In OpenRISC this
-looks to be the only relocation code pattern to be limited to 64k.
-
-This patch allows specifying a new option -mcmodel=large which can be
-used to generate 2 more instructions to construct 32-bit addresses for
-up to 4G GOTs.
-
-gcc/ChangeLog:
-
- PR 99783
- * config/or1k/or1k-opts.h: New file.
- * config/or1k/or1k.c (or1k_legitimize_address_1, print_reloc):
- Support generating gotha relocations if -mcmodel=large is
- specified.
- * config/or1k/or1k.h (TARGET_CMODEL_SMALL, TARGET_CMODEL_LARGE):
- New macros.
- * config/or1k/or1k.opt (mcmodel=): New option.
- * doc/invoke.text (OpenRISC Options): Document mcmodel.
-
-Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
----
- gcc/config/or1k/or1k-opts.h | 30 ++++++++++++++++++++++++++++++
- gcc/config/or1k/or1k.c | 11 +++++++++--
- gcc/config/or1k/or1k.h | 7 +++++++
- gcc/config/or1k/or1k.opt | 19 +++++++++++++++++++
- gcc/doc/invoke.texi | 13 ++++++++++++-
- 5 files changed, 77 insertions(+), 3 deletions(-)
- create mode 100644 gcc/config/or1k/or1k-opts.h
-
-diff --git a/gcc/config/or1k/or1k-opts.h b/gcc/config/or1k/or1k-opts.h
-new file mode 100644
-index 00000000000..f791b894fdd
---- /dev/null
-+++ b/gcc/config/or1k/or1k-opts.h
-@@ -0,0 +1,30 @@
-+/* Definitions for option handling for OpenRISC.
-+ Copyright (C) 2021 Free Software Foundation, Inc.
-+ Contributed by Stafford Horne.
-+
-+ This file is part of GCC.
-+
-+ GCC is free software; you can redistribute it and/or modify it
-+ under the terms of the GNU General Public License as published
-+ by the Free Software Foundation; either version 3, or (at your
-+ option) any later version.
-+
-+ GCC is distributed in the hope that it will be useful, but WITHOUT
-+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
-+ License for more details.
-+
-+ You should have received a copy of the GNU General Public License
-+ along with GCC; see the file COPYING3. If not see
-+ <http://www.gnu.org/licenses/>. */
-+
-+#ifndef GCC_OR1K_OPTS_H
-+#define GCC_OR1K_OPTS_H
-+
-+/* The OpenRISC code generation models available. */
-+enum or1k_cmodel_type {
-+ CMODEL_SMALL,
-+ CMODEL_LARGE
-+};
-+
-+#endif /* GCC_OR1K_OPTS_H */
-diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
-index fc10fcfabde..df67d72b139 100644
---- a/gcc/config/or1k/or1k.c
-+++ b/gcc/config/or1k/or1k.c
-@@ -750,7 +750,14 @@ or1k_legitimize_address_1 (rtx x, rtx scratch)
- {
- base = gen_sym_unspec (base, UNSPEC_GOT);
- crtl->uses_pic_offset_table = 1;
-- t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
-+ if (TARGET_CMODEL_LARGE)
-+ {
-+ emit_insn (gen_rtx_SET (t1, gen_rtx_HIGH (Pmode, base)));
-+ emit_insn (gen_add3_insn (t1, t1, pic_offset_table_rtx));
-+ t2 = gen_rtx_LO_SUM (Pmode, t1, base);
-+ }
-+ else
-+ t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
- t2 = gen_const_mem (Pmode, t2);
- emit_insn (gen_rtx_SET (t1, t2));
- base = t1;
-@@ -1097,7 +1104,7 @@ print_reloc (FILE *stream, rtx x, HOST_WIDE_INT add, reloc_kind kind)
- no special markup. */
- static const char * const relocs[RKIND_MAX][RTYPE_MAX] = {
- { "lo", "got", "gotofflo", "tpofflo", "gottpofflo", "tlsgdlo" },
-- { "ha", NULL, "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
-+ { "ha", "gotha", "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
- };
- reloc_type type = RTYPE_DIRECT;
-
-diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
-index 6dda230f217..858f30743b7 100644
---- a/gcc/config/or1k/or1k.h
-+++ b/gcc/config/or1k/or1k.h
-@@ -21,6 +21,8 @@
- #ifndef GCC_OR1K_H
- #define GCC_OR1K_H
-
-+#include "config/or1k/or1k-opts.h"
-+
- /* Names to predefine in the preprocessor for this target machine. */
- #define TARGET_CPU_CPP_BUILTINS() \
- do \
-@@ -35,6 +37,11 @@
- } \
- while (0)
-
-+#define TARGET_CMODEL_SMALL \
-+ (or1k_code_model == CMODEL_SMALL)
-+#define TARGET_CMODEL_LARGE \
-+ (or1k_code_model == CMODEL_LARGE)
-+
- /* Storage layout. */
-
- #define DEFAULT_SIGNED_CHAR 1
-diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
-index 7bdbd842dd4..116524c3441 100644
---- a/gcc/config/or1k/or1k.opt
-+++ b/gcc/config/or1k/or1k.opt
-@@ -23,6 +23,9 @@
-
- ; Please try to keep this file in ASCII collating order.
-
-+HeaderInclude
-+config/or1k/or1k-opts.h
-+
- mhard-div
- Target RejectNegative InverseMask(SOFT_DIV)
- Use hardware divide instructions, use -msoft-div for emulation.
-@@ -31,6 +34,22 @@ mhard-mul
- Target RejectNegative InverseMask(SOFT_MUL).
- Use hardware multiply instructions, use -msoft-mul for emulation.
-
-+mcmodel=
-+Target RejectNegative Joined Enum(or1k_cmodel_type) Var(or1k_code_model) Init(CMODEL_SMALL)
-+Specify the code model used for accessing memory addresses. Specifying large
-+enables generating binaries with large global offset tables. By default the
-+value is small.
-+
-+Enum
-+Name(or1k_cmodel_type) Type(enum or1k_cmodel_type)
-+Known code model types (for use with the -mcmodel= option):
-+
-+EnumValue
-+Enum(or1k_cmodel_type) String(small) Value(CMODEL_SMALL)
-+
-+EnumValue
-+Enum(or1k_cmodel_type) String(large) Value(CMODEL_LARGE)
-+
- mcmov
- Target RejectNegative Mask(CMOV)
- Allows generation of binaries which use the l.cmov instruction. If your target
-diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
-index 0ab6c9c6449..0904b2b5a41 100644
---- a/gcc/doc/invoke.texi
-+++ b/gcc/doc/invoke.texi
-@@ -1030,7 +1030,9 @@ Objective-C and Objective-C++ Dialects}.
- @emph{OpenRISC Options}
- @gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol
- -msoft-mul -msoft-div @gol
---mcmov -mror -msext -msfimm -mshftimm}
-+-mcmov -mror -mrori -msext -msfimm -mshftimm @gol
-+-mcmodel=@var{code-model}}
-+
-
- @emph{PDP-11 Options}
- @gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
-@@ -27408,6 +27410,15 @@ MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
- SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
- instruction set extensions.)
-
-+@item -mcmodel=small
-+@opindex mcmodel=small
-+Generate OpenRISC code for the small model: The GOT is limited to 64k. This is
-+the default model.
-+
-+@item -mcmodel=large
-+@opindex mcmodel=large
-+Generate OpenRISC code for the large model: The GOT may grow up to 4G in size.
-+
-
- @item btver1
- CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
---
-2.25.1
-
+++ /dev/null
-From b540f7b916ba7cf2059b84c5cc8d08c67ebe9a0b Mon Sep 17 00:00:00 2001
-From: Stafford Horne <shorne@gmail.com>
-Date: Sun, 2 May 2021 06:11:45 +0900
-Subject: [PATCH] or1k: Use cmodel=large when building crtstuff
-
-When linking gcc runtime objects into large binaries the link may fail
-with the below errors. This will happen even if we are building with
--mcmodel=large.
-
- /home/shorne/work/openrisc/output/host/lib/gcc/or1k-buildroot-linux-uclibc/10.3.0/crtbeginS.o: in function `deregister_tm_clones':
- crtstuff.c:(.text+0x3c): relocation truncated to fit: R_OR1K_GOT16 against undefined symbol `_ITM_deregisterTMCloneTable'
- /home/shorne/work/openrisc/output/host/lib/gcc/or1k-buildroot-linux-uclibc/10.3.0/crtbeginS.o: in function `register_tm_clones':
- crtstuff.c:(.text+0xc0): relocation truncated to fit: R_OR1K_GOT16 against undefined symbol `_ITM_registerTMCloneTable'
-
-This patch builds the gcc crtstuff binaries always with the
--mcmodel=large option to ensure they can be linked into large binaries.
-
-libgcc/ChangeLog:
-
- PR 99783
- * config.host (or1k-*, tmake_file): Add or1k/t-crtstuff.
- * config/or1k/t-crtstuff: New file.
-
-Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
----
- libgcc/config.host | 4 ++--
- libgcc/config/or1k/t-crtstuff | 2 ++
- 2 files changed, 4 insertions(+), 2 deletions(-)
- create mode 100644 libgcc/config/or1k/t-crtstuff
-
-diff --git a/libgcc/config.host b/libgcc/config.host
-index 0f15fda3612..0c21d384e6f 100644
---- a/libgcc/config.host
-+++ b/libgcc/config.host
-@@ -1051,12 +1051,12 @@ nios2-*-*)
- extra_parts="$extra_parts crti.o crtn.o"
- ;;
- or1k-*-linux*)
-- tmake_file="$tmake_file or1k/t-or1k"
-+ tmake_file="$tmake_file or1k/t-or1k or1k/t-crtstuff"
- tmake_file="$tmake_file t-softfp-sfdf t-softfp"
- md_unwind_header=or1k/linux-unwind.h
- ;;
- or1k-*-*)
-- tmake_file="$tmake_file or1k/t-or1k"
-+ tmake_file="$tmake_file or1k/t-or1k or1k/t-crtstuff"
- tmake_file="$tmake_file t-softfp-sfdf t-softfp"
- ;;
- pdp11-*-*)
-diff --git a/libgcc/config/or1k/t-crtstuff b/libgcc/config/or1k/t-crtstuff
-new file mode 100644
-index 00000000000..dcae7f3498e
---- /dev/null
-+++ b/libgcc/config/or1k/t-crtstuff
-@@ -0,0 +1,2 @@
-+# Compile crtbeginS.o and crtendS.o with -mcmodel=large
-+CRTSTUFF_T_CFLAGS_S += -mcmodel=large
---
-2.25.1
-
--- /dev/null
+From 014db5e5febec94e35c13ce89ee6b389328873a1 Mon Sep 17 00:00:00 2001
+From: shorne <shorne@138bc75d-0d04-0410-961f-82ee72b054a4>
+Date: Sat, 31 Aug 2019 06:00:56 +0000
+Subject: [PATCH] or1k: Fix issue with set_got clobbering LR (r9)
+
+When compiling glibc we found that the GOT register was being allocated
+r9 when the instruction was still set_got_tmp. That is a problem
+because r9 is the Link Register (LR) in OpenRISC which is used/clobbered
+in set_got. We cannot use r9 as the GOT register. Also, we cannot
+simply say set_got_tmp clobbers r9 as this is the reason for having the
+temporary set_got_tmp.
+
+Fix by using a register class constraint that does not allow r9 during
+register allocation.
+
+gcc/ChangeLog:
+
+ * config/or1k/constraints.md (t): New constraint.
+ * config/or1k/or1k.h (GOT_REGS): New register class.
+ * config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint.
+
+git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@275242 138bc75d-0d04-0410-961f-82ee72b054a4
+(cherry picked from commit 5b9471ffca25d39635680516ba2ff85295480fc3)
+Signed-off-by: Romain Naour <romain.naour@gmail.com>
+---
+ gcc/config/or1k/constraints.md | 4 ++++
+ gcc/config/or1k/or1k.h | 3 +++
+ gcc/config/or1k/or1k.md | 4 ++--
+ 3 files changed, 9 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md
+index 93da8c058c6..a16b749008f 100644
+--- a/gcc/config/or1k/constraints.md
++++ b/gcc/config/or1k/constraints.md
+@@ -24,6 +24,7 @@
+
+ ; We use:
+ ; c - sibcall registers
++; t - got address registers (excludes LR (r9) which is clobbered by set_got)
+ ; I - constant signed 16-bit
+ ; K - constant unsigned 16-bit
+ ; M - constant signed 16-bit shifted left 16-bits (l.movhi)
+@@ -32,6 +33,9 @@
+ (define_register_constraint "c" "SIBCALL_REGS"
+ "Registers which can hold a sibling call address")
+
++(define_register_constraint "t" "GOT_REGS"
++ "Registers which can be used to store the Global Offset Table (GOT) address.")
++
+ ;; Immediates
+ (define_constraint "I"
+ "A signed 16-bit immediate in the range -32768 to 32767."
+diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
+index 6dda230f217..feee702d89c 100644
+--- a/gcc/config/or1k/or1k.h
++++ b/gcc/config/or1k/or1k.h
+@@ -189,6 +189,7 @@ enum reg_class
+ {
+ NO_REGS,
+ SIBCALL_REGS,
++ GOT_REGS,
+ GENERAL_REGS,
+ FLAG_REGS,
+ ALL_REGS,
+@@ -200,6 +201,7 @@ enum reg_class
+ #define REG_CLASS_NAMES { \
+ "NO_REGS", \
+ "SIBCALL_REGS", \
++ "GOT_REGS", \
+ "GENERAL_REGS", \
+ "FLAG_REGS", \
+ "ALL_REGS" }
+@@ -212,6 +214,7 @@ enum reg_class
+ #define REG_CLASS_CONTENTS \
+ { { 0x00000000, 0x00000000 }, \
+ { SIBCALL_REGS_MASK, 0 }, \
++ { 0xfffffdff, 0x00000000 }, \
+ { 0xffffffff, 0x00000003 }, \
+ { 0x00000000, 0x00000004 }, \
+ { 0xffffffff, 0x00000007 } \
+diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
+index 2dad51cd46b..88f3f02630f 100644
+--- a/gcc/config/or1k/or1k.md
++++ b/gcc/config/or1k/or1k.md
+@@ -595,7 +595,7 @@
+ ;; set_got pattern below. This works because the set_got_tmp insn is the
+ ;; first insn in the stream and that it isn't moved during RA.
+ (define_insn "set_got_tmp"
+- [(set (match_operand:SI 0 "register_operand" "=r")
++ [(set (match_operand:SI 0 "register_operand" "=t")
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))]
+ ""
+ {
+@@ -604,7 +604,7 @@
+
+ ;; The insn to initialize the GOT.
+ (define_insn "set_got"
+- [(set (match_operand:SI 0 "register_operand" "=r")
++ [(set (match_operand:SI 0 "register_operand" "=t")
+ (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
+ (clobber (reg:SI LR_REGNUM))]
+ ""
+--
+2.31.1
+
--- /dev/null
+From f80e9941739fb3973b61fc6a5abddef5ad2faf73 Mon Sep 17 00:00:00 2001
+From: Bernd Kuhls <bernd.kuhls@t-online.de>
+Date: Fri, 27 Mar 2020 21:23:53 +0100
+Subject: [PATCH] gcc: define _REENTRANT for OpenRISC when -pthread is passed
+
+The detection of pthread support fails on OpenRISC unless _REENTRANT
+is defined. Added the CPP_SPEC definition to correct this.
+
+Patch sent upstream: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94372
+
+Signed-off-by: Bernd Kuhls <bernd.kuhls@t-online.de>
+---
+ gcc/config/or1k/linux.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/gcc/config/or1k/linux.h b/gcc/config/or1k/linux.h
+index cbdc781418f..36303af892c 100644
+--- a/gcc/config/or1k/linux.h
++++ b/gcc/config/or1k/linux.h
+@@ -32,6 +32,8 @@
+ #undef MUSL_DYNAMIC_LINKER
+ #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-or1k.so.1"
+
++#define CPP_SPEC "%{pthread:-D_REENTRANT}"
++
+ #undef LINK_SPEC
+ #define LINK_SPEC "%{h*} \
+ %{static:-Bstatic} \
+--
+2.31.1
+
--- /dev/null
+From 1107ecc3e8af31adc7bbd4e08c0614836bd1cebd Mon Sep 17 00:00:00 2001
+From: Romain Naour <romain.naour@gmail.com>
+Date: Wed, 20 Jan 2021 23:22:16 +0100
+Subject: [PATCH] Revert "re PR target/92095 (internal error with -O1
+ -mcpu=niagara2 -fPIE)"
+
+This reverts commit 6bf2990842388101897b6f465524cbc295ee8cf9.
+
+Building the Buildroot defconfig qemu_sparc_ss10_defconfig using
+gcc 8.4, 9.3 and 10 produce a broken rootfs that trigger illegal
+instruction messages.
+
+gcc 8.3, 9.2 are the latest working gcc version.
+git bisect between gcc 8.4 and 8.4 allowed to identify
+the commit that introcuce the regression.
+
+Reverting this patch allowed to produce a working rootfs.
+
+Signed-off-by: Romain Naour <romain.naour@gmail.com>
+Cc: Eric Botcazou <ebotcazou@gcc.gnu.org>
+---
+ gcc/config/sparc/sparc-protos.h | 1 -
+ gcc/config/sparc/sparc.c | 121 +++++++-----------
+ gcc/config/sparc/sparc.md | 5 +-
+ .../gcc.c-torture/compile/20191108-1.c | 14 --
+ gcc/testsuite/gcc.target/sparc/overflow-3.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-4.c | 2 +-
+ gcc/testsuite/gcc.target/sparc/overflow-5.c | 2 +-
+ 7 files changed, 53 insertions(+), 94 deletions(-)
+ delete mode 100644 gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+
+diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
+index f1c120c4860..f4b6f00a7b1 100644
+--- a/gcc/config/sparc/sparc-protos.h
++++ b/gcc/config/sparc/sparc-protos.h
+@@ -69,7 +69,6 @@ extern void sparc_split_reg_mem (rtx, rtx, machine_mode);
+ extern void sparc_split_mem_reg (rtx, rtx, machine_mode);
+ extern int sparc_split_reg_reg_legitimate (rtx, rtx);
+ extern void sparc_split_reg_reg (rtx, rtx, machine_mode);
+-extern const char *output_load_pcrel_sym (rtx *);
+ extern const char *output_ubranch (rtx, rtx_insn *);
+ extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *);
+ extern const char *output_return (rtx_insn *);
+diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
+index 0553dc501e6..516dcf96d7b 100644
+--- a/gcc/config/sparc/sparc.c
++++ b/gcc/config/sparc/sparc.c
+@@ -4170,6 +4170,13 @@ eligible_for_sibcall_delay (rtx_insn *trial)
+ static bool
+ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ {
++ /* After IRA has run in PIC mode, it is too late to put anything into the
++ constant pool if the PIC register hasn't already been initialized. */
++ if ((lra_in_progress || reload_in_progress)
++ && flag_pic
++ && !crtl->uses_pic_offset_table)
++ return true;
++
+ switch (GET_CODE (x))
+ {
+ case CONST_INT:
+@@ -4205,11 +4212,9 @@ sparc_cannot_force_const_mem (machine_mode mode, rtx x)
+ }
+ \f
+ /* Global Offset Table support. */
+-static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+-static GTY(()) rtx got_register_rtx = NULL_RTX;
+ static GTY(()) rtx got_helper_rtx = NULL_RTX;
+-
+-static GTY(()) bool got_helper_needed = false;
++static GTY(()) rtx got_register_rtx = NULL_RTX;
++static GTY(()) rtx got_symbol_rtx = NULL_RTX;
+
+ /* Return the SYMBOL_REF for the Global Offset Table. */
+
+@@ -4222,6 +4227,27 @@ sparc_got (void)
+ return got_symbol_rtx;
+ }
+
++#ifdef HAVE_GAS_HIDDEN
++# define USE_HIDDEN_LINKONCE 1
++#else
++# define USE_HIDDEN_LINKONCE 0
++#endif
++
++static void
++get_pc_thunk_name (char name[32], unsigned int regno)
++{
++ const char *reg_name = reg_names[regno];
++
++ /* Skip the leading '%' as that cannot be used in a
++ symbol name. */
++ reg_name += 1;
++
++ if (USE_HIDDEN_LINKONCE)
++ sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
++ else
++ ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
++}
++
+ /* Wrapper around the load_pcrel_sym{si,di} patterns. */
+
+ static rtx
+@@ -4241,78 +4267,30 @@ gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2)
+ return insn;
+ }
+
+-/* Output the load_pcrel_sym{si,di} patterns. */
+-
+-const char *
+-output_load_pcrel_sym (rtx *operands)
+-{
+- if (flag_delayed_branch)
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" add\t%0, %%lo(%a1+4), %0", operands);
+- }
+- else
+- {
+- output_asm_insn ("sethi\t%%hi(%a1-8), %0", operands);
+- output_asm_insn ("add\t%0, %%lo(%a1-4), %0", operands);
+- output_asm_insn ("call\t%a2", operands);
+- output_asm_insn (" nop", NULL);
+- }
+-
+- if (operands[2] == got_helper_rtx)
+- got_helper_needed = true;
+-
+- return "";
+-}
+-
+-#ifdef HAVE_GAS_HIDDEN
+-# define USE_HIDDEN_LINKONCE 1
+-#else
+-# define USE_HIDDEN_LINKONCE 0
+-#endif
+-
+ /* Emit code to load the GOT register. */
+
+ void
+ load_got_register (void)
+ {
+- rtx insn;
++ if (!got_register_rtx)
++ got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+
+ if (TARGET_VXWORKS_RTP)
+- {
+- if (!got_register_rtx)
+- got_register_rtx = pic_offset_table_rtx;
+-
+- insn = gen_vxworks_load_got ();
+- }
++ emit_insn (gen_vxworks_load_got ());
+ else
+ {
+- if (!got_register_rtx)
+- got_register_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
+-
+ /* The GOT symbol is subject to a PC-relative relocation so we need a
+ helper function to add the PC value and thus get the final value. */
+ if (!got_helper_rtx)
+ {
+ char name[32];
+-
+- /* Skip the leading '%' as that cannot be used in a symbol name. */
+- if (USE_HIDDEN_LINKONCE)
+- sprintf (name, "__sparc_get_pc_thunk.%s",
+- reg_names[REGNO (got_register_rtx)] + 1);
+- else
+- ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC",
+- REGNO (got_register_rtx));
+-
++ get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
+ got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
+ }
+
+- insn
+- = gen_load_pcrel_sym (got_register_rtx, sparc_got (), got_helper_rtx);
++ emit_insn (gen_load_pcrel_sym (got_register_rtx, sparc_got (),
++ got_helper_rtx));
+ }
+-
+- emit_insn (insn);
+ }
+
+ /* Ensure that we are not using patterns that are not OK with PIC. */
+@@ -5477,7 +5455,7 @@ save_local_or_in_reg_p (unsigned int regno, int leaf_function)
+ return true;
+
+ /* GOT register (%l7) if needed. */
+- if (got_register_rtx && regno == REGNO (got_register_rtx))
++ if (regno == GLOBAL_OFFSET_TABLE_REGNUM && got_register_rtx)
+ return true;
+
+ /* If the function accesses prior frames, the frame pointer and the return
+@@ -12520,9 +12498,10 @@ static void
+ sparc_file_end (void)
+ {
+ /* If we need to emit the special GOT helper function, do so now. */
+- if (got_helper_needed)
++ if (got_helper_rtx)
+ {
+ const char *name = XSTR (got_helper_rtx, 0);
++ const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
+ #ifdef DWARF2_UNWIND_INFO
+ bool do_cfi;
+ #endif
+@@ -12559,22 +12538,17 @@ sparc_file_end (void)
+ #ifdef DWARF2_UNWIND_INFO
+ do_cfi = dwarf2out_do_cfi_asm ();
+ if (do_cfi)
+- output_asm_insn (".cfi_startproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_startproc\n");
+ #endif
+ if (flag_delayed_branch)
+- {
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" add\t%%o7, %0, %0", &got_register_rtx);
+- }
++ fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
++ reg_name, reg_name);
+ else
+- {
+- output_asm_insn ("add\t%%o7, %0, %0", &got_register_rtx);
+- output_asm_insn ("jmp\t%%o7+8", NULL);
+- output_asm_insn (" nop", NULL);
+- }
++ fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
++ reg_name, reg_name);
+ #ifdef DWARF2_UNWIND_INFO
+ if (do_cfi)
+- output_asm_insn (".cfi_endproc", NULL);
++ fprintf (asm_out_file, "\t.cfi_endproc\n");
+ #endif
+ }
+
+@@ -13080,10 +13054,7 @@ sparc_init_pic_reg (void)
+ edge entry_edge;
+ rtx_insn *seq;
+
+- /* In PIC mode, we need to always initialize the PIC register if optimization
+- is enabled, because we are called from IRA and LRA may later force things
+- to the constant pool for optimization purposes. */
+- if (!flag_pic || (!crtl->uses_pic_offset_table && !optimize))
++ if (!crtl->uses_pic_offset_table)
+ return;
+
+ start_sequence ();
+diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
+index d9ef79c13cc..6dbd054f1c7 100644
+--- a/gcc/config/sparc/sparc.md
++++ b/gcc/config/sparc/sparc.md
+@@ -1601,7 +1601,10 @@
+ (clobber (reg:P O7_REG))]
+ "REGNO (operands[0]) == INTVAL (operands[3])"
+ {
+- return output_load_pcrel_sym (operands);
++ if (flag_delayed_branch)
++ return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
++ else
++ return "sethi\t%%hi(%a1-8), %0\n\tadd\t%0, %%lo(%a1-4), %0\n\tcall\t%a2\n\t nop";
+ }
+ [(set (attr "type") (const_string "multi"))
+ (set (attr "length")
+diff --git a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c b/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
+deleted file mode 100644
+index 7929751bb06..00000000000
+--- a/gcc/testsuite/gcc.c-torture/compile/20191108-1.c
++++ /dev/null
+@@ -1,14 +0,0 @@
+-/* PR target/92095 */
+-/* Testcase by Sergei Trofimovich <slyfox@inbox.ru> */
+-
+-typedef union {
+- double a;
+- int b[2];
+-} c;
+-
+-double d(int e)
+-{
+- c f;
+- (&f)->b[0] = 15728640;
+- return e ? -(&f)->a : (&f)->a;
+-}
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-3.c b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+index 52d6ab2b688..86dddfb09e6 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-3.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-3.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie" } */
++/* { dg-options "-O" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-4.c b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+index c6121b958c3..019feee335c 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-4.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-4.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie -mno-vis3 -mno-vis4" } */
++/* { dg-options "-O -mno-vis3 -mno-vis4" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+diff --git a/gcc/testsuite/gcc.target/sparc/overflow-5.c b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+index f00283f6e7b..67d4ac38095 100644
+--- a/gcc/testsuite/gcc.target/sparc/overflow-5.c
++++ b/gcc/testsuite/gcc.target/sparc/overflow-5.c
+@@ -1,6 +1,6 @@
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+-/* { dg-options "-O -fno-pie -mvis3" } */
++/* { dg-options "-O -mvis3" } */
+
+ #include <stdbool.h>
+ #include <stdint.h>
+--
+2.31.1
+
--- /dev/null
+From 90b202b59fa2bdb68314a23471b32d3e16602bc8 Mon Sep 17 00:00:00 2001
+From: Stafford Horne <shorne@gmail.com>
+Date: Sun, 2 May 2021 06:11:44 +0900
+Subject: [PATCH] or1k: Add mcmodel option to handle large GOTs
+
+When building libgeos we get an error with:
+
+ linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux':
+ crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 against symbol `__cxa_finalize' defined in .text section in
+ /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so.
+
+This is caused by GOT code having a limit of 64k. In OpenRISC this
+looks to be the only relocation code pattern to be limited to 64k.
+
+This patch allows specifying a new option -mcmodel=large which can be
+used to generate 2 more instructions to construct 32-bit addresses for
+up to 4G GOTs.
+
+gcc/ChangeLog:
+
+ PR 99783
+ * config/or1k/or1k-opts.h: New file.
+ * config/or1k/or1k.c (or1k_legitimize_address_1, print_reloc):
+ Support generating gotha relocations if -mcmodel=large is
+ specified.
+ * config/or1k/or1k.h (TARGET_CMODEL_SMALL, TARGET_CMODEL_LARGE):
+ New macros.
+ * config/or1k/or1k.opt (mcmodel=): New option.
+ * doc/invoke.text (OpenRISC Options): Document mcmodel.
+
+Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
+---
+ gcc/config/or1k/or1k-opts.h | 30 ++++++++++++++++++++++++++++++
+ gcc/config/or1k/or1k.c | 11 +++++++++--
+ gcc/config/or1k/or1k.h | 7 +++++++
+ gcc/config/or1k/or1k.opt | 19 +++++++++++++++++++
+ gcc/doc/invoke.texi | 13 ++++++++++++-
+ 5 files changed, 77 insertions(+), 3 deletions(-)
+ create mode 100644 gcc/config/or1k/or1k-opts.h
+
+diff --git a/gcc/config/or1k/or1k-opts.h b/gcc/config/or1k/or1k-opts.h
+new file mode 100644
+index 00000000000..f791b894fdd
+--- /dev/null
++++ b/gcc/config/or1k/or1k-opts.h
+@@ -0,0 +1,30 @@
++/* Definitions for option handling for OpenRISC.
++ Copyright (C) 2021 Free Software Foundation, Inc.
++ Contributed by Stafford Horne.
++
++ This file is part of GCC.
++
++ GCC is free software; you can redistribute it and/or modify it
++ under the terms of the GNU General Public License as published
++ by the Free Software Foundation; either version 3, or (at your
++ option) any later version.
++
++ GCC is distributed in the hope that it will be useful, but WITHOUT
++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
++ License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with GCC; see the file COPYING3. If not see
++ <http://www.gnu.org/licenses/>. */
++
++#ifndef GCC_OR1K_OPTS_H
++#define GCC_OR1K_OPTS_H
++
++/* The OpenRISC code generation models available. */
++enum or1k_cmodel_type {
++ CMODEL_SMALL,
++ CMODEL_LARGE
++};
++
++#endif /* GCC_OR1K_OPTS_H */
+diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
+index fc10fcfabde..df67d72b139 100644
+--- a/gcc/config/or1k/or1k.c
++++ b/gcc/config/or1k/or1k.c
+@@ -750,7 +750,14 @@ or1k_legitimize_address_1 (rtx x, rtx scratch)
+ {
+ base = gen_sym_unspec (base, UNSPEC_GOT);
+ crtl->uses_pic_offset_table = 1;
+- t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
++ if (TARGET_CMODEL_LARGE)
++ {
++ emit_insn (gen_rtx_SET (t1, gen_rtx_HIGH (Pmode, base)));
++ emit_insn (gen_add3_insn (t1, t1, pic_offset_table_rtx));
++ t2 = gen_rtx_LO_SUM (Pmode, t1, base);
++ }
++ else
++ t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
+ t2 = gen_const_mem (Pmode, t2);
+ emit_insn (gen_rtx_SET (t1, t2));
+ base = t1;
+@@ -1097,7 +1104,7 @@ print_reloc (FILE *stream, rtx x, HOST_WIDE_INT add, reloc_kind kind)
+ no special markup. */
+ static const char * const relocs[RKIND_MAX][RTYPE_MAX] = {
+ { "lo", "got", "gotofflo", "tpofflo", "gottpofflo", "tlsgdlo" },
+- { "ha", NULL, "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
++ { "ha", "gotha", "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
+ };
+ reloc_type type = RTYPE_DIRECT;
+
+diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
+index feee702d89c..dbaf0d0fe4c 100644
+--- a/gcc/config/or1k/or1k.h
++++ b/gcc/config/or1k/or1k.h
+@@ -21,6 +21,8 @@
+ #ifndef GCC_OR1K_H
+ #define GCC_OR1K_H
+
++#include "config/or1k/or1k-opts.h"
++
+ /* Names to predefine in the preprocessor for this target machine. */
+ #define TARGET_CPU_CPP_BUILTINS() \
+ do \
+@@ -35,6 +37,11 @@
+ } \
+ while (0)
+
++#define TARGET_CMODEL_SMALL \
++ (or1k_code_model == CMODEL_SMALL)
++#define TARGET_CMODEL_LARGE \
++ (or1k_code_model == CMODEL_LARGE)
++
+ /* Storage layout. */
+
+ #define DEFAULT_SIGNED_CHAR 1
+diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
+index 7bdbd842dd4..116524c3441 100644
+--- a/gcc/config/or1k/or1k.opt
++++ b/gcc/config/or1k/or1k.opt
+@@ -23,6 +23,9 @@
+
+ ; Please try to keep this file in ASCII collating order.
+
++HeaderInclude
++config/or1k/or1k-opts.h
++
+ mhard-div
+ Target RejectNegative InverseMask(SOFT_DIV)
+ Use hardware divide instructions, use -msoft-div for emulation.
+@@ -31,6 +34,22 @@ mhard-mul
+ Target RejectNegative InverseMask(SOFT_MUL).
+ Use hardware multiply instructions, use -msoft-mul for emulation.
+
++mcmodel=
++Target RejectNegative Joined Enum(or1k_cmodel_type) Var(or1k_code_model) Init(CMODEL_SMALL)
++Specify the code model used for accessing memory addresses. Specifying large
++enables generating binaries with large global offset tables. By default the
++value is small.
++
++Enum
++Name(or1k_cmodel_type) Type(enum or1k_cmodel_type)
++Known code model types (for use with the -mcmodel= option):
++
++EnumValue
++Enum(or1k_cmodel_type) String(small) Value(CMODEL_SMALL)
++
++EnumValue
++Enum(or1k_cmodel_type) String(large) Value(CMODEL_LARGE)
++
+ mcmov
+ Target RejectNegative Mask(CMOV)
+ Allows generation of binaries which use the l.cmov instruction. If your target
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index 7b5f6e03d9f..683c64417af 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -1032,7 +1032,9 @@ Objective-C and Objective-C++ Dialects}.
+ @emph{OpenRISC Options}
+ @gccoptlist{-mboard=@var{name} -mnewlib -mhard-mul -mhard-div @gol
+ -msoft-mul -msoft-div @gol
+--mcmov -mror -msext -msfimm -mshftimm}
++-mcmov -mror -mrori -msext -msfimm -mshftimm @gol
++-mcmodel=@var{code-model}}
++
+
+ @emph{PDP-11 Options}
+ @gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
+@@ -27462,6 +27464,15 @@ MWAITX, SHA, CLZERO, AES, PCL_MUL, CX16, MOVBE, MMX, SSE, SSE2, SSE3, SSE4A,
+ SSSE3, SSE4.1, SSE4.2, ABM, XSAVEC, XSAVES, CLFLUSHOPT, POPCNT, and 64-bit
+ instruction set extensions.)
+
++@item -mcmodel=small
++@opindex mcmodel=small
++Generate OpenRISC code for the small model: The GOT is limited to 64k. This is
++the default model.
++
++@item -mcmodel=large
++@opindex mcmodel=large
++Generate OpenRISC code for the large model: The GOT may grow up to 4G in size.
++
+
+ @item btver1
+ CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
+--
+2.31.1
+
--- /dev/null
+From d64a757040fe36b0d9dc65d24107c656f66bc8e5 Mon Sep 17 00:00:00 2001
+From: Stafford Horne <shorne@gmail.com>
+Date: Sun, 2 May 2021 06:11:45 +0900
+Subject: [PATCH] or1k: Use cmodel=large when building crtstuff
+
+When linking gcc runtime objects into large binaries the link may fail
+with the below errors. This will happen even if we are building with
+-mcmodel=large.
+
+ /home/shorne/work/openrisc/output/host/lib/gcc/or1k-buildroot-linux-uclibc/10.3.0/crtbeginS.o: in function `deregister_tm_clones':
+ crtstuff.c:(.text+0x3c): relocation truncated to fit: R_OR1K_GOT16 against undefined symbol `_ITM_deregisterTMCloneTable'
+ /home/shorne/work/openrisc/output/host/lib/gcc/or1k-buildroot-linux-uclibc/10.3.0/crtbeginS.o: in function `register_tm_clones':
+ crtstuff.c:(.text+0xc0): relocation truncated to fit: R_OR1K_GOT16 against undefined symbol `_ITM_registerTMCloneTable'
+
+This patch builds the gcc crtstuff binaries always with the
+-mcmodel=large option to ensure they can be linked into large binaries.
+
+libgcc/ChangeLog:
+
+ PR 99783
+ * config.host (or1k-*, tmake_file): Add or1k/t-crtstuff.
+ * config/or1k/t-crtstuff: New file.
+
+Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
+---
+ libgcc/config.host | 4 ++--
+ libgcc/config/or1k/t-crtstuff | 2 ++
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+ create mode 100644 libgcc/config/or1k/t-crtstuff
+
+diff --git a/libgcc/config.host b/libgcc/config.host
+index bdbf77a3e62..bfb45a90630 100644
+--- a/libgcc/config.host
++++ b/libgcc/config.host
+@@ -1061,12 +1061,12 @@ nios2-*-*)
+ extra_parts="$extra_parts crti.o crtn.o"
+ ;;
+ or1k-*-linux*)
+- tmake_file="$tmake_file or1k/t-or1k"
++ tmake_file="$tmake_file or1k/t-or1k or1k/t-crtstuff"
+ tmake_file="$tmake_file t-softfp-sfdf t-softfp"
+ md_unwind_header=or1k/linux-unwind.h
+ ;;
+ or1k-*-*)
+- tmake_file="$tmake_file or1k/t-or1k"
++ tmake_file="$tmake_file or1k/t-or1k or1k/t-crtstuff"
+ tmake_file="$tmake_file t-softfp-sfdf t-softfp"
+ ;;
+ pdp11-*-*)
+diff --git a/libgcc/config/or1k/t-crtstuff b/libgcc/config/or1k/t-crtstuff
+new file mode 100644
+index 00000000000..dcae7f3498e
+--- /dev/null
++++ b/libgcc/config/or1k/t-crtstuff
+@@ -0,0 +1,2 @@
++# Compile crtbeginS.o and crtendS.o with -mcmodel=large
++CRTSTUFF_T_CFLAGS_S += -mcmodel=large
+--
+2.31.1
+
config BR2_GCC_VERSION
string
default "8.4.0" if BR2_GCC_VERSION_8_X
- default "9.3.0" if BR2_GCC_VERSION_9_X
+ default "9.4.0" if BR2_GCC_VERSION_9_X
default "10.3.0" if BR2_GCC_VERSION_10_X
default "arc-2020.09-release" if BR2_GCC_VERSION_ARC
default "48152afb96c59733d5bc79e3399bb7b3d4b44266" if BR2_GCC_VERSION_CSKY
# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-8.4.0/sha512.sum
sha512 6de904f552a02de33b11ef52312bb664396efd7e1ce3bbe37bfad5ef617f133095b3767b4804bc7fe78df335cb53bc83f1ac055baed40979ce4c2c3e46b70280 gcc-8.4.0.tar.xz
-# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-9.3.0/sha512.sum
-sha512 4b9e3639eef6e623747a22c37a904b4750c93b6da77cf3958d5047e9b5ebddb7eebe091cc16ca0a227c0ecbd2bf3b984b221130f269a97ee4cc18f9cf6c444de gcc-9.3.0.tar.xz
+# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-9.4.0/sha512.sum
+sha512 dfd3500bf21784b8351a522d53463cf362ede66b0bc302edf350bb44e94418497a8b4b797b6af8ca9b2eeb746b3b115d9c3698381b989546e9151b4496415624 gcc-9.4.0.tar.xz
# From ftp://gcc.gnu.org/pub/gcc/releases/gcc-10.3.0/sha512.sum
sha512 2b2dd7453d48a398c29eaebd1422b70341001b8c90a62aee51e83344e7fdd8a8e45f82a4a9165bd7edc76dada912c932f4b6632c5636760fec4c5d7e402b3f86 gcc-10.3.0.tar.xz
projects / buildroot.git / commitdiff