if (p->function_trace_start == 0) {
functionTracingEnabled = true;
} else {
- typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
- Event *event = new wrap(this, true);
+ Event *event = new EventFunctionWrapper(
+ [this]{ enableFunctionTrace(); }, name(), true);
schedule(event, p->function_trace_start);
}
}
thread->startup();
Event *startupEvent(
- new EventWrapper<BaseKvmCPU,
- &BaseKvmCPU::startupThread>(this, true));
+ new EventFunctionWrapper([this]{ startupThread(); }, name(), true));
schedule(startupEvent, curTick());
}
ElasticTrace::ElasticTrace(const ElasticTraceParams* params)
: ProbeListenerObject(params),
- regEtraceListenersEvent(this),
+ regEtraceListenersEvent([this]{ regEtraceListeners(); }, name()),
firstWin(true),
lastClearedSeqNum(0),
depWindowSize(params->depWindowSize),
void regStats();
/** Event to trigger registering this listener for all probe points. */
- EventWrapper<ElasticTrace,
- &ElasticTrace::regEtraceListeners> regEtraceListenersEvent;
+ EventFunctionWrapper regEtraceListenersEvent;
private:
/**
TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
: BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
- fetchEvent(this)
+ fetchEvent([this]{ fetch(); }, name())
{
_status = Idle;
}
public:
TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
- : MasterPort(_name, _cpu), cpu(_cpu), retryRespEvent(this)
+ : MasterPort(_name, _cpu), cpu(_cpu),
+ retryRespEvent([this]{ sendRetryResp(); }, name())
{ }
protected:
void schedule(PacketPtr _pkt, Tick t);
};
- EventWrapper<MasterPort, &MasterPort::sendRetryResp> retryRespEvent;
+ EventFunctionWrapper retryRespEvent;
};
class IcachePort : public TimingCPUPort
private:
- typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
- FetchEvent fetchEvent;
+ EventFunctionWrapper fetchEvent;
struct IprEvent : Event {
Packet *pkt;
MemTest::MemTest(const Params *p)
: MemObject(p),
- tickEvent(this),
- noRequestEvent(this),
- noResponseEvent(this),
+ tickEvent([this]{ tick(); }, name()),
+ noRequestEvent([this]{ noRequest(); }, name()),
+ noResponseEvent([this]{ noResponse(); }, name()),
port("port", *this),
retryPkt(nullptr),
size(p->size),
void tick();
- EventWrapper<MemTest, &MemTest::tick> tickEvent;
+ EventFunctionWrapper tickEvent;
void noRequest();
- EventWrapper<MemTest, &MemTest::noRequest> noRequestEvent;
+ EventFunctionWrapper noRequestEvent;
void noResponse();
- EventWrapper<MemTest, &MemTest::noResponse> noResponseEvent;
+ EventFunctionWrapper noResponseEvent;
class CpuPort : public MasterPort
{
configFile(p->config_file),
elasticReq(p->elastic_req),
progressCheck(p->progress_check),
- noProgressEvent(this),
+ noProgressEvent([this]{ noProgress(); }, name()),
nextTransitionTick(0),
nextPacketTick(0),
currState(0),
port(name() + ".port", *this),
retryPkt(NULL),
retryPktTick(0),
- updateEvent(this),
+ updateEvent([this]{ update(); }, name()),
numSuppressed(0)
{
}
/**
* Event to keep track of our progress, or lack thereof.
*/
- EventWrapper<TrafficGen, &TrafficGen::noProgress> noProgressEvent;
+ EventFunctionWrapper noProgressEvent;
/** Time of next transition */
Tick nextTransitionTick;
Tick retryPktTick;
/** Event for scheduling updates */
- EventWrapper<TrafficGen, &TrafficGen::update> updateEvent;
+ EventFunctionWrapper updateEvent;
uint64_t numSuppressed;
icacheGen(*this, ".iside", icachePort, instMasterID, instTraceFile),
dcacheGen(*this, ".dside", dcachePort, dataMasterID, dataTraceFile,
params),
- icacheNextEvent(this),
- dcacheNextEvent(this),
+ icacheNextEvent([this]{ schedIcacheNext(); }, name()),
+ dcacheNextEvent([this]{ schedDcacheNext(); }, name()),
oneTraceComplete(false),
traceOffset(0),
execCompleteEvent(nullptr),
void schedDcacheNext();
/** Event for the control flow method schedIcacheNext() */
- EventWrapper<TraceCPU, &TraceCPU::schedIcacheNext> icacheNextEvent;
+ EventFunctionWrapper icacheNextEvent;
/** Event for the control flow method schedDcacheNext() */
- EventWrapper<TraceCPU, &TraceCPU::schedDcacheNext> dcacheNextEvent;
+ EventFunctionWrapper dcacheNextEvent;
/** This is called when either generator finishes executing from the trace */
void checkAndSchedExitEvent();
GpuTLB::GpuTLB(const Params *p)
: MemObject(p), configAddress(0), size(p->size),
- cleanupEvent(this, false, Event::Maximum_Pri), exitEvent(this)
+ cleanupEvent([this]{ cleanup(); }, name(), false,
+ Event::Maximum_Pri),
+ exitEvent([this]{ exitCallback(); }, name())
{
assoc = p->assoc;
assert(assoc <= size);
// free memory and do the required clean-up
void cleanup();
- EventWrapper<GpuTLB, &GpuTLB::cleanup> cleanupEvent;
+ EventFunctionWrapper cleanupEvent;
/**
* This hash map will use the virtual page address as a key
// Called at the end of simulation to dump page access stats.
void exitCallback();
- EventWrapper<GpuTLB, &GpuTLB::exitCallback> exitEvent;
+ EventFunctionWrapper exitEvent;
};
}