mixxeo: swap pairs 0 and 1 on DVI1

diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py
index cfd1d144cb6434e50f5eb33c6cf43f155cfd907e..1eb5d83e2f0a7f7cc876576060fe7dc318f93788 100644 (file)
--- a/mibuild/platforms/mixxeo.py
+++ b/mibuild/platforms/mixxeo.py
@@ -101,10 +101,10 @@ _io = [
        ("dvi_in", 1,
                Subsignal("clk_p", Pins("C11"), IOStandard("TMDS_33")),
                Subsignal("clk_n", Pins("A11"), IOStandard("TMDS_33")),
-               Subsignal("data0_p", Pins("C17"), IOStandard("TMDS_33")),
-               Subsignal("data0_n", Pins("A17"), IOStandard("TMDS_33")),
-               Subsignal("data1_p", Pins("B18"), IOStandard("TMDS_33")),
-               Subsignal("data1_n", Pins("A18"), IOStandard("TMDS_33")),
+               Subsignal("data0_p", Pins("B18"), IOStandard("TMDS_33")),
+               Subsignal("data0_n", Pins("A18"), IOStandard("TMDS_33")),
+               Subsignal("data1_p", Pins("C17"), IOStandard("TMDS_33")),
+               Subsignal("data1_n", Pins("A17"), IOStandard("TMDS_33")),
                Subsignal("data2_p", Pins("E16"), IOStandard("TMDS_33")),
                Subsignal("data2_n", Pins("D17"), IOStandard("TMDS_33")),
                Subsignal("scl", Pins("F17"), IOStandard("LVCMOS33")),