| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
| 32 | E VSS_2 | |
-| 33 | E SDR_SDRAD10 | |
-| 34 | E SDR_SDRAD11 | |
-| 35 | E SDR_SDRAD12 | |
+| 33 | E SDR_AD10 | |
+| 34 | E SDR_AD11 | |
+| 35 | E SDR_AD12 | |
| 36 | E SDR_DQM1 | |
| 37 | E SDR_D8 | |
| 38 | E SDR_D9 | |
| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
| 64 | S VSS_4 | |
-| 65 | S CLK_0 | |
-| 66 | S RST_0 | |
-| 68 | S MSPI0_CK | |
-| 69 | S MSPI0_NSS | |
-| 70 | S MSPI0_MOSI | |
-| 71 | S MSPI0_MISO | |
-| 72 | S UART0_TX | |
-| 73 | S UART0_RX | |
-| 78 | S GPIOS_S0 | |
-| 79 | S GPIOS_S1 | |
-| 80 | S GPIOS_S2 | |
-| 81 | S GPIOS_S3 | |
-| 82 | S GPIOS_S4 | |
-| 83 | S GPIOS_S5 | |
-| 84 | S GPIOS_S6 | |
-| 85 | S GPIOS_S7 | |
-| 95 | S VDD_4 | |
+| 65 | S SYS_CLK | |
+| 66 | S SYS_RST | |
+| 67 | S SYS_PLLCLK | |
+| 68 | S SYS_PLLOUT | |
+| 69 | S SYS_CSEL0 | |
+| 70 | S SYS_CSEL1 | |
+| 71 | S SYS_CSEL2 | |
+| 72 | S VDD_4 | |
+| 73 | S TWI_SDA | |
+| 74 | S TWI_SCL | |
+| 79 | S MSPI0_CK | |
+| 80 | S MSPI0_NSS | |
+| 81 | S MSPI0_MOSI | |
+| 82 | S MSPI0_MISO | |
+| 84 | S UART0_TX | |
+| 85 | S UART0_RX | |
+| 86 | S VSS_5 | |
+| 87 | S GPIOS_S0 | |
+| 88 | S GPIOS_S1 | |
+| 89 | S GPIOS_S2 | |
+| 90 | S GPIOS_S3 | |
+| 91 | S GPIOS_S4 | |
+| 92 | S GPIOS_S5 | |
+| 93 | S GPIOS_S6 | |
+| 94 | S GPIOS_S7 | |
+| 95 | S VDD_5 | |
## Bank W (32 pins, width 2)
| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
| --- | ----------- | ----------- | ----------- | ----------- |
-| 96 | W VSS_5 | |
+| 96 | W VSS_6 | |
| 97 | W PWM_0 | |
| 98 | W PWM_1 | |
| 99 | W EINT_0 | |
| 103 | W MSPI1_NSS | |
| 104 | W MSPI1_MOSI | |
| 105 | W MSPI1_MISO | |
-| 106 | W VDD_5 | |
+| 106 | W VDD_6 | |
| 107 | W SD0_CMD | |
| 108 | W SD0_CLK | |
| 109 | W SD0_D0 | |
| 110 | W SD0_D1 | |
| 111 | W SD0_D2 | |
| 112 | W SD0_D3 | |
-| 113 | W VSS_6 | |
-| 127 | W VDD_6 | |
+| 113 | W VSS_7 | |
+| 127 | W VDD_7 | |
# Pinouts (Fixed function)
auto-generated by [[pinouts.py]]
-## CLK
-
-System Clock
-
-* CLK_0 : S1/0
-
## EINT
External Interrupt
* GPIOE_E15 : E21/0
* GPIOE_E8 : E14/0
* GPIOE_E9 : E15/0
-* GPIOS_S0 : S14/0
-* GPIOS_S1 : S15/0
-* GPIOS_S2 : S16/0
-* GPIOS_S3 : S17/0
-* GPIOS_S4 : S18/0
-* GPIOS_S5 : S19/0
-* GPIOS_S6 : S20/0
-* GPIOS_S7 : S21/0
+* GPIOS_S0 : S23/0
+* GPIOS_S1 : S24/0
+* GPIOS_S2 : S25/0
+* GPIOS_S3 : S26/0
+* GPIOS_S4 : S27/0
+* GPIOS_S5 : S28/0
+* GPIOS_S6 : S29/0
+* GPIOS_S7 : S30/0
## JTAG
## MSPI0
-SPI (Serial Peripheral Interface) Master 1
+SPI Master 1 (general)
-* MSPI0_CK : S4/0
-* MSPI0_MISO : S7/0
-* MSPI0_MOSI : S6/0
-* MSPI0_NSS : S5/0
+* MSPI0_CK : S15/0
+* MSPI0_MISO : S18/0
+* MSPI0_MOSI : S17/0
+* MSPI0_NSS : S16/0
## MSPI1
-SPI (Serial Peripheral Interface) Master 2
+SPI Master 2 (SDCard)
* MSPI1_CK : W6/0
* MSPI1_MISO : W9/0
* PWM_0 : W1/0
* PWM_1 : W2/0
-## RST
-
-Reset
-
-* RST_0 : S2/0
-
## SD0
SD/MMC 1
* SDR_AD0 : N11/0
* SDR_AD1 : N12/0
+* SDR_AD10 : E1/0
+* SDR_AD11 : E2/0
+* SDR_AD12 : E3/0
* SDR_AD2 : N13/0
* SDR_AD3 : N14/0
* SDR_AD4 : N15/0
* SDR_DQM0 : N2/0
* SDR_DQM1 : E4/0
* SDR_RASn : N25/0
-* SDR_SDRAD10 : E1/0
-* SDR_SDRAD11 : E2/0
-* SDR_SDRAD12 : E3/0
* SDR_WEn : N27/0
+## SYS
+
+System Control
+
+* SYS_CLK : S1/0
+* SYS_CSEL0 : S5/0
+* SYS_CSEL1 : S6/0
+* SYS_CSEL2 : S7/0
+* SYS_PLLCLK : S3/0
+* SYS_PLLOUT : S4/0
+* SYS_RST : S2/0
+
+## TWI
+
+I2C Master 1
+
+* TWI_SCL : S10/0
+* TWI_SDA : S9/0
+
## UART0
UART (TX/RX) 1
-* UART0_RX : S9/0
-* UART0_TX : S8/0
+* UART0_RX : S21/0
+* UART0_TX : S20/0
## VDD
* VDD_1 : N31/0
* VDD_2 : E13/0
* VDD_3 : E31/0
-* VDD_4 : S31/0
-* VDD_5 : W10/0
-* VDD_6 : W31/0
+* VDD_4 : S8/0
+* VDD_5 : S31/0
+* VDD_6 : W10/0
+* VDD_7 : W31/0
## VSS
* VSS_2 : E0/0
* VSS_3 : E23/0
* VSS_4 : S0/0
-* VSS_5 : W0/0
-* VSS_6 : W17/0
+* VSS_5 : S22/0
+* VSS_6 : W0/0
+* VSS_7 : W17/0
# Pinmap for Libre-SOC 180nm
-* UART0_TX 72 S8/0
-* UART0_RX 73 S9/0
+* UART0_TX 84 S20/0
+* UART0_RX 85 S21/0
## GPIOS
-* GPIOS_S0 78 S14/0
-* GPIOS_S1 79 S15/0
-* GPIOS_S2 80 S16/0
-* GPIOS_S3 81 S17/0
-* GPIOS_S4 82 S18/0
-* GPIOS_S5 83 S19/0
-* GPIOS_S6 84 S20/0
-* GPIOS_S7 85 S21/0
+* GPIOS_S0 87 S23/0
+* GPIOS_S1 88 S24/0
+* GPIOS_S2 89 S25/0
+* GPIOS_S3 90 S26/0
+* GPIOS_S4 91 S27/0
+* GPIOS_S5 92 S28/0
+* GPIOS_S6 93 S29/0
+* GPIOS_S7 94 S30/0
## GPIOE
* VDD_1 31 N31/0
* VDD_2 45 E13/0
* VDD_3 63 E31/0
-* VDD_4 95 S31/0
-* VDD_5 106 W10/0
-* VDD_6 127 W31/0
+* VDD_4 72 S8/0
+* VDD_5 95 S31/0
+* VDD_6 106 W10/0
+* VDD_7 127 W31/0
## VSS
* VSS_2 32 E0/0
* VSS_3 55 E23/0
* VSS_4 64 S0/0
-* VSS_5 96 W0/0
-* VSS_6 113 W17/0
+* VSS_5 86 S22/0
+* VSS_6 96 W0/0
+* VSS_7 113 W17/0
-## CLK
+## SYS
-* CLK_0 65 S1/0
+* SYS_CLK 65 S1/0
+* SYS_RST 66 S2/0
+* SYS_PLLCLK 67 S3/0
+* SYS_PLLOUT 68 S4/0
+* SYS_CSEL0 69 S5/0
+* SYS_CSEL1 70 S6/0
+* SYS_CSEL2 71 S7/0
-## RST
+## TWI
+I2C.
-* RST_0 66 S2/0
-
-## TWI0
-
+* TWI_SDA 73 S9/0
+* TWI_SCL 74 S10/0
## MSPI0
-* MSPI0_CK 68 S4/0
-* MSPI0_NSS 69 S5/0
-* MSPI0_MOSI 70 S6/0
-* MSPI0_MISO 71 S7/0
+* MSPI0_CK 79 S15/0
+* MSPI0_NSS 80 S16/0
+* MSPI0_MOSI 81 S17/0
+* MSPI0_MISO 82 S18/0
## MSPI1
* SDR_CASn 26 N26/0
* SDR_WEn 27 N27/0
* SDR_CSn0 28 N28/0
-* SDR_SDRAD10 33 E1/0
-* SDR_SDRAD11 34 E2/0
-* SDR_SDRAD12 35 E3/0
+* SDR_AD10 33 E1/0
+* SDR_AD11 34 E2/0
+* SDR_AD12 35 E3/0
* SDR_DQM1 36 E4/0
* SDR_D8 37 E5/0
* SDR_D9 38 E6/0
# Reference Datasheets
datasheets and pinout links
+
* <http://datasheets.chipdb.org/AMD/8018x/80186/amd-80186.pdf>
* <http://hands.com/~lkcl/eoma/shenzen/frida/FRD144A2701.pdf>
* <http://pinouts.ru/Memory/sdcard_pinout.shtml>