register_file: Move GPRs into distributed RAM

The register file is currently implemented as a whole pile of individual
1-bit registers instead of LUT memory which is a huge waste of FPGA
space.

This is caused by the output signal exposing the register file to the
outside world for simulation debug.

This removes that output, and moves the dumping of the register file
to the register file module itself. This saves about 8% of fpga on
the little Arty A7-35T.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/common.vhdl b/common.vhdl
index bb898a0736e47fd4173156ca6f809b9ff1e2de9b..380c9be66180b174854e0250895b051377dce7bd 100644 (file)
--- a/common.vhdl
+++ b/common.vhdl
@@ -213,10 +213,6 @@ package common is
                write_cr_data : std_ulogic_vector(31 downto 0);
        end record;
        constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));
-
-       -- Would prefer not to expose this outside the register file, but ghdl
-       -- doesn't support external names
-       type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
 end common;
 
 package body common is

diff --git a/core.vhdl b/core.vhdl
index f25fa063a5c426d26100e2f7cc9e02d41323c222..df40d4373c28b4cf3f82f1dbf89bd4719b935604 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -94,9 +94,6 @@ architecture behave of core is
     -- Debug status
     signal dbg_core_is_stopped: std_ulogic;
 
-    -- For sim
-    signal registers: regfile;
-
 begin
 
     core_rst <= dbg_core_rst or rst;
@@ -180,12 +177,16 @@ begin
             );
 
     register_file_0: entity work.register_file
+        generic map (
+            SIM => SIM
+            )
         port map (
             clk => clk,
             d_in => decode2_to_register_file,
             d_out => register_file_to_decode2,
             w_in => writeback_to_register_file,
-            registers_out => registers);
+           sim_dump => terminate
+           );
 
     cr_file_0: entity work.cr_file
         port map (
@@ -277,17 +278,4 @@ begin
            terminated_out => terminated_out
            );
 
-    -- Dump registers if core terminates
-    sim_terminate_test: if SIM generate
-       dump_registers: process(all)
-       begin
-           if terminate = '1' then
-               loop_0: for i in 0 to 31 loop
-                   report "REG " & to_hstring(registers(i));
-               end loop loop_0;
-               assert false report "end of test" severity failure;
-           end if;
-       end process;
-    end generate;
-
 end behave;

diff --git a/register_file.vhdl b/register_file.vhdl
index 65ecefdfada380beaae5ef7c2e0ef30e84a768f8..a251a9fd5622c5dedd5768d783448712426479fe 100644 (file)
--- a/register_file.vhdl
+++ b/register_file.vhdl
@@ -6,6 +6,9 @@ library work;
 use work.common.all;
 
 entity register_file is
+    generic (
+        SIM : boolean := false
+        );
     port(
         clk           : in std_logic;
 
@@ -15,11 +18,12 @@ entity register_file is
         w_in          : in WritebackToRegisterFileType;
 
         -- debug
-        registers_out : out regfile
+        sim_dump      : in std_ulogic
         );
 end entity register_file;
 
 architecture behaviour of register_file is
+    type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
     signal registers : regfile := (others => (others => '0'));
 begin
     -- synchronous writes
@@ -64,6 +68,17 @@ begin
         end if;
     end process register_read_0;
 
-    -- debug
-    registers_out <= registers;
+    -- Dump registers if core terminates
+    sim_dump_test: if SIM generate
+       dump_registers: process(all)
+       begin
+           if sim_dump = '1' then
+               loop_0: for i in 0 to 31 loop
+                   report "REG " & to_hstring(registers(i));
+               end loop loop_0;
+               assert false report "end of test" severity failure;
+           end if;
+       end process;
+    end generate;
+
 end architecture behaviour;