anv/pipeline: Set StencilBufferWriteEnable from the pipeline
authorJason Ekstrand <jason.ekstrand@intel.com>
Fri, 4 Mar 2016 18:45:24 +0000 (10:45 -0800)
committerJason Ekstrand <jason.ekstrand@intel.com>
Fri, 4 Mar 2016 20:03:00 +0000 (12:03 -0800)
The hardware docs say that StencilBufferWriteEnable should only be set if
StencilTestEnable is set.  It seems reasonable to set them together.

src/intel/vulkan/gen7_cmd_buffer.c
src/intel/vulkan/gen7_pipeline.c
src/intel/vulkan/gen8_cmd_buffer.c
src/intel/vulkan/gen8_pipeline.c

index 1713cc17836253ab32a546a23dd20823a3b99be5..71010583129f4175e13881c40827f3dab5bdf994 100644 (file)
@@ -581,9 +581,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
       struct anv_dynamic_state *d = &cmd_buffer->state.dynamic;
 
       struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
-         .StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
-                                     d->stencil_write_mask.back != 0,
-
          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 
index 22a892bba3a0859843965308a286cdb58948589f..d563a8c26cdf8c1455279f971dd8cf38c7e37e5b 100644 (file)
@@ -95,6 +95,7 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline,
       .DoubleSidedStencilEnable = true,
 
       .StencilTestEnable = info->stencilTestEnable,
+      .StencilBufferWriteEnable = info->stencilTestEnable,
       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],
index d506cf48b0de4a607e0889d633c23e38e3945683..8e7a078d84bc2c3da1a8f0162ac47aeed059c21c 100644 (file)
@@ -384,9 +384,6 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer)
       struct GENX(3DSTATE_WM_DEPTH_STENCIL wm_depth_stencil) = {
          GENX(3DSTATE_WM_DEPTH_STENCIL_header),
 
-         .StencilBufferWriteEnable = d->stencil_write_mask.front != 0 ||
-                                     d->stencil_write_mask.back != 0,
-
          .StencilTestMask = d->stencil_compare_mask.front & 0xff,
          .StencilWriteMask = d->stencil_write_mask.front & 0xff,
 
index ecb8f6d7b0943b4c2995f6fcd53662097a5ccba3..e8a067851cc6532ab86614231d20ca5cfe3cc5e4 100644 (file)
@@ -227,6 +227,7 @@ emit_ds_state(struct anv_pipeline *pipeline,
       .DoubleSidedStencilEnable = true,
 
       .StencilTestEnable = info->stencilTestEnable,
+      .StencilBufferWriteEnable = info->stencilTestEnable,
       .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp],
       .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp],
       .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp],