SE/FS: Make SE vs. FS mode a runtime parameter.

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6154f987792161ebdbeeb283d4e4159d08d1974b..80379f6a3381a234ae230a788399ee530b69ca6a 100644 (file)
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -552,8 +552,8 @@ def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
     return self
 
 
-def makeDualRoot(testSystem, driveSystem, dumpfile):
-    self = Root()
+def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
+    self = Root(full_system = full_system)
     self.testsys = testSystem
     self.drivesys = driveSystem
     self.etherlink = EtherLink()

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 08484559a93a80d15ecf7884265aabdbd59d082a..9f41e24b965c60a5e040af506fbfa71b6d380427 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -198,9 +198,9 @@ if len(bm) == 2:
         drive_sys.kernel = binary(options.kernel)
 
     drive_sys.init_param = options.init_param
-    root = makeDualRoot(test_sys, drive_sys, options.etherdump)
+    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 elif len(bm) == 1:
-    root = Root(system=test_sys)
+    root = Root(full_system=True, system=test_sys)
 else:
     print "Error I don't know how to create more than 2 systems."
     sys.exit(1)

diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 24a49a9b3b7d1e2d322bcdf3d5f881aad2bb1592..b2cedc8f5946f7324ff64c0db99e7ca5f3d38b98 100644 (file)
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -172,7 +172,7 @@ make_level(treespec, prototypes, system.physmem, "port")
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 if options.atomic:
     root.system.mem_mode = 'atomic'
 else:

diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 55b1c85e6982b34b9e90a0437d09baf0b977e6e7..d4843e8662e41e6bfa204028a401010fabf2720c 100644 (file)
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -111,7 +111,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index e6ac5f8c865e3121a4b0b569ce4662a36f95dd27..e18ed95af23c057bdc3a9bcf6fd5c49408e47c88 100644 (file)
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -141,6 +141,6 @@ for (i, cpu) in enumerate(system.cpu):
         cpu.interrupts.pio = system.piobus.port
         cpu.interrupts.int_port = system.piobus.port
 
-root = Root(system = system)
+root = Root(full_system = True, system = system)
 
 Simulation.run(options, root, system, FutureClass)

diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 6b1a46776f9e3719f2226336696204b546b3a4d8..a418c47eb619ebf4564a52b938216d55226cf8fc 100644 (file)
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -162,7 +162,7 @@ for (i, dma) in enumerate(dmas):
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index cd221ec7e0e3826b9ec24b48eea0c43a579c8a3a..b5d788bf5eac421705e40a88d01a713b16471b32 100644 (file)
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -121,7 +121,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 7655e32fdedaa7572dcc830045c7afc8eaa0ad6a..4bf17d70bd3f9c0bfb6a920961c09dc35360caa6 100644 (file)
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -131,7 +131,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/configs/example/se.py b/configs/example/se.py
index 57236448246d80d839e3b7d8b116f8e6daf56e31..f1dae94827780f136c2a1f3ee69b42c8e068ddf4 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -200,6 +200,6 @@ for i in xrange(np):
     if options.fastmem:
         system.cpu[0].physmem_port = system.physmem.port
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 Simulation.run(options, root, system, FutureClass)

diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index e8c471eaa7f79754544046d91606297391b9fb3a..4a9446794d5aa3f488bd914c21cf82a7e358d6fb 100644 (file)
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -239,7 +239,7 @@ for cluster in clusters:
 # Define the root
 # ----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 # --------------------
 # Pick the correct Splash2 Benchmarks

diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 200eb191dd269d8256441fdbe796d06167f9086c..8a9b815e6d43548335faa27dcf4f661ae62ac9b5 100644 (file)
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -225,7 +225,7 @@ for cpu in cpus:
 # Define the root
 # ----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 # --------------------
 # Pick the correct Splash2 Benchmarks

diff --git a/src/sim/Root.py b/src/sim/Root.py
index e15de155460b5c41634c52c521a032595d8e5472..daa0a903fdb62f29e2ec8dc17fdfee80076a8d59 100644 (file)
--- a/src/sim/Root.py
+++ b/src/sim/Root.py
@@ -28,6 +28,7 @@
 # Authors: Nathan Binkert
 
 from m5.SimObject import SimObject
+from m5.defines import buildEnv
 from m5.params import *
 from m5.util import fatal
 
@@ -58,6 +59,8 @@ class Root(SimObject):
 
     type = 'Root'
 
+    full_system = Param.Bool("if this is a full system simulation")
+
     # Time syncing prevents the simulation from running faster than real time.
     time_sync_enable = Param.Bool(False, "whether time syncing is enabled")
     time_sync_period = Param.Clock("100ms", "how often to sync with real time")

diff --git a/src/sim/full_system.hh b/src/sim/full_system.hh
index 911648f3a39f41bb6c5aefb4f9995098c1f93be9..e67fc11a97c917b510e509383be553ff5fea9a8d 100644 (file)
--- a/src/sim/full_system.hh
+++ b/src/sim/full_system.hh
@@ -31,8 +31,6 @@
 #ifndef __SIM_FULL_SYSTEM_HH__
 #define __SIM_FULL_SYSTEM_HH__
 
-#include "config/full_system.hh"
-
-static const bool FullSystem = FULL_SYSTEM;
+extern bool FullSystem;
 
 #endif // __SIM_FULL_SYSTEM_HH__

diff --git a/src/sim/root.cc b/src/sim/root.cc
index dd7c1207711fa822ae84dc346d127a2d0897a796..c47ada30eeddcc4a39bbc1851232c8978f4392c6 100644 (file)
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -33,6 +33,7 @@
 
 #include "base/misc.hh"
 #include "debug/TimeSync.hh"
+#include "sim/full_system.hh"
 #include "sim/root.hh"
 
 Root *Root::_root = NULL;
@@ -123,6 +124,8 @@ Root::loadState(Checkpoint *cp)
     timeSyncEnable(params()->time_sync_enable);
 }
 
+bool FullSystem;
+
 Root *
 RootParams::create()
 {
@@ -132,5 +135,7 @@ RootParams::create()
 
     created = true;
 
+    FullSystem = full_system;
+
     return new Root(this);
 }

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 1bab8360938e6939ba381fa84263ab1a21bdb7aa..2a87cb66341bbaa36698d1c272419c75fc54cf04 100644 (file)
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 2517e7670778466cbb7eec061670cca19e943dda..6d0f8aa868021d68ee95f53224c49ae616154327 100644 (file)
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -117,7 +117,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 66e49a63ea1ccc5c1d6a2facc283da4b329808cb..c1358eecd181d4552df437f3208adc205004f4d9 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -86,7 +86,7 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Cache CachePort MemoryAccess"
 #root.trace.cycle=1

diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index b14f0e5b1f3e328e1d9e74a85157a944e9b9e3dc..2f8829db0dd80d883cede28e42c482c57f4a3164 100644 (file)
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -51,5 +51,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 67aaebd21b039e445b9213d5538e48c831055e5b..9436cf88a3cba6524f11c412f6601abf6d3b6328 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -86,7 +86,7 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Bus Cache"
 #root.trace.flags = "BusAddrRanges"

diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 07851ae9f1082718fee0c9f60465c12ae1ccc62d..b967a508043f099e5ec0749988e2b656a1efdcee 100644 (file)
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,4 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 395fd24a37a11d568360f59db0df1fb1a5167449..9701b10123cbc59191067dbb8103bcaf3d5a5662 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 0fe23d1ee8c37585c0ece06a224116526014625e..f3b8e700f15ecffabefcb98b0b855a6cd1c8541a 100644 (file)
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -108,6 +108,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index eeff170694688c688085e41f997bd28a6f0704c7..62c7c7bd40ff9f2c2b577b0d6ba20ea11b24e66b 100644 (file)
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index a1b2f46765485528dcab1848decf51f4008d02c6..cbfda22a267688a6976f9cb62f83b8aec9df9bc0 100644 (file)
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 69c583abdcaaba95b5160cf501bef899192f865e..adab96fcb2567f4f9e09316c8ff45c8eef45fba0 100644 (file)
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index bab5a193d6e340ecd3aa9ccc30e02bdbf2d01df7..f466bc480d6b02f3e61aa74b4819de82bc3ce140 100644 (file)
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index edfd940adaf9ad659a843a4faa014aad31425c68..5baa3c91a9d2c755ac13e3c2e1602e0031b3a8f7 100644 (file)
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 83f85641a4224b6a8958780da5968a9dc2b7ee1c..f1de86411517e62fb1f77e0be964103cba106144 100644 (file)
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -90,6 +90,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 7fe0d409bbbcbc08b3eb4dfa69d98990ea430157..81646f825c4a8314ea76276defb2e6fbe56259e3 100644 (file)
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 90f2539e6ece4941b5a52c28cab0666ccad47d16..8d1840571df6ce99d616fe4ce789b9fc225f3065 100644 (file)
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index a7e598b0aeb9edae9991f99aff7b8a2d6fc5ed6d..0fffe1aa2f40b30e1b49644b2ff6a121f8fa2e6c 100644 (file)
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -112,7 +112,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 705f13ef391965add85571a1d996590808c61fad..fe0311801cc3a4268cc5494adcb45451180de713 100644 (file)
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -52,5 +52,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'atomic'

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index e722ef33464a1972e077cf8f7e8c9c7268f7815a..db0c0b9c0db9f8b4514387aa94c0de2f210eae28 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -85,5 +85,5 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'atomic'

diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 1912301642b1b00817de0d47c7117f7febe0170d..eb7415b8da56dfda7d8cd3d7b9b1ba7f4d6f173b 100644 (file)
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -37,4 +37,4 @@ system.physmem.port = system.membus.port
 system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)

diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 58ca862e18a202fc914bb619d5c8e30f22efe83e..63d5291b980a9b6fe263ae400404d5c7d797c183 100644 (file)
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -95,7 +95,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system=False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index f1ebb1939b7221586b7bfe2f40abd21c8c31b95f..c82ef0a266b45db673c799a31870b898fa05f8bc 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -85,5 +85,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 319dd3b553c3c9db8dfc371d5ea983a9fd0f13a5..2324c196b1ef5df9e9fa769836900de5c9ef1210 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -91,7 +91,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index cc0d1d20740602b1e13c5f9bcdbc4a766fe9b0eb..19b40fe480b80e821e34e2f39a0f5b3c5723c416 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -51,4 +51,4 @@ system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system=False, system = system)

diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index ae2c59110fea4307aa1966f6e2b1b724986afd21..217135bf050949b16cd03183f937d6d31d75a1b8 100644 (file)
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -36,6 +36,6 @@ system = FSConfig.makeSparcSystem('atomic')
 system.cpu = cpu
 cpu.connectAllPorts(system.membus)
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')

diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index a082615337b13e24684d7601b9d28b8e3e7aa667..dc30633b3bede2d0b0b830d205e5142eb9eb045c 100644 (file)
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -96,6 +96,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index c63637f73cd3e6b78bdbcdfe5e2f96b7ad620eea..1680be16694f63a8caf4e6ad1b0627b10a2416f3 100644 (file)
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -95,6 +95,6 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index a6bb4b12210427233865785a6401601e9f581c1f..accf350b36613cc5ef15620907f2e5bf94cd15a8 100644 (file)
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 758dbef098f9b79871e0f587bc1030555d1f3e44..9a29f5c651c4e8d6f9d3c413631c284535cae1ab 100644 (file)
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -93,5 +93,5 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')

diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index a2335d7636505615a7a511af641820b51a064455..897b1c9469d35a0f5df198db7a379ac2edc4e535 100644 (file)
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -91,6 +91,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index ad466a5c086f528699afc8c387a2da51d97472c1..6b78b71f4154d34a7118f6ca8e703a881ed0babe 100644 (file)
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -93,7 +93,7 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
 

diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 7dc0ded5c01f3e60da0e2ed2f870abb9c5f1a303..e3a764e16ead66d7d7a76dcfe9d32f2da2a2951a 100644 (file)
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 

diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 658508fa033f4c6d6502690e729bd687db606a7f..d32e5dd872e55403b8814eb9aa8eaeaf15b3d69f 100644 (file)
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -53,6 +53,6 @@ drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
 drive_sys.iobridge.slave = drive_sys.iobus.port
 drive_sys.iobridge.master = drive_sys.membus.port
 
-root = makeDualRoot(test_sys, drive_sys, "ethertrace")
+root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
 
 maxtick = 199999999