Started adding a system to output data after every instruction.

src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
    Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
    Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
    Options to turn on output after every instruction. They are commented out.

--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index c31619408b55e860dc524453544064a793d92f7a..43b48a0ab2c978dadbf68aaa57ca3ac6352b3aa7 100644 (file)
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -45,6 +45,21 @@ class ThreadContext;
 namespace AlphaISA
 {
 
+    static inline std::string getIntRegName(RegIndex)
+    {
+        return "";
+    }
+
+    static inline std::string getFloatRegName(RegIndex)
+    {
+        return "";
+    }
+
+    static inline std::string getMiscRegName(RegIndex)
+    {
+        return "";
+    }
+
     class IntRegFile
     {
       protected:

diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index f057461aef47b6330df3f5203fed4a6fa302926b..e9447d39e0e1a5048705acee052bf6483645e27e 100644 (file)
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -41,6 +41,11 @@ class Checkpoint;
 
 namespace MipsISA
 {
+    static inline std::string getFloatRegName(RegIndex)
+    {
+        return "";
+    }
+
     const uint32_t MIPS32_QNAN = 0x7fbfffff;
     const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
 

diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index 5496fc1f50f508aa3e9605dca1511ed85e893297..a45a17a85cb16ba5439f7ee044d6cb774dcc93f8 100644 (file)
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -41,6 +41,11 @@ class ThreadContext;
 
 namespace MipsISA
 {
+    static inline std::string getIntRegName(RegIndex)
+    {
+        return "";
+    }
+
     enum MiscIntRegNums {
        HI = NumIntArchRegs,
        LO

diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index 66d3218d4e4d32516d409f608e535f13d1cf22d6..c2e1c317682f0c6d64e5f349d254d261516dd41f 100644 (file)
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -39,6 +39,11 @@ class ThreadContext;
 
 namespace MipsISA
 {
+    static inline std::string getMiscRegName(RegIndex)
+    {
+        return "";
+    }
+
     //Coprocessor 0 Register Names
     enum MiscRegTags {
         //Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8

diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 7fdad5113f9f4f1a45ec7e2f31341715b5f6ec4b..748f66d37c03368a98cbac4983c079777c367740 100644 (file)
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -34,6 +34,7 @@
 #include <fstream>
 #include <iomanip>
 
+#include "arch/regfile.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
@@ -42,7 +43,7 @@
 #include "sim/system.hh"
 
 using namespace std;
-
+using namespace TheISA;
 
 ////////////////////////////////////////////////////////////////////////
 //
@@ -53,7 +54,43 @@ using namespace std;
 void
 Trace::InstRecord::dump(ostream &outs)
 {
-    if (flags[INTEL_FORMAT]) {
+    if (flags[PRINT_REG_DELTA])
+    {
+        outs << "PC = 0x" << setbase(16)
+                        << setfill('0')
+                        << setw(16) << PC << endl;
+        outs << setbase(10)
+             << setfill(' ')
+             << setw(0);
+        /*
+        int numSources = staticInst->numSrcRegs();
+        int numDests = staticInst->numDestRegs();
+        outs << "Sources:";
+        for(int x = 0; x < numSources; x++)
+        {
+            int sourceNum = staticInst->srcRegIdx(x);
+            if(sourceNum < FP_Base_DepTag)
+                outs << " " << getIntRegName(sourceNum);
+            else if(sourceNum < Ctrl_Base_DepTag)
+                outs << " " << getFloatRegName(sourceNum - FP_Base_DepTag);
+            else
+                outs << " " << getMiscRegName(sourceNum - Ctrl_Base_DepTag);
+        }
+        outs << endl;
+        outs << "Destinations:";
+        for(int x = 0; x < numDests; x++)
+        {
+            int destNum = staticInst->destRegIdx(x);
+            if(destNum < FP_Base_DepTag)
+                outs << " " << getIntRegName(destNum);
+            else if(destNum < Ctrl_Base_DepTag)
+                outs << " " << getFloatRegName(destNum - FP_Base_DepTag);
+            else
+                outs << " " << getMiscRegName(destNum - Ctrl_Base_DepTag);
+        }
+        outs << endl;*/
+    }
+    else if (flags[INTEL_FORMAT]) {
 #if FULL_SYSTEM
         bool is_trace_system = (cpu->system->name() == trace_system);
 #else
@@ -196,6 +233,8 @@ Param<bool> exe_trace_print_fetchseq(&exeTraceParams, "print_fetchseq",
                                   "print fetch sequence number", false);
 Param<bool> exe_trace_print_cp_seq(&exeTraceParams, "print_cpseq",
                                   "print correct-path sequence number", false);
+Param<bool> exe_trace_print_reg_delta(&exeTraceParams, "print_reg_delta",
+                                  "print which registers changed to what", false);
 Param<bool> exe_trace_pc_symbol(&exeTraceParams, "pc_symbol",
                                   "Use symbols for the PC if available", true);
 Param<bool> exe_trace_intel_format(&exeTraceParams, "intel_format",
@@ -222,6 +261,7 @@ Trace::InstRecord::setParams()
     flags[PRINT_INT_REGS]    = exe_trace_print_iregs;
     flags[PRINT_FETCH_SEQ]   = exe_trace_print_fetchseq;
     flags[PRINT_CP_SEQ]      = exe_trace_print_cp_seq;
+    flags[PRINT_REG_DELTA]   = exe_trace_print_reg_delta;
     flags[PC_SYMBOL]         = exe_trace_pc_symbol;
     flags[INTEL_FORMAT]      = exe_trace_intel_format;
     trace_system            = exe_trace_system;

diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 95f8b449cda24960869374305ba42b97128a5452..8cc98b777d72d231cb754dced2e86e673e8655a6 100644 (file)
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -147,6 +147,7 @@ class InstRecord : public Record
         PRINT_INT_REGS,
         PRINT_FETCH_SEQ,
         PRINT_CP_SEQ,
+        PRINT_REG_DELTA,
         PC_SYMBOL,
         INTEL_FORMAT,
         NUM_BITS

diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 293c4dbca4ae01d25cf7fd57b8307615d1233aa3..e296453db3f58dad0902776a4713c016cc7c4b7d 100644 (file)
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -177,6 +177,8 @@ bool_option("print-fetch-seq", default=False,
     help="Print fetch sequence numbers in trace output")
 bool_option("print-cpseq", default=False,
     help="Print correct path sequence numbers in trace output")
+#bool_option("print-reg-delta", default=False,
+#    help="Print which registers changed to what in trace output")
 
 options = attrdict()
 arguments = []
@@ -290,6 +292,7 @@ def main():
     objects.ExecutionTrace.print_iregs = options.print_iregs
     objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq
     objects.ExecutionTrace.print_cpseq = options.print_cpseq
+    #objects.ExecutionTrace.print_reg_delta = options.print_reg_delta
 
     sys.argv = arguments
     sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path