targets/nexys4ddr: use LiteXSoC's add_spi_sdcard method.

diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 5d8282b7a7a8525229b6f3e5be0b5aa50542aeb5..ba0d6c1d823c9b6940fc23fd5deeb97490dc0388 100755 (executable)
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -25,8 +25,6 @@ from litesdcard.core import SDCore
 from litesdcard.bist import BISTBlockGenerator, BISTBlockChecker
 from litex.soc.cores.timer import Timer
 
-from litex.soc.cores.spi import SPIMaster
-
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -87,13 +85,6 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
-    def add_spisdcard(self):
-        spisdcard_pads = self.platform.request("spisdcard")
-        if hasattr(spisdcard_pads, "rst"):
-            self.comb += spisdcard_pads.rst.eq(0)
-        self.submodules.spisdcard = SPIMaster(spisdcard_pads, 8, self.sys_clk_freq, 400e3)
-        self.add_csr("spisdcard")
-
     def add_sdcard(self):
         sdcard_pads = self.platform.request("sdcard")
         if hasattr(sdcard_pads, "rst"):
@@ -142,7 +133,7 @@ def main():
         with_ethernet=args.with_ethernet,
         **soc_sdram_argdict(args))
     if args.with_spi_sdcard:
-        soc.add_spisdcard()
+        soc.add_spi_sdcard()
     if args.with_sdcard:
         if args.with_spi_sdcard:
             raise ValueError("'--with-spi-sdcard' and '--with-sdcard' are mutually exclusive!")