record conversation snippet
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 4 Dec 2018 11:29:37 +0000 (11:29 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 4 Dec 2018 11:29:37 +0000 (11:29 +0000)
3d_gpu/microarchitecture.mdwn

index 07576242a0813388fc201b299287ed58cb1cf4fd..f3e4f96d29e6a3be93b9fc6a123ecf257da92a44 100644 (file)
@@ -190,6 +190,20 @@ Reorder Buffer
     - Registers updated
     - Memory updated
 
+Reorder Buffer Entry
+
+* Instruction type
+    - branch (no destination resutl)
+    - store (has a memory address destination)
+    - register operation (ALU operation or load, which has reg dests)
+* Destination
+    - register number (for loads and ALU ops) or
+    - memory address (for stores) where the result should be written
+* Value
+    - value of instruction result, pending a commit
+* Ready
+    - indicates that the instruction has completed execution: value is ready
+
 # References
 
 * <https://en.wikipedia.org/wiki/Tomasulo_algorithm>