further investigation note

diff --git a/3d_gpu/architecture/compared_to_register_renaming.mdwn b/3d_gpu/architecture/compared_to_register_renaming.mdwn
index 1e2866e341fdb6db1b204a07d5b3b00fb0b2764f..9658de84b41725e89c2a494787bc8bbbfd9c42e4 100644 (file)
--- a/3d_gpu/architecture/compared_to_register_renaming.mdwn
+++ b/3d_gpu/architecture/compared_to_register_renaming.mdwn
@@ -56,7 +56,8 @@ f:
 
 Renamed hardware registers are named `h0`, `h1`, `h2`, ...
 
-The syntax `ldu h7, 8(h5 -> h8)` will be used to mean that the address read comes from `h5` and the address write goes to `h8`
+The syntax `ldu h7, 8(h5 -> h8)` will be used to mean that the address
+read comes from `h5` and the address write goes to `h8`
 
 The register rename table starts out as following: