rs6000-power2-1.c: Change the options to be more correct.

2004-04-29  Andrew Pinski  <pinskia@physics.uc.edu>

        * gcc.dg/rs6000-power2-1.c: Change the options to be more correct.
        * gcc.dg/rs6000-power2-2.c: Change the options to be more correct.
        Change the asm registers to be in form of frN instead of fN.

From-SVN: r81303

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 718a92eb2dc6d8f0a9f35d2327e26876c0f067af..2214658bbbc45c02e88109805481ab59d1c98777 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2004-04-29  Andrew Pinski  <pinskia@physics.uc.edu>
+
+       * gcc.dg/rs6000-power2-1.c: Change the options to be more correct.
+       * gcc.dg/rs6000-power2-2.c: Change the options to be more correct.
+       Change the asm registers to be in form of frN instead of fN.
+
 2004-04-28  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
        * gcc.dg/torture/builtin-convert-2.c: New test.

diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-1.c b/gcc/testsuite/gcc.dg/rs6000-power2-1.c
index 7f22b98c64e0e961382cca45d8aebe27da14ea20..0e9b5aa1d5d62f2f95c7c1f4bb4f916692cbd9b0 100644 (file)
--- a/gcc/testsuite/gcc.dg/rs6000-power2-1.c
+++ b/gcc/testsuite/gcc.dg/rs6000-power2-1.c
@@ -1,5 +1,5 @@
 /* { dg-do assemble { target powerpc-*-* rs6000-*-* }  } */
-/* { dg-options "-O -mpower2 -fno-schedule-insns -w" } */
+/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
 /* This used to ICE as the peephole was not checking to see
    if the register is a floating point one (I think this cannot
    happen in real life except in this example).  */

diff --git a/gcc/testsuite/gcc.dg/rs6000-power2-2.c b/gcc/testsuite/gcc.dg/rs6000-power2-2.c
index dda48526c24567417f65d317da43fd55ec08842d..74cc0ec64e37d6c8a3446e9e1015048e09c2d7ff 100644 (file)
--- a/gcc/testsuite/gcc.dg/rs6000-power2-2.c
+++ b/gcc/testsuite/gcc.dg/rs6000-power2-2.c
@@ -1,13 +1,13 @@
 /* { dg-do assemble { target powerpc-*-* rs6000-*-* }  } */
-/* { dg-options "-O -mpower2 -fno-schedule-insns" } */
+/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */
 /* { dg-final { scan-assembler-not "lfd" } } */
 /* { dg-final { scan-assembler-not "sfd" } } */
 /* { dg-final { scan-assembler "lfq" } } */
 /* { dg-final { scan-assembler "sfq" } } */
 
-register double t1 __asm__("f0");
-register double t2 __asm__("f1");
-register double t3 __asm__("f2"), t4 __asm__("f3");
+register double t1 __asm__("fr0");
+register double t2 __asm__("fr1");
+register double t3 __asm__("fr2"), t4 __asm__("fr3");
 void t(double *a, double *b)
 {
         t1 = a[-1];