Fixed part selects of parameters

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b4115f0cd154531389cfbcaab45ceb083e5af41a..9b8e0faa46f53b98c79ad5771042f9e7987ea187 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -902,6 +902,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                use_const_chunk:
                        if (children.size() != 0) {
                                log_assert(children[0]->type == AST_RANGE);
+                               int source_width = id2ast->range_left - id2ast->range_right + 1;
+                               int source_offset = id2ast->range_right;
                                if (!children[0]->range_valid) {
                                        AstNode *left_at_zero_ast = children[0]->children[0]->clone();
                                        AstNode *right_at_zero_ast = children[0]->children.size() >= 2 ? children[0]->children[1]->clone() : left_at_zero_ast->clone();
@@ -914,17 +916,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                                        AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
                                                        children[0]->children[1]->clone() : children[0]->children[0]->clone());
                                        fake_ast->children[0]->delete_children();
-                                       RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width,
-                                                       fake_ast->children[0]->genRTLIL(), !id2ast->range_swapped ? fake_ast->children[1]->genRTLIL() :
-                                                       current_module->Sub(NEW_ID, RTLIL::SigSpec(wire->width - width), fake_ast->children[1]->genRTLIL()));
+                                       RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL();
+                                       log_dump(width, shift_val, id2ast->range_swapped, source_width, id2ast->range_left, id2ast->range_right);
+                                       if (id2ast->range_right != 0)
+                                               shift_val = current_module->Sub(NEW_ID, shift_val, id2ast->range_right);
+                                       if (id2ast->range_swapped)
+                                               shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val);
+                                       RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shr", width, fake_ast->children[0]->genRTLIL(), shift_val);
                                        delete left_at_zero_ast;
                                        delete right_at_zero_ast;
                                        delete fake_ast;
                                        return sig;
                                } else {
-                                       int source_width = id2ast->range_left - id2ast->range_right + 1;
                                        chunk.width = children[0]->range_left - children[0]->range_right + 1;
-                                       chunk.offset = children[0]->range_right - id2ast->range_right;
+                                       chunk.offset = children[0]->range_right - source_offset;
                                        if (id2ast->range_swapped)
                                                chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
                                        if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 7aa6d24c3fead499b2104204c2af4029d348b9e4..d47bfb5e68f587818c555c3da4012caeff123bae 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -575,6 +575,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
                                }
                                children[0]->is_signed = is_signed;
                        }
+                       range_valid = true;
+                       range_swapped = children[1]->range_swapped;
+                       range_left = children[1]->range_left;
+                       range_right = children[1]->range_right;
                } else
                if (children.size() > 1 && children[1]->type == AST_REALVALUE && children[0]->type == AST_CONSTANT) {
                        double as_realvalue = children[0]->asReal(sign_hint);
@@ -1522,8 +1526,23 @@ skip_dynamic_range_lvalue_expansion:;
                                if (current_scope[str]->children[0]->type == AST_CONSTANT) {
                                        if (children.size() != 0 && children[0]->type == AST_RANGE && children[0]->range_valid) {
                                                std::vector<RTLIL::State> data;
-                                               for (int i = children[0]->range_right; i <= children[0]->range_left; i++)
-                                                       data.push_back(current_scope[str]->children[0]->bits[i]);
+                                               bool param_upto = current_scope[str]->range_valid && current_scope[str]->range_swapped;
+                                               int param_offset = current_scope[str]->range_valid ? current_scope[str]->range_right : 0;
+                                               int param_width = current_scope[str]->range_valid ? current_scope[str]->range_left - current_scope[str]->range_right + 1 :
+                                                               SIZE(current_scope[str]->children[0]->bits);
+                                               int tmp_range_left = children[0]->range_left, tmp_range_right = children[0]->range_right;
+                                               if (param_upto) {
+                                                       tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1;
+                                                       tmp_range_right = (param_width + 2*param_offset) - children[0]->range_left - 1;
+                                               }
+                                               log_dump(param_upto, param_offset, param_width, children[0]->range_left, children[0]->range_right, tmp_range_left, tmp_range_right);
+                                               for (int i = tmp_range_right; i <= tmp_range_left; i++) {
+                                                       int index = i - param_offset;
+                                                       if (0 <= index && index < param_width)
+                                                               data.push_back(current_scope[str]->children[0]->bits[index]);
+                                                       else
+                                                               data.push_back(RTLIL::State::Sx);
+                                               }
                                                newNode = mkconst_bits(data, false);
                                        } else
                                        if (children.size() == 0)