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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index b9ee7598f94295d45cc6d4870e9e32b330a50760..3ef9c84f7095d65a6c9585b3dc376fc410eaa33b 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -568,7 +568,7 @@ came out with an astonishing 43% improvement in completion time. 43%
 less instructions executed is an almost unheard-of level of optimisation:
 most ISA designers are elated if they can achieve 5 to 10%. The reduction
 was so compelling that ST Microelectronics put it into commercial
-production in one of their embedded CPUs.
+production in one of their embedded CPUs, the ST120 DSP-MCU.
 
 The kicker: when implementing SVP64's Matrix REMAP Schedule, the VLSI
 design of its triple-nested for-loop system