radeonsi: set amdgpu metadata before exporting a texture

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 5a6ce71414c1a1e27b871a067013c8e824c37477..7d256dbe0067d1056453a3b7e18d884d2d4a851e 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -439,7 +439,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return PIPE_ENDIAN_LITTLE;
 
        case PIPE_CAP_VENDOR_ID:
-               return 0x1002;
+               return ATI_VENDOR_ID;
        case PIPE_CAP_DEVICE_ID:
                return rscreen->b.info.pci_id;
        case PIPE_CAP_ACCELERATED:

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 31ec24de9a26518199e2654e209f9410a0ac0872..d20069ef0c924b056cb23cbf17d4fa651dbb4111 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -43,6 +43,8 @@
 #include "util/u_suballoc.h"
 #include "util/u_transfer.h"
 
+#define ATI_VENDOR_ID 0x1002
+
 #define R600_RESOURCE_FLAG_TRANSFER            (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH       (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
 #define R600_RESOURCE_FLAG_FORCE_TILING                (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
@@ -332,6 +334,10 @@ struct r600_common_screen {
         * drawing and re-emit the framebuffer state accordingly.
         */
        unsigned                        dirty_fb_counter;
+
+       void (*query_opaque_metadata)(struct r600_common_screen *rscreen,
+                                     struct r600_texture *rtex,
+                                     struct radeon_bo_metadata *md);
 };
 
 /* This encapsulates a state or an operation which can emitted into the GPU

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index b8c4c795b3cab4318458c4f32dddfae4dbdfa985..1a8822ca54ba0af6a5f9ba8277500d168a6f8806 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -355,6 +355,10 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
 
                        /* Set metadata. */
                        r600_texture_init_metadata(rtex, &metadata);
+                       if (rscreen->query_opaque_metadata)
+                               rscreen->query_opaque_metadata(rscreen, rtex,
+                                                              &metadata);
+
                        rscreen->ws->buffer_set_metadata(res->buf, &metadata);
                }
        } else {

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index b445f6f010f76548a710c82670dbd635ce9ed2e9..58e7f3acd67c9c56ca0c4300736a6e14405f4417 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -420,7 +420,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
                return PIPE_ENDIAN_LITTLE;
 
        case PIPE_CAP_VENDOR_ID:
-               return 0x1002;
+               return ATI_VENDOR_ID;
        case PIPE_CAP_DEVICE_ID:
                return sscreen->b.info.pci_id;
        case PIPE_CAP_ACCELERATED:
@@ -613,6 +613,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
        sscreen->b.b.is_format_supported = si_is_format_supported;
        sscreen->b.b.resource_create = r600_resource_create_common;
 
+       si_init_screen_state_functions(sscreen);
+
        if (!r600_common_screen_init(&sscreen->b, ws) ||
            !si_init_gs_info(sscreen) ||
            !si_init_shader_cache(sscreen)) {

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 8190913df8a081bc032b52753f4fdf2fbbee4351..f823af188c7f619d19c822cffc9aa7f00187bff2 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -34,6 +34,7 @@
 #include "util/u_format_s3tc.h"
 #include "util/u_memory.h"
 #include "util/u_pstipple.h"
+#include "util/u_resource.h"
 
 /* Initialize an external atom (owned by ../radeon). */
 static void
@@ -3600,6 +3601,68 @@ void si_init_state_functions(struct si_context *sctx)
        si_init_config(sctx);
 }
 
+static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
+                                    struct r600_texture *rtex,
+                                    struct radeon_bo_metadata *md)
+{
+       struct si_screen *sscreen = (struct si_screen*)rscreen;
+       struct pipe_resource *res = &rtex->resource.b.b;
+       static const unsigned char swizzle[] = {
+               PIPE_SWIZZLE_RED,
+               PIPE_SWIZZLE_GREEN,
+               PIPE_SWIZZLE_BLUE,
+               PIPE_SWIZZLE_ALPHA
+       };
+       uint32_t desc[8], i;
+       bool is_array = util_resource_is_array_texture(res);
+
+       /* DRM 2.x.x doesn't support this. */
+       if (rscreen->info.drm_major != 3)
+               return;
+
+       assert(rtex->fmask.size == 0);
+
+       /* Metadata image format format version 1:
+        * [0] = 1 (metadata format identifier)
+        * [1] = (VENDOR_ID << 16) | PCI_ID
+        * [2:9] = image descriptor for the whole resource
+        *         [2] is always 0, because the base address is cleared
+        *         [9] is the DCC offset bits [39:8] from the beginning of
+        *             the buffer
+        * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
+        */
+
+       md->metadata[0] = 1; /* metadata image format version 1 */
+
+       /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
+       md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
+
+       si_make_texture_descriptor(sscreen, rtex, res->target, res->format,
+                                  swizzle, 0, 0, res->last_level, 0,
+                                  is_array ? res->array_size - 1 : 0,
+                                  res->width0, res->height0, res->depth0,
+                                  desc, NULL);
+
+       /* Clear the base address and set the relative DCC offset. */
+       desc[0] = 0;
+       desc[1] &= C_008F14_BASE_ADDRESS_HI;
+       desc[7] = rtex->dcc_offset >> 8;
+
+       /* Dwords [2:9] contain the image descriptor. */
+       memcpy(&md->metadata[2], desc, sizeof(desc));
+
+       /* Dwords [10:..] contain the mipmap level offsets. */
+       for (i = 0; i <= res->last_level; i++)
+               md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
+
+       md->size_metadata = (11 + res->last_level) * 4;
+}
+
+void si_init_screen_state_functions(struct si_screen *sscreen)
+{
+       sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
+}
+
 static void
 si_write_harvested_raster_configs(struct si_context *sctx,
                                  struct si_pm4_state *pm4,

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 40792cbc1d5b170fecb004b6f8ad960cfcd6e1e9..fb16d0f29539a11110fa3e7255fe0cdbf54d3a25 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -263,6 +263,7 @@ boolean si_is_format_supported(struct pipe_screen *screen,
                                unsigned sample_count,
                                unsigned usage);
 void si_init_state_functions(struct si_context *sctx);
+void si_init_screen_state_functions(struct si_screen *sscreen);
 unsigned cik_bank_wh(unsigned bankwh);
 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode);
 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect);