Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
authorClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 07:48:26 +0000 (09:48 +0200)
committerClifford Wolf <clifford@clifford.at>
Wed, 23 Jul 2014 07:52:55 +0000 (09:52 +0200)
16 files changed:
backends/blif/blif.cc
backends/edif/edif.cc
frontends/ilang/parser.y
kernel/rtlil.cc
kernel/rtlil.h
kernel/sigtools.h
passes/abc/abc.cc
passes/fsm/fsm_map.cc
passes/memory/memory_share.cc
passes/opt/opt_clean.cc
passes/proc/proc_mux.cc
passes/sat/eval.cc
passes/sat/miter.cc
passes/sat/share.cc
passes/techmap/extract.cc
passes/techmap/iopadmap.cc

index edb6809ee968b43eba2ee55f36acbed129ec34b8..a240d2a26a6166d71582a1774287a7c62c7de305 100644 (file)
@@ -118,7 +118,7 @@ struct BlifDumper
                for (auto &it : inputs) {
                        RTLIL::Wire *wire = it.second;
                        for (int i = 0; i < wire->width; i++)
-                               fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
+                               fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i)));
                }
                fprintf(f, "\n");
 
@@ -126,7 +126,7 @@ struct BlifDumper
                for (auto &it : outputs) {
                        RTLIL::Wire *wire = it.second;
                        for (int i = 0; i < wire->width; i++)
-                               fprintf(f, " %s", cstr(RTLIL::SigSpec::grml(wire, i)));
+                               fprintf(f, " %s", cstr(RTLIL::SigSpec(wire, i)));
                }
                fprintf(f, "\n");
 
index f003c750d526b02ebdfc3b83486fa546bb0d8f88..74cf2499736db4daff5ba7f43637b3227beafa69 100644 (file)
@@ -271,7 +271,7 @@ struct EdifBackend : public Backend {
                                } else {
                                        fprintf(f, "          (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
                                        for (int i = 0; i < wire->width; i++) {
-                                               RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i));
+                                               RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, i));
                                                net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
                                        }
                                }
index dcb51d44d8e44e695874af6cfe3528af3635474f..3fe5199f332aa231041c9e414e8ed8639a2f7437 100644 (file)
@@ -369,13 +369,13 @@ sigspec:
        TOK_ID '[' TOK_INT ']' {
                if (current_module->wires.count($1) == 0)
                        rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-               $$ = new RTLIL::SigSpec(RTLIL::SigSpec::grml(current_module->wires[$1], $3));
+               $$ = new RTLIL::SigSpec(current_module->wires[$1], $3);
                free($1);
        } |
        TOK_ID '[' TOK_INT ':' TOK_INT ']' {
                if (current_module->wires.count($1) == 0)
                        rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-               $$ = new RTLIL::SigSpec(RTLIL::SigSpec::grml(current_module->wires[$1], $5, $3 - $5 + 1));
+               $$ = new RTLIL::SigSpec(current_module->wires[$1], $5, $3 - $5 + 1);
                free($1);
        } |
        '{' sigspec_list '}' {
index f5b84bc66b2a9efc2e1e277b04d0b4488d056475..6bb3e6126ab42eeceae273983235fb7a878e0447 100644 (file)
@@ -1331,13 +1331,11 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
        this->offset = 0;
 }
 
-RTLIL::SigChunk RTLIL::SigChunk::grml(RTLIL::Wire *wire, int offset, int width)
+RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
 {
-       RTLIL::SigChunk chunk;
-       chunk.wire = wire;
-       chunk.width = width;
-       chunk.offset = offset;
-       return chunk;
+       this->wire = wire;
+       this->width = width;
+       this->offset = offset;
 }
 
 RTLIL::SigChunk::SigChunk(const std::string &str)
@@ -1448,13 +1446,11 @@ RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire)
        check();
 }
 
-RTLIL::SigSpec RTLIL::SigSpec::grml(RTLIL::Wire *wire, int offset, int width)
+RTLIL::SigSpec::SigSpec(RTLIL::Wire *wire, int offset, int width)
 {
-       RTLIL::SigSpec sig;
-       sig.chunks_.push_back(RTLIL::SigChunk::grml(wire, offset, width));
-       sig.width_ = sig.chunks_.back().width;
-       sig.check();
-       return sig;
+       chunks_.push_back(RTLIL::SigChunk(wire, offset, width));
+       width_ = chunks_.back().width;
+       check();
 }
 
 RTLIL::SigSpec::SigSpec(const std::string &str)
@@ -2152,7 +2148,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
                        std::vector<std::string> index_tokens;
                        sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
                        if (index_tokens.size() == 1)
-                               sig.append(RTLIL::SigSpec::grml(wire, atoi(index_tokens.at(0).c_str())));
+                               sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
                        else {
                                int a = atoi(index_tokens.at(0).c_str());
                                int b = atoi(index_tokens.at(1).c_str());
@@ -2160,7 +2156,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
                                        int tmp = a;
                                        a = b, b = tmp;
                                }
-                               sig.append(RTLIL::SigSpec::grml(wire, a, b-a+1));
+                               sig.append(RTLIL::SigSpec(wire, a, b-a+1));
                        }
                } else
                        sig.append(wire);
index 542e685de34cd6f97460ee83e2762b2c1a648c39..8321465941ee40fe3ee8b57beb568ad98c4b7221 100644 (file)
@@ -463,9 +463,7 @@ struct RTLIL::SigChunk {
        SigChunk();
        SigChunk(const RTLIL::Const &value);
        SigChunk(RTLIL::Wire *wire);
-       SigChunk(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
-       SigChunk(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
-       static SigChunk grml(RTLIL::Wire *wire, int offset, int width = 1);
+       SigChunk(RTLIL::Wire *wire, int offset, int width = 1);
        SigChunk(const std::string &str);
        SigChunk(int val, int width = 32);
        SigChunk(RTLIL::State bit, int width = 1);
@@ -526,9 +524,7 @@ public:
        SigSpec(const RTLIL::Const &value);
        SigSpec(const RTLIL::SigChunk &chunk);
        SigSpec(RTLIL::Wire *wire);
-       SigSpec(RTLIL::Wire *wire, int width); // <-- using this will cause a linker error
-       SigSpec(RTLIL::Wire *wire, int width, int offset) __attribute__((deprecated));
-       static SigSpec grml(RTLIL::Wire *wire, int offset, int width = 1);
+       SigSpec(RTLIL::Wire *wire, int offset, int width = 1);
        SigSpec(const std::string &str);
        SigSpec(int val, int width = 32);
        SigSpec(RTLIL::State bit, int width = 1);
index d011b0ef5985905af0f61911d8f8d32d92609e17..cd179ebf0f7555b91a8169ed0227c1f0909b5fb1 100644 (file)
@@ -144,7 +144,7 @@ struct SigPool
        {
                RTLIL::SigSpec sig;
                for (auto &bit : bits) {
-                       sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
+                       sig.append(RTLIL::SigSpec(bit.first, bit.second));
                        break;
                }
                return sig;
@@ -154,7 +154,7 @@ struct SigPool
        {
                RTLIL::SigSpec sig;
                for (auto &bit : bits)
-                       sig.append(RTLIL::SigSpec::grml(bit.first, bit.second));
+                       sig.append(RTLIL::SigSpec(bit.first, bit.second));
                sig.sort_and_unify();
                return sig;
        }
index fa2c496043d8ef60dcb29503515ed25ddfdcb4fb..8cdd39b7ad57c1bff1ce83e4cfa36bdcf83336b4 100644 (file)
@@ -466,7 +466,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                        clk_str = clk_str.substr(1);
                }
                if (module->wires.count(RTLIL::escape_id(clk_str)) != 0)
-                       clk_sig = assign_map(RTLIL::SigSpec::grml(module->wires.at(RTLIL::escape_id(clk_str)), 0));
+                       clk_sig = assign_map(RTLIL::SigSpec(module->wires.at(RTLIL::escape_id(clk_str)), 0));
        }
 
        if (dff_mode && clk_sig.size() == 0)
index 1ac9664ad2df8f9c370477fb286d5d427933a7e1..9dda2ba89511c4d5d536a6e1195cef4e2e271002 100644 (file)
@@ -30,7 +30,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
        RTLIL::SigSpec cases_vector;
 
        for (int in_state : fullstate_cache)
-               cases_vector.append(RTLIL::SigSpec::grml(state_onehot, in_state));
+               cases_vector.append(RTLIL::SigSpec(state_onehot, in_state));
 
        for (auto &it : pattern_cache)
        {
@@ -47,7 +47,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
 
                for (int in_state : it.second)
                        if (fullstate_cache.count(in_state) == 0)
-                               or_sig.append(RTLIL::SigSpec::grml(state_onehot, in_state));
+                               or_sig.append(RTLIL::SigSpec(state_onehot, in_state));
                or_sig.optimize();
 
                if (or_sig.size() == 0)
@@ -215,7 +215,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
                for (size_t j = 0; j < state.bits.size(); j++)
                        if (state.bits[j] == RTLIL::State::S0 || state.bits[j] == RTLIL::State::S1) {
-                               sig_a.append(RTLIL::SigSpec::grml(state_wire, j));
+                               sig_a.append(RTLIL::SigSpec(state_wire, j));
                                sig_b.append(RTLIL::SigSpec(state.bits[j]));
                        }
                sig_a.optimize();
@@ -223,7 +223,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
                if (sig_b == RTLIL::SigSpec(RTLIL::State::S1))
                {
-                       module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(state_onehot, i), sig_a));
+                       module->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(state_onehot, i), sig_a));
                }
                else
                {
@@ -234,7 +234,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                        eq_cell->type = "$eq";
                        eq_cell->connections["\\A"] = sig_a;
                        eq_cell->connections["\\B"] = sig_b;
-                       eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(state_onehot, i);
+                       eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, i);
                        eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
                        eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
                        eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
@@ -266,7 +266,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                                fullstate_cache.erase(tr.state_in);
                }
 
-               implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec::grml(next_state_onehot, i));
+               implement_pattern_cache(module, pattern_cache, fullstate_cache, fsm_data.state_table.size(), state_onehot, ctrl_in, RTLIL::SigSpec(next_state_onehot, i));
        }
 
        if (encoding_is_onehot)
@@ -279,7 +279,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                                if (state.bits[j] == RTLIL::State::S1)
                                        bit_idx = j;
                        if (bit_idx >= 0)
-                               next_state_sig.replace(bit_idx, RTLIL::SigSpec::grml(next_state_onehot, i));
+                               next_state_sig.replace(bit_idx, RTLIL::SigSpec(next_state_onehot, i));
                }
                log_assert(!next_state_sig.has_marked_bits());
                module->connections.push_back(RTLIL::SigSig(next_state_wire, next_state_sig));
@@ -297,7 +297,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
                                sig_a = RTLIL::SigSpec(state);
                        } else {
                                sig_b.append(RTLIL::SigSpec(state));
-                               sig_s.append(RTLIL::SigSpec::grml(next_state_onehot, i));
+                               sig_s.append(RTLIL::SigSpec(next_state_onehot, i));
                        }
                }
 
index 45c01f74a93617b6a230d27cbbd51d128f2be23f..38eff99613ac84917bfb2984c0466a354ddb0d36 100644 (file)
@@ -613,7 +613,7 @@ struct MemoryShareWorker
                                        groups_en[key] = grouped_en->width;
                                        grouped_en->width++;
                                }
-                               en.append(RTLIL::SigSpec::grml(grouped_en, groups_en[key]));
+                               en.append(RTLIL::SigSpec(grouped_en, groups_en[key]));
                        }
 
                        module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
index 165bb25c962fb1bc4df58b35112027164748c85a..23fc48d5dfc00c6b95b1f58c28f4251828f64bd1 100644 (file)
@@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
        for (auto &it : module->wires) {
                RTLIL::Wire *wire = it.second;
                for (int i = 0; i < wire->width; i++) {
-                       RTLIL::SigSpec s1 = RTLIL::SigSpec::grml(wire, i), s2 = assign_map(s1);
+                       RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, i), s2 = assign_map(s1);
                        if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
                                assign_map.add(s1);
                }
index 0fe7657320b15e9b1dcbd4c47486ef3cbd27142b..804c51fd34dec4f66c46a7ca37722c5704dbb623 100644 (file)
@@ -81,7 +81,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
                if (sig.size() == 1 && comp == RTLIL::SigSpec(1,1))
                {
-                       mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++), sig));
+                       mod->connections.push_back(RTLIL::SigSig(RTLIL::SigSpec(cmp_wire, cmp_wire->width++), sig));
                }
                else
                {
@@ -103,7 +103,7 @@ static RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal,
 
                        eq_cell->connections["\\A"] = sig;
                        eq_cell->connections["\\B"] = comp;
-                       eq_cell->connections["\\Y"] = RTLIL::SigSpec::grml(cmp_wire, cmp_wire->width++);
+                       eq_cell->connections["\\Y"] = RTLIL::SigSpec(cmp_wire, cmp_wire->width++);
                }
        }
 
index 91b428126af7c679f9f6c6349627834a3405e0b6..902dedb62c7351563a77d1957914c063156b03b2 100644 (file)
@@ -260,8 +260,8 @@ struct VlogHammerReporter
                                for (int i = 0; i < int(inputs.size()); i++) {
                                        RTLIL::Wire *wire = module->wires.at(inputs[i]);
                                        for (int j = input_widths[i]-1; j >= 0; j--) {
-                                               ce.set(RTLIL::SigSpec::grml(wire, j), bits.back());
-                                               recorded_set_vars.append(RTLIL::SigSpec::grml(wire, j));
+                                               ce.set(RTLIL::SigSpec(wire, j), bits.back());
+                                               recorded_set_vars.append(RTLIL::SigSpec(wire, j));
                                                recorded_set_vals.bits.push_back(bits.back());
                                                bits.pop_back();
                                        }
index 51cf3ae0dbf16f4029ab9ae4720c1e35871e6d4a..12384e2ccaa2139d9b19295f149c9a8c60200b07 100644 (file)
@@ -174,7 +174,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
                                        eqx_cell->parameters["\\Y_WIDTH"] = 1;
                                        eqx_cell->parameters["\\A_SIGNED"] = 0;
                                        eqx_cell->parameters["\\B_SIGNED"] = 0;
-                                       eqx_cell->connections["\\A"] = RTLIL::SigSpec::grml(w2_gold, i);
+                                       eqx_cell->connections["\\A"] = RTLIL::SigSpec(w2_gold, i);
                                        eqx_cell->connections["\\B"] = RTLIL::State::Sx;
                                        eqx_cell->connections["\\Y"] = gold_x.extract(i, 1);
                                        miter_module->add(eqx_cell);
index c209e8ed71b9f72e5c39c9327dd98623ba357171..ede2fa88c7950cf164f4bfb5e3418ece0da34751 100644 (file)
@@ -292,8 +292,8 @@ struct ShareWorker
                        supercell->connections["\\Y"] = y;
                        module->add(supercell);
 
-                       RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
-                       RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
+                       RTLIL::SigSpec new_y1(y, 0, y1.size());
+                       RTLIL::SigSpec new_y2(y, 0, y2.size());
 
                        module->connections.push_back(RTLIL::SigSig(y1, new_y1));
                        module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -405,8 +405,8 @@ struct ShareWorker
                        supercell->connections["\\Y"] = y;
                        supercell->check();
 
-                       RTLIL::SigSpec new_y1 = RTLIL::SigSpec::grml(y, 0, y1.size());
-                       RTLIL::SigSpec new_y2 = RTLIL::SigSpec::grml(y, 0, y2.size());
+                       RTLIL::SigSpec new_y1(y, 0, y1.size());
+                       RTLIL::SigSpec new_y2(y, 0, y2.size());
 
                        module->connections.push_back(RTLIL::SigSig(y1, new_y1));
                        module->connections.push_back(RTLIL::SigSig(y2, new_y2));
@@ -620,7 +620,7 @@ struct ShareWorker
                RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
                for (auto &p : activation_patterns) {
                        all_cases_wire->width++;
-                       module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec::grml(all_cases_wire, all_cases_wire->width - 1));
+                       module->addEq(NEW_ID, p.first, p.second, RTLIL::SigSpec(all_cases_wire, all_cases_wire->width - 1));
                }
                if (all_cases_wire->width == 1)
                        return all_cases_wire;
index 988917b17f624bec772f5fbdab2a775fbd2473d5..1687a1ffbf3250bc6f184f110557a4abca444559 100644 (file)
@@ -315,7 +315,7 @@ namespace
                        RTLIL::Wire *wire = it.second;
                        if (wire->port_id > 0) {
                                for (int i = 0; i < wire->width; i++)
-                                       sig2port.insert(sigmap(RTLIL::SigSpec::grml(wire, i)), std::pair<std::string, int>(wire->name, i));
+                                       sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
                                cell->connections[wire->name] = RTLIL::SigSpec(RTLIL::State::Sz, wire->width);
                        }
                }
index 2cb76014cabcceed2cb606dd861609a627bf4bea..09147383a219a092ecabb5f74e437f95a6924326 100644 (file)
@@ -179,9 +179,9 @@ struct IopadmapPass : public Pass {
                                                RTLIL::Cell *cell = new RTLIL::Cell;
                                                cell->name = NEW_ID;
                                                cell->type = RTLIL::escape_id(celltype);
-                                               cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec::grml(wire, i);
+                                               cell->connections[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
                                                if (!portname2.empty())
-                                                       cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec::grml(new_wire, i);
+                                                       cell->connections[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
                                                if (!widthparam.empty())
                                                        cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
                                                if (!nameparam.empty())