then Vectorise because this creates the situation of Prefixed-Prefixed,
resulting in deep complexity in Hardware Decode at a critical juncture, as
well as introducing 96-bit instructions.
+* **All* of these Scalar instructions are candidates for Vectorisation.
+ Thus none of them may be 64-bit-Scalar-only.
*Three 75% allocations are thus genuinely needed*, all other options are unsuitable
for consideration.