Mon Oct 21 16:16:26 1996 Martin M. Hunt <hunt@pizza.cygnus.com>

	* interp.c (sim_resume): Change the way single-stepping and exceptions
 	are handled so single-stepping works again.

diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 95b2690c0650c4f63ba400c070f5438322f025fa..9f1b4ac281c6cb7eabe6c95de0a10b4338493b31 100644 (file)
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,8 @@
+Mon Oct 21 16:16:26 1996  Martin M. Hunt  <hunt@pizza.cygnus.com>
+
+       * interp.c (sim_resume): Change the way single-stepping and exceptions
+       are handled so single-stepping works again.
+
 Thu Oct 17 12:24:16 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
 
        * endian.c: Optimize simulated loads/stores on x86, AIX, and big

diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c
index d06b86bb84c40fa1f61a1de179ea637edda79bb2..21d48112c5771afc4a8af0d5e69240ada265ac50 100644 (file)
--- a/sim/d10v/interp.c
+++ b/sim/d10v/interp.c
@@ -317,11 +317,7 @@ sim_resume (step, siggnal)
 
 /*   (*d10v_callback->printf_filtered) (d10v_callback, "sim_resume (%d,%d)  PC=0x%x\n",step,siggnal,PC); */
 
- if (step)
-   State.exception = SIGTRAP;
- else
-   State.exception = 0;
- 
+  State.exception = 0;
  do
    {
      uint32 byte_pc = ((uint32)PC) << 2;
@@ -369,7 +365,10 @@ sim_resume (step, siggnal)
           PC++;
        }
    } 
- while (!State.exception);
+ while ( !State.exception && !step);
+
+ if (step && !State.exception)
+   State.exception = SIGTRAP;
 }
 
 int