verilog: set src attribute for primitives

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 837c14ad773e3e700e5bc10e4523c2c5505f109e..4886816495f8a43984a74af84fd6cde25c8b27e0 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1739,8 +1739,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
                        AstNode *node = children_list[1];
                        if (op_type != AST_POS)
-                               for (size_t i = 2; i < children_list.size(); i++)
+                               for (size_t i = 2; i < children_list.size(); i++) {
                                        node = new AstNode(op_type, node, children_list[i]);
+                                       node->location = location;
+                               }
                        if (invert_results)
                                node = new AstNode(AST_BIT_NOT, node);
 

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4a5aba79e509d7ab078c16351c49e962fc0bd5a7..f2ff685e995ee1995d45a595400eb3ec1b782b7d 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1747,7 +1747,9 @@ single_prim:
        /* no name */ {
                astbuf2 = astbuf1->clone();
                ast_stack.back()->children.push_back(astbuf2);
-       } '(' cell_port_list ')';
+       } '(' cell_port_list ')' {
+               SET_AST_NODE_LOC(astbuf2, @1, @$);
+       }
 
 cell_parameter_list_opt:
        '#' '(' cell_parameter_list ')' | /* empty */;