Add some debug to abc9

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 328f0e3c3fa326802fe52fb4bac27fa57cc2eacc..41ab9abeab3973d288c15e4db843d573afdf17b3 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -423,6 +423,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
        Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
 
+#if 0
+       std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig");
+       std::ifstream ifs;
+       ifs.open(buffer);
+       if (ifs.fail())
+               log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
+       buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
+       log_assert(!design->module("$__abc9__"));
+       AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
+       reader.parse_xaiger();
+       ifs.close();
+       Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v"));
+       design->remove(design->module("$__abc9__"));
+#endif
+
        design->selection_stack.pop_back();
 
        // Now 'unexpose' those wires by undoing
@@ -540,9 +555,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                log_assert(!design->module("$__abc9__"));
                AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
                reader.parse_xaiger();
-
                ifs.close();
 
+#if 0
+               Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v"));
+#endif
+
                log_header(design, "Re-integrating ABC9 results.\n");
                RTLIL::Module *mapped_mod = design->module("$__abc9__");
                if (mapped_mod == NULL)