1998-12-14 Dave Brolley <brolley@cygnus.com>
authorDave Brolley <brolley@redhat.com>
Mon, 14 Dec 1998 20:06:17 +0000 (20:06 +0000)
committerDave Brolley <brolley@redhat.com>
Mon, 14 Dec 1998 20:06:17 +0000 (20:06 +0000)
* sim/fr30/call.cgs: Test ret here as well.
* sim/fr30/ld.cgs: Remove bogus comment.
* sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
* sim/fr30/div.ms: New testcase.
* sim/fr30/st.cgs: New testcase.
* sim/fr30/sth.cgs: New testcase.
* sim/fr30/stb.cgs: New testcase.
* sim/fr30/mov.cgs: New testcase.
* sim/fr30/jmp.cgs: New testcase.
* sim/fr30/ret.cgs: New testcase.
* sim/fr30/int.cgs: New testcase.

sim/testsuite/ChangeLog
sim/testsuite/sim/fr30/div.ms [new file with mode: 0644]
sim/testsuite/sim/fr30/int.cgs [new file with mode: 0644]
sim/testsuite/sim/fr30/jmp.cgs [new file with mode: 0644]
sim/testsuite/sim/fr30/mov.cgs [new file with mode: 0644]
sim/testsuite/sim/fr30/ret.cgs [new file with mode: 0644]
sim/testsuite/sim/fr30/st.cgs [new file with mode: 0644]
sim/testsuite/sim/fr30/stb.cgs [new file with mode: 0644]
sim/testsuite/sim/fr30/sth.cgs [new file with mode: 0644]
sim/testsuite/sim/fr30/testutils.inc

index 27c19642d7a877e2dae8990d995f47b5e4cfdfb9..fe12f0e8af5a75884ec361a002a6f8b8d5210f2f 100644 (file)
@@ -1,3 +1,17 @@
+1998-12-14  Dave Brolley  <brolley@cygnus.com>
+
+       * sim/fr30/call.cgs: Test ret here as well.
+       * sim/fr30/ld.cgs: Remove bogus comment.
+       * sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
+       * sim/fr30/div.ms: New testcase.
+       * sim/fr30/st.cgs: New testcase.
+       * sim/fr30/sth.cgs: New testcase.
+       * sim/fr30/stb.cgs: New testcase.
+       * sim/fr30/mov.cgs: New testcase.
+       * sim/fr30/jmp.cgs: New testcase.
+       * sim/fr30/ret.cgs: New testcase.
+       * sim/fr30/int.cgs: New testcase.
+
 Thu Dec 10 18:46:25 1998  Dave Brolley  <brolley@cygnus.com>
 
        * sim/fr30/div0s.cgs: New testcase.
diff --git a/sim/testsuite/sim/fr30/div.ms b/sim/testsuite/sim/fr30/div.ms
new file mode 100644 (file)
index 0000000..d5d7173
--- /dev/null
@@ -0,0 +1,131 @@
+# fr30 testcase for division
+# mach(): fr30
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global div
+div:
+       ; example 1 from div0s the manual
+       mvi_h_gr        0x01234567,r2
+       mvi_h_dr        0xdeadbeef,mdh
+       mvi_h_dr        0xfedcba98,mdl
+       div0s           r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div2            r2
+       div3
+       div4s
+       test_h_gr       0x01234567,r2
+       test_h_dr       0xffffffff,mdh
+       test_h_dr       0xffffffff,mdl
+       test_dbits      0x3
+
+       ; example 2 from div0s the manual
+       mvi_h_dr        0xdeadbeef,mdh
+       mvi_h_dr        0xfedcba98,mdl
+       mvi_h_gr        0x1234567,r2
+       mvi_h_gr        1,r0
+       mvi_h_gr        32,r1
+       div0s           r2
+loop1: sub             r0,r1
+       bne:d           loop1
+       div1            r2
+       div2            r2
+       div3
+       div4s
+       test_h_gr       0x01234567,r2
+       test_h_dr       0xffffffff,mdh
+       test_h_dr       0xffffffff,mdl
+       test_dbits      0x3
+
+       ; example 1 from div0u in the manual
+       mvi_h_gr        0x01234567,r2
+       mvi_h_dr        0xdeadbeef,mdh
+       mvi_h_dr        0xfedcba98,mdl
+       div0u           r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       div1            r2
+       test_h_gr       0x01234567,r2
+       test_h_dr       0x00000078,mdh
+       test_h_dr       0x000000e0,mdl
+       test_dbits      0x0
+
+       ; example 2 from div0u in the manual
+       mvi_h_dr        0xdeadbeef,mdh
+       mvi_h_dr        0xfedcba98,mdl
+       mvi_h_gr        0x1234567,r2
+       mvi_h_gr        1,r0
+       mvi_h_gr        32,r1
+       div0u           r2
+loop2: sub             r0,r1
+       bne:d           loop2
+       div1            r2
+       test_h_gr       0x01234567,r2
+       test_h_dr       0x00000078,mdh
+       test_h_dr       0x000000e0,mdl
+       test_dbits      0x0
+
+       pass
diff --git a/sim/testsuite/sim/fr30/int.cgs b/sim/testsuite/sim/fr30/int.cgs
new file mode 100644 (file)
index 0000000..a48bca9
--- /dev/null
@@ -0,0 +1,20 @@
+# fr30 testcase for add $u8
+# mach(): fr30
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global add
+add:
+       ; Test add $Rj,$Ri
+       mvi_h_gr        1,r7
+       mvi_h_gr        2,r8
+       set_cc          0x0f            ; Set mask opposite of expected
+       add             r7,r8
+       test_cc         0 0 0 0
+       test_h_gr       3,r8
+
+
+       pass
diff --git a/sim/testsuite/sim/fr30/jmp.cgs b/sim/testsuite/sim/fr30/jmp.cgs
new file mode 100644 (file)
index 0000000..db4af22
--- /dev/null
@@ -0,0 +1,29 @@
+# fr30 testcase for jmp @$Ri
+# mach(): fr30
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global jmp
+
+       ; Test jmp $Ri
+       mvi_h_gr        #func1,r0
+       set_cc          0x0f            ; condition codes shouldn't change
+jmp1:
+       jmp             @r0
+       fail
+func1:
+       test_cc         1 1 1 1
+       mvi_h_gr        #func2,r0
+       set_cc          0x0f            ; condition codes shouldn't change
+jmp2:
+       jmp:d           @r0
+       ldi:8           1,r0            ; Must assume this works
+       fail
+func2:
+       test_cc         1 1 1 1
+       testr_h_gr      1,r0
+
+       pass
diff --git a/sim/testsuite/sim/fr30/mov.cgs b/sim/testsuite/sim/fr30/mov.cgs
new file mode 100644 (file)
index 0000000..bf99252
--- /dev/null
@@ -0,0 +1,108 @@
+# fr30 testcase for mov $Rj,$Ri
+# mach(): fr30
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global mov
+mov:
+       ; Test mov $Rj,$Ri
+       mvi_h_gr        1,r7
+       mvi_h_dr        0xa,tbr
+       mvi_h_dr        0xb,rp
+       mvi_h_dr        0xc,mdh
+       mvi_h_dr        0xd,mdl
+       mvr_h_gr        sp,ssp
+       mvr_h_gr        sp,usp
+
+       mov             r7,r7
+       set_cc          0x0f            ; Condition codes should not change
+       test_cc         1 1 1 1
+       test_h_gr       1,r7
+
+       mov             r7,r8
+       set_cc          0x0e            ; Condition codes should not change
+       test_cc         1 1 1 0
+       test_h_gr       1,r7
+       test_h_gr       1,r8
+
+       ; Test mov $Rs,$Ri
+       set_cc          0x0d            ; Condition codes should not change
+       mov             tbr,r7
+       test_cc         1 1 0 1
+       test_h_gr       0xa,r7
+
+       set_cc          0x0c            ; Condition codes should not change
+       mov             rp,r7
+       test_cc         1 1 0 0
+       test_h_gr       0xb,r7
+
+       set_cc          0x0b            ; Condition codes should not change
+       mov             mdh,r7
+       test_cc         1 0 1 1
+       test_h_gr       0xc,r7
+
+       set_cc          0x0a            ; Condition codes should not change
+       mov             mdl,r7
+       test_cc         1 0 1 0
+       test_h_gr       0xd,r7
+
+       set_cc          0x09            ; Condition codes should not change
+       mov             usp,r7
+       test_cc         1 0 0 1
+       testr_h_gr      sp,r7
+
+       set_cc          0x08            ; Condition codes should not change
+       mov             ssp,r7
+       test_cc         1 0 0 0
+       testr_h_gr      sp,r7
+
+       ; Test mov $Ri,$Rs
+       set_cc          0x07            ; Condition codes should not change
+       mov             r8,tbr
+       test_cc         0 1 1 1
+       test_h_dr       0x1,tbr
+
+       set_cc          0x06            ; Condition codes should not change
+       mov             r8,rp
+       test_cc         0 1 1 0
+       test_h_dr       0x1,rp
+
+       set_cc          0x05            ; Condition codes should not change
+       mov             r8,mdh
+       test_cc         0 1 0 1
+       test_h_dr       0x1,mdh
+
+       set_cc          0x04            ; Condition codes should not change
+       mov             r8,mdl
+       test_cc         0 1 0 0
+       test_h_dr       0x1,mdl
+
+       set_cc          0x03            ; Condition codes should not change
+       mov             r8,ssp
+       test_cc         0 0 1 1
+       test_h_dr       0x1,ssp
+
+       set_cc          0x02            ; Condition codes should not change
+       mov             r8,usp
+       test_cc         0 0 1 0
+       test_h_dr       0x1,usp
+
+       ; Test mov $PS,$Ri
+       set_cc          0x01            ; Condition codes affect result
+       set_dbits       0x3
+       mov             ps,r7
+       test_cc         0 0 0 1
+       test_h_gr       0x00000601,r7
+
+       ; Test mov $Ri,PS
+       set_cc          0x01            ; Set opposite of expected
+       set_dbits       0x1             ; Set opposite of expected
+       mvi_h_gr        0x0000040e,r7
+       mov             r7,PS
+       test_cc         1 1 1 0
+       test_dbits      0x2
+
+       pass
diff --git a/sim/testsuite/sim/fr30/ret.cgs b/sim/testsuite/sim/fr30/ret.cgs
new file mode 100644 (file)
index 0000000..413840e
--- /dev/null
@@ -0,0 +1,69 @@
+# fr30 testcase for call @$Ri
+# mach(): fr30
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global call
+
+       ; Test call $Ri
+       mvi_h_gr        0xdeadbeef,r9
+       mvi_h_gr        #func1,r0
+       set_cc          0x0f            ; condition codes shouldn't change
+call1:
+       call            @r0
+       test_h_gr       0xbeefdead,r9
+       pass
+
+func1:
+       test_cc         1 1 1 1
+       mvi_h_gr        #call1,r7
+       inci_h_gr       2,r7
+       testr_h_dr      r7,rp
+       save_rp
+
+       mvi_h_gr        #func2,r0
+       set_cc          0x0f            ; condition codes shouldn't change
+call2:
+       call:d          @r0
+       ldi:8           1,r0            ; Must assume this works
+       restore_rp
+       ret
+func2:
+       test_cc         1 1 1 1
+       mvi_h_gr        #call2,r7
+       inci_h_gr       4,r7
+       testr_h_dr      r7,rp
+       testr_h_gr      1,r0
+       save_rp
+
+       set_cc          0x0f            ; condition codes shouldn't change
+call3:
+       call            func3
+       restore_rp
+       ret
+func3:
+       test_cc         1 1 1 1
+       mvi_h_gr        #call3,r7
+       inci_h_gr       2,r7
+       testr_h_dr      r7,rp
+       save_rp
+
+       set_cc          0x0f            ; condition codes shouldn't change
+call4:
+       call:d          func4
+       ldi:8           1,r0            ; Must assume this works
+       restore_rp
+       ret
+func4:
+       test_cc         1 1 1 1
+       mvi_h_gr        #call4,r7
+       inci_h_gr       4,r7
+       testr_h_dr      r7,rp
+       testr_h_gr      1,r0
+       mvi_h_gr        0xbeefdead,r9
+       ret
+
+       fail
diff --git a/sim/testsuite/sim/fr30/st.cgs b/sim/testsuite/sim/fr30/st.cgs
new file mode 100644 (file)
index 0000000..e458d14
--- /dev/null
@@ -0,0 +1,194 @@
+# fr30 testcase for
+# mach(): fr30
+#  st $Ri,@$Rj
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global st
+st:
+       mvr_h_gr        sp,r9           ; Save stack pointer
+       ; Test st $Ri,@Rj
+       mvi_h_gr        0xdeadbeef,r8
+       set_cc          0x0f            ; Condition codes should not change
+       st              r8,@sp
+       test_cc         1 1 1 1
+       test_h_mem      0xdeadbeef,sp
+       test_h_gr       0xdeadbeef,r8
+
+       ; Test st $Ri,@(R13,Rj)
+       mvi_h_gr        0xbeefdead,r8
+       mvr_h_gr        sp,r1
+       inci_h_gr       -8,sp
+       mvr_h_gr        sp,r2
+       inci_h_gr       4,sp
+
+       mvi_h_gr        4,r13
+       set_cc          0x0e            ; Condition codes should not change
+       st              r8,@(r13,sp)
+       test_cc         1 1 1 0
+       test_h_mem      0xbeefdead,r1
+       test_h_gr       0xbeefdead,r8
+
+       mvi_h_gr        0,r13
+       set_cc          0x0d            ; Condition codes should not change
+       st              r8,@(r13,sp)
+       test_cc         1 1 0 1
+       test_h_mem      0xbeefdead,sp
+       test_h_gr       0xbeefdead,r8
+
+       mvi_h_gr        -4,r13
+       set_cc          0x0c            ; Condition codes should not change
+       st              r8,@(r13,sp)
+       test_cc         1 1 0 0
+       test_h_mem      0xbeefdead,r2
+       test_h_gr       0xbeefdead,r8
+
+       ; Test st $Ri,@(R14,$disp10)
+       mvi_h_gr        0xdeadbeef,r8
+       mvr_h_gr        r9,sp           ; Restore stack pointer
+       mvr_h_gr        sp,r14
+       inci_h_gr       -508,r14
+       mvr_h_gr        r14,r2
+       inci_h_gr       -512,r14
+       mvr_h_gr        r14,r3
+       inci_h_gr       512,r14
+
+       set_cc          0x0b            ; Condition codes should not change
+       st              r8,@(r14,508)
+       test_cc         1 0 1 1
+       test_h_mem      0xdeadbeef,r1
+       test_h_gr       0xdeadbeef,r8
+
+       set_cc          0x0a            ; Condition codes should not change
+       st              r8,@(r14,0)
+       test_cc         1 0 1 0
+       test_h_mem      0xdeadbeef,r2
+       test_h_gr       0xdeadbeef,r8
+
+       set_cc          0x09            ; Condition codes should not change
+       st              r8,@(r14,-512)
+       test_cc         1 0 0 1
+       test_h_mem      0xdeadbeef,r3
+       test_h_gr       0xdeadbeef,r8
+
+       ; Test st $Ri,@(R15,$udisp6)
+       mvi_h_gr        0xbeefdead,r8
+       mvr_h_gr        r9,sp           ; Restore stack pointer
+       inci_h_gr       -60,sp
+
+       set_cc          0x08            ; Condition codes should not change
+       st              r8,@(r15,60)
+       test_cc         1 0 0 0
+       test_h_mem      0xbeefdead,r9
+       test_h_gr       0xbeefdead,r8
+
+       set_cc          0x07            ; Condition codes should not change
+       st              r8,@(r15,0)
+       test_cc         0 1 1 1
+       test_h_mem      0xbeefdead,r9
+       test_h_gr       0xbeefdead,r8
+
+       ; Test st $Ri,@-R15
+       mvr_h_gr        r9,sp           ; Restore stack pointer
+       mvr_h_gr        r9,r10
+
+       set_cc          0x06            ; Condition codes should not change
+       st              r15,@-r15
+       test_cc         0 1 1 0
+       testr_h_mem     r9,sp           ; original value stored
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       mvi_h_gr        0xdeadbeef,r8
+       set_cc          0x05            ; Condition codes should not change
+       st              r8,@-r15
+       test_cc         0 1 0 1
+       test_h_mem      0xdeadbeef,sp
+       test_h_gr       0xdeadbeef,r8
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       ; Test st $Rs,@-R15
+       mvr_h_gr        r9,sp           ; Restore stack pointer
+       mvr_h_gr        r9,r10
+       mvi_h_dr        0xbeefdead,tbr
+       mvi_h_dr        0xdeadbeef,rp
+       mvi_h_dr        0x0000dead,mdh
+       mvi_h_dr        0xbeef0000,mdl
+
+       set_cc          0x04            ; Condition codes should not change
+       st              tbr,@-r15
+       test_cc         0 1 0 0
+       test_h_mem      0xbeefdead,sp
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       set_cc          0x03            ; Condition codes should not change
+       st              rp,@-r15
+       test_cc         0 0 1 1
+       test_h_mem      0xdeadbeef,sp
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       set_cc          0x02            ; Condition codes should not change
+       st              mdh,@-r15
+       test_cc         0 0 1 0
+       test_h_mem      0x0000dead,sp
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       set_cc          0x01            ; Condition codes should not change
+       st              mdl,@-r15
+       test_cc         0 0 0 1
+       test_h_mem      0xbeef0000,sp
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       mvr_h_gr        sp,usp
+       set_s_user
+       set_cc          0x00            ; Condition codes should not change
+       st              ssp,@-r15
+       test_cc         0 0 0 0
+       testr_h_mem     r10,sp
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       set_cc          0x00            ; Condition codes should not change
+       st              usp,@-r15
+       test_cc         0 0 0 0
+       testr_h_mem     r10,sp          ; original value stored
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       mvr_h_gr        sp,ssp
+       set_s_system
+       set_cc          0x00            ; Condition codes should not change
+       st              usp,@-r15
+       test_cc         0 0 0 0
+       testr_h_mem     r10,sp
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       set_cc          0x00            ; Condition codes should not change
+       st              ssp,@-r15
+       test_cc         0 0 0 0
+       testr_h_mem     r10,sp          ; original value stored
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       ; Test st $PS,@-R15
+       mvr_h_gr        r9,sp           ; Restore stack pointer
+       mvr_h_gr        r9,r10
+
+       set_cc          0x0f            ; Condition codes affect result
+       set_dbits       3               ; Division bits affect result
+       st              ps,@-r15
+       test_cc         1 1 1 1
+       test_h_mem      0x0000060f,sp
+       inci_h_gr       -4,r10
+       testr_h_gr      r10,sp          ; was decremented
+
+       pass
diff --git a/sim/testsuite/sim/fr30/stb.cgs b/sim/testsuite/sim/fr30/stb.cgs
new file mode 100644 (file)
index 0000000..d9d4fd0
--- /dev/null
@@ -0,0 +1,84 @@
+# fr30 testcase for
+# mach(): fr30
+#  stb $Ri,@$Rj
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global stb
+stb:
+       mvr_h_gr        sp,r9           ; Save stack pointer
+       ; Test stb $Ri,@Rj
+       mvi_h_mem       0xdeadbeef,sp
+       mvi_h_gr        0xaaaaaafe,r8
+       set_cc          0x0f            ; Condition codes should not change
+       stb             r8,@sp
+       test_cc         1 1 1 1
+       test_h_mem      0xfeadbeef,sp
+       test_h_gr       0xaaaaaafe,r8
+
+       ; Test stb $Ri,@(R13,Rj)
+       mvi_h_mem       0xbeefdead,sp
+       mvi_h_gr        0xaaaaaade,r8
+       mvr_h_gr        sp,r1
+       inci_h_gr       -8,sp
+       mvr_h_gr        sp,r2
+       mvi_h_mem       0xbeefdead,sp
+       inci_h_gr       4,sp
+       mvi_h_mem       0xbeefdead,sp
+
+       mvi_h_gr        4,r13
+       set_cc          0x0e            ; Condition codes should not change
+       stb             r8,@(r13,sp)
+       test_cc         1 1 1 0
+       test_h_mem      0xdeefdead,r1
+       test_h_gr       0xaaaaaade,r8
+
+       mvi_h_gr        0,r13
+       set_cc          0x0d            ; Condition codes should not change
+       stb             r8,@(r13,sp)
+       test_cc         1 1 0 1
+       test_h_mem      0xdeefdead,sp
+       test_h_gr       0xaaaaaade,r8
+
+       mvi_h_gr        -4,r13
+       set_cc          0x0c            ; Condition codes should not change
+       stb             r8,@(r13,sp)
+       test_cc         1 1 0 0
+       test_h_mem      0xdeefdead,r2
+       test_h_gr       0xaaaaaade,r8
+
+       ; Test stb $Ri,@(R14,$disp8
+       mvr_h_gr        r9,sp           ; Restore stack pointer
+       mvi_h_gr        0xaaaaaafe,r8
+       mvi_h_mem       0xdeadbeef,sp
+       mvr_h_gr        sp,r14
+       inci_h_gr       -127,r14
+       mvr_h_gr        r14,r2
+       mvi_h_mem       0xdeadbeef,r14
+       inci_h_gr       -128,r14
+       mvr_h_gr        r14,r3
+       mvi_h_mem       0xdeadbeef,r14
+       inci_h_gr       128,r14
+
+       set_cc          0x0b            ; Condition codes should not change
+       stb             r8,@(r14,127)
+       test_cc         1 0 1 1
+       test_h_mem      0xfeadbeef,r1
+       test_h_gr       0xaaaaaafe,r8
+
+       set_cc          0x0a            ; Condition codes should not change
+       stb             r8,@(r14,0)
+       test_cc         1 0 1 0
+       test_h_mem      0xfeadbeef,r2
+       test_h_gr       0xaaaaaafe,r8
+
+       set_cc          0x09            ; Condition codes should not change
+       stb             r8,@(r14,-128)
+       test_cc         1 0 0 1
+       test_h_mem      0xfeadbeef,r3
+       test_h_gr       0xaaaaaafe,r8
+
+       pass
diff --git a/sim/testsuite/sim/fr30/sth.cgs b/sim/testsuite/sim/fr30/sth.cgs
new file mode 100644 (file)
index 0000000..64c83e6
--- /dev/null
@@ -0,0 +1,84 @@
+# fr30 testcase for
+# mach(): fr30
+#  sth $Ri,@$Rj
+
+       .include "testutils.inc"
+
+       START
+
+       .text
+       .global sth
+sth:
+       mvr_h_gr        sp,r9           ; Save stack pointer
+       ; Test sth $Ri,@Rj
+       mvi_h_mem       0xdeadbeef,sp
+       mvi_h_gr        0xaaaabeef,r8
+       set_cc          0x0f            ; Condition codes should not change
+       sth             r8,@sp
+       test_cc         1 1 1 1
+       test_h_mem      0xbeefbeef,sp
+       test_h_gr       0xaaaabeef,r8
+
+       ; Test sth $Ri,@(R13,Rj)
+       mvi_h_mem       0xbeefdead,sp
+       mvi_h_gr        0xaaaadead,r8
+       mvr_h_gr        sp,r1
+       inci_h_gr       -8,sp
+       mvr_h_gr        sp,r2
+       mvi_h_mem       0xbeefdead,sp
+       inci_h_gr       4,sp
+       mvi_h_mem       0xbeefdead,sp
+
+       mvi_h_gr        4,r13
+       set_cc          0x0e            ; Condition codes should not change
+       sth             r8,@(r13,sp)
+       test_cc         1 1 1 0
+       test_h_mem      0xdeaddead,r1
+       test_h_gr       0xaaaadead,r8
+
+       mvi_h_gr        0,r13
+       set_cc          0x0d            ; Condition codes should not change
+       sth             r8,@(r13,sp)
+       test_cc         1 1 0 1
+       test_h_mem      0xdeaddead,sp
+       test_h_gr       0xaaaadead,r8
+
+       mvi_h_gr        -4,r13
+       set_cc          0x0c            ; Condition codes should not change
+       sth             r8,@(r13,sp)
+       test_cc         1 1 0 0
+       test_h_mem      0xdeaddead,r2
+       test_h_gr       0xaaaadead,r8
+
+       ; Test sth $Ri,@(R14,$disp9)
+       mvr_h_gr        r9,sp           ; Restore stack pointer
+       mvi_h_gr        0xaaaabeef,r8
+       mvi_h_mem       0xdeadbeef,sp
+       mvr_h_gr        sp,r14
+       inci_h_gr       -254,r14
+       mvr_h_gr        r14,r2
+       mvi_h_mem       0xdeadbeef,r14
+       inci_h_gr       -256,r14
+       mvr_h_gr        r14,r3
+       mvi_h_mem       0xdeadbeef,r14
+       inci_h_gr       256,r14
+
+       set_cc          0x0b            ; Condition codes should not change
+       sth             r8,@(r14,254)
+       test_cc         1 0 1 1
+       test_h_mem      0xbeefbeef,r1
+       test_h_gr       0xaaaabeef,r8
+
+       set_cc          0x0a            ; Condition codes should not change
+       sth             r8,@(r14,0)
+       test_cc         1 0 1 0
+       test_h_mem      0xbeefbeef,r2
+       test_h_gr       0xaaaabeef,r8
+
+       set_cc          0x09            ; Condition codes should not change
+       sth             r8,@(r14,-256)
+       test_cc         1 0 0 1
+       test_h_mem      0xbeefbeef,r3
+       test_h_gr       0xaaaabeef,r8
+
+       pass
index f335ea1d0f873a668714722ddd3d620b0f45525c..2b9e489f0635ef5274a55fa2f107726d388e9f30 100644 (file)
@@ -10,6 +10,8 @@ passmsg:
        .global _start
 _start:
        ldi32 0x7fffc,sp        ; TODO -- what's a good value for this?
+       mov   sp,usp
+       mov   sp,ssp
        .endm
 
 ; Exit with return code
@@ -196,3 +198,13 @@ test_cc\@:
        and r4,r0
        test_h_gr \val,r0
        .endm
+
+; Save the return pointer
+       .macro save_rp
+       st rp,@-R15
+       .ENDM
+
+; restore the return pointer
+       .macro restore_rp
+       ld @R15+,rp
+       .endm