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Fix wire numbering
author
Eddie Hung
<eddie@fpgeh.com>
Tue, 16 Apr 2019 21:53:01 +0000
(14:53 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Tue, 16 Apr 2019 21:53:01 +0000
(14:53 -0700)
backends/aiger/xaiger.cc
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diff --git
a/backends/aiger/xaiger.cc
b/backends/aiger/xaiger.cc
index 7c76978746be4834b11dbd64b2bca7d124578e1f..66ab3878e9f4c9181571c9eb5a5d9858bdf0896f 100644
(file)
--- a/
backends/aiger/xaiger.cc
+++ b/
backends/aiger/xaiger.cc
@@
-589,11
+589,12
@@
struct XAigerWriter
if (cell->input(c.first)) {
box_inputs += c.second.size();
if (holes_cell) {
- holes_wire = holes_module->wire(stringf("\\i%d", num_inputs
++
));
+ holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
if (!holes_wire) {
holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
holes_wire->port_input = true;
}
+ ++num_inputs;
holes_cell->setPort(c.first, holes_wire);
}
}