fhdl/verilog: implicit get_fragment

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c5ba2272a0bae12a96734ca2f8b709c6883f6fdb..795fcf00627922096c5c24a784509938a454bfff 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -260,6 +260,8 @@ def convert(f, ios=None, name="top",
   return_ns=False,
   special_overrides=dict(),
   display_run=False):
+       if not isinstance(f, Fragment):
+               f = f.get_fragment()
        if ios is None:
                ios = set()
        if clock_domains is None: