DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
vaddr, req->getSize());
+ DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",
+ pstate, hpstate, lsuIm, part_id);
assert(req->getAsi() == ASI_IMPLICIT);
return new InstructionAccessException;
}
- if (lsuIm) {
+ if (!lsuIm) {
e = lookup(req->getVaddr(), part_id, true);
real = true;
context = 0;
asi = (ASI)req->getAsi();
DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
vaddr, size, asi);
-
+ DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",
+ pstate, hpstate, lsuDm, part_id);
if (asi == ASI_IMPLICIT)
implicit = true;
goto handleScratchRegAccess;
if (AsiIsQueue(asi))
goto handleQueueRegAccess;
+ if (AsiIsSparcError(asi))
+ goto handleSparcErrorRegAccess;
if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
panic("Accessing ASI %#X. Should we?\n", asi);
}
goto regAccessOk;
+handleSparcErrorRegAccess:
+ if (!hpriv) {
+ if (priv) {
+ writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
+ return new DataAccessException;
+ } else {
+ writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
+ return new PrivilegedAction;
+ }
+ }
+ goto regAccessOk;
+
+
regAccessOk:
handleMmuRegAccess:
DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
Addr va = pkt->getAddr();
ASI asi = (ASI)pkt->req->getAsi();
- DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n",
+ DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
(uint32_t)asi, va, data);
switch (asi) {
}
break;
case ASI_QUEUE:
- assert(mbits(va,13,6) == va);
+ assert(mbits(data,13,6) == data);
tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
(va >> 4) - 0x3c, data);
break;
assert(va == 0);
tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
break;
+ case ASI_SPARC_ERROR_EN_REG:
+ case ASI_SPARC_ERROR_STATUS_REG:
+ warn("Ignoring write to SPARC ERROR regsiter\n");
+ break;
case ASI_HYP_SCRATCHPAD:
case ASI_SCRATCHPAD:
tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
int64_t time;
int oldLevel, newLevel;
switch (miscReg) {
- /* Full system only ASRs */
- case MISCREG_SOFTINT:
- // Check if we are going to interrupt because of something
- oldLevel = InterruptLevel(softint);
- newLevel = InterruptLevel(val);
- setReg(miscReg, val);
- if (newLevel > oldLevel)
- ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
- //tc->getCpuPtr()->checkInterrupts = true;
- panic("SOFTINT not implemented\n");
- break;
-
- case MISCREG_SOFTINT_CLR:
- return setRegWithEffect(miscReg, ~val & softint, tc);
- case MISCREG_SOFTINT_SET:
- return setRegWithEffect(miscReg, val | softint, tc);
-
- case MISCREG_TICK_CMPR:
- if (tickCompare == NULL)
- tickCompare = new TickCompareEvent(this, tc);
- setReg(miscReg, val);
- if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
+ /* Full system only ASRs */
+ case MISCREG_SOFTINT:
+ // Check if we are going to interrupt because of something
+ oldLevel = InterruptLevel(softint);
+ newLevel = InterruptLevel(val);
+ setReg(miscReg, val);
+ //if (newLevel > oldLevel)
+ ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
+ //tc->getCpuPtr()->checkInterrupts = true;
+ //panic("SOFTINT not implemented\n");
+ warn("Writing to softint not really supported, writing: %#x\n", val);
+ break;
+
+ case MISCREG_SOFTINT_CLR:
+ return setRegWithEffect(miscReg, ~val & softint, tc);
+ case MISCREG_SOFTINT_SET:
+ return setRegWithEffect(miscReg, val | softint, tc);
+
+ case MISCREG_TICK_CMPR:
+ if (tickCompare == NULL)
+ tickCompare = new TickCompareEvent(this, tc);
+ setReg(miscReg, val);
+ if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
tickCompare->deschedule();
- time = (tick_cmpr & mask(63)) - (tick & mask(63));
- if (!(tick_cmpr & ~mask(63)) && time > 0)
- tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
- break;
-
- case MISCREG_STICK_CMPR:
- if (sTickCompare == NULL)
- sTickCompare = new STickCompareEvent(this, tc);
- setReg(miscReg, val);
- if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
- sTickCompare->deschedule();
- time = (stick_cmpr & mask(63)) - (stick & mask(63));
- if (!(stick_cmpr & ~mask(63)) && time > 0)
- sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
- break;
-
- case MISCREG_PIL:
- setReg(miscReg, val);
- //tc->getCpuPtr()->checkInterrupts;
- // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
- panic("PIL not implemented\n");
- break;
-
- case MISCREG_HVER:
- panic("Shouldn't be writing HVER\n");
-
- case MISCREG_HTBA:
- // clear lower 7 bits on writes.
- setReg(miscReg, val & ULL(~0x7FFF));
- break;
-
- case MISCREG_HSTICK_CMPR:
- if (hSTickCompare == NULL)
- hSTickCompare = new HSTickCompareEvent(this, tc);
- setReg(miscReg, val);
- if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
- hSTickCompare->deschedule();
- time = (hstick_cmpr & mask(63)) - (stick & mask(63));
- if (!(hstick_cmpr & ~mask(63)) && time > 0)
- hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
- break;
-
- case MISCREG_HPSTATE:
- case MISCREG_HTSTATE:
- case MISCREG_STRAND_STS_REG:
- setReg(miscReg, val);
- break;
-
- default:
- panic("Invalid write to FS misc register\n");
+ time = (tick_cmpr & mask(63)) - (tick & mask(63));
+ if (!(tick_cmpr & ~mask(63)) && time > 0)
+ tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
+ warn ("writing to TICK compare register %#X\n", val);
+ break;
+
+ case MISCREG_STICK_CMPR:
+ if (sTickCompare == NULL)
+ sTickCompare = new STickCompareEvent(this, tc);
+ setReg(miscReg, val);
+ if ((stick_cmpr & mask(63)) && sTickCompare->scheduled())
+ sTickCompare->deschedule();
+ time = (stick_cmpr & mask(63)) - (stick & mask(63));
+ if (!(stick_cmpr & ~mask(63)) && time > 0)
+ sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
+ warn ("writing to sTICK compare register value %#X\n", val);
+ break;
+
+ case MISCREG_PIL:
+ setReg(miscReg, val);
+ //tc->getCpuPtr()->checkInterrupts;
+ // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX
+ // panic("PIL not implemented\n");
+ warn ("PIL not implemented writing %#X\n", val);
+ break;
+
+ case MISCREG_HVER:
+ panic("Shouldn't be writing HVER\n");
+
+ case MISCREG_HTBA:
+ // clear lower 7 bits on writes.
+ setReg(miscReg, val & ULL(~0x7FFF));
+ break;
+
+ case MISCREG_QUEUE_CPU_MONDO_HEAD:
+ case MISCREG_QUEUE_CPU_MONDO_TAIL:
+ case MISCREG_QUEUE_DEV_MONDO_HEAD:
+ case MISCREG_QUEUE_DEV_MONDO_TAIL:
+ case MISCREG_QUEUE_RES_ERROR_HEAD:
+ case MISCREG_QUEUE_RES_ERROR_TAIL:
+ case MISCREG_QUEUE_NRES_ERROR_HEAD:
+ case MISCREG_QUEUE_NRES_ERROR_TAIL:
+ setReg(miscReg, val);
+ tc->getCpuPtr()->checkInterrupts = true;
+ break;
+
+ case MISCREG_HSTICK_CMPR:
+ if (hSTickCompare == NULL)
+ hSTickCompare = new HSTickCompareEvent(this, tc);
+ setReg(miscReg, val);
+ if ((hstick_cmpr & mask(63)) && hSTickCompare->scheduled())
+ hSTickCompare->deschedule();
+ time = (hstick_cmpr & mask(63)) - (stick & mask(63));
+ if (!(hstick_cmpr & ~mask(63)) && time > 0)
+ hSTickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
+ warn ("writing to hsTICK compare register value %#X\n", val);
+ break;
+
+ case MISCREG_HPSTATE:
+ // i.d. is always set on any hpstate write
+ setReg(miscReg, val | 1 << 11);
+ break;
+ case MISCREG_HTSTATE:
+ case MISCREG_STRAND_STS_REG:
+ setReg(miscReg, val);
+ break;
+
+ default:
+ panic("Invalid write to FS misc register\n");
}
}
MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
-
- /* Privileged registers. */
- case MISCREG_SOFTINT:
- case MISCREG_TICK_CMPR:
- case MISCREG_STICK_CMPR:
- case MISCREG_PIL:
- case MISCREG_HPSTATE:
- case MISCREG_HINTP:
- case MISCREG_HTSTATE:
- case MISCREG_STRAND_STS_REG:
- case MISCREG_HSTICK_CMPR:
- return readReg(miscReg) ;
-
- case MISCREG_HTBA:
- return readReg(miscReg) & ULL(~0x7FFF);
- case MISCREG_HVER:
- return NWindows | MaxTL << 8 | MaxGL << 16;
-
- default:
- panic("Invalid read to FS misc register\n");
+ /* Privileged registers. */
+ case MISCREG_QUEUE_CPU_MONDO_HEAD:
+ case MISCREG_QUEUE_CPU_MONDO_TAIL:
+ case MISCREG_QUEUE_DEV_MONDO_HEAD:
+ case MISCREG_QUEUE_DEV_MONDO_TAIL:
+ case MISCREG_QUEUE_RES_ERROR_HEAD:
+ case MISCREG_QUEUE_RES_ERROR_TAIL:
+ case MISCREG_QUEUE_NRES_ERROR_HEAD:
+ case MISCREG_QUEUE_NRES_ERROR_TAIL:
+ case MISCREG_SOFTINT:
+ case MISCREG_TICK_CMPR:
+ case MISCREG_STICK_CMPR:
+ case MISCREG_PIL:
+ case MISCREG_HPSTATE:
+ case MISCREG_HINTP:
+ case MISCREG_HTSTATE:
+ case MISCREG_STRAND_STS_REG:
+ case MISCREG_HSTICK_CMPR:
+ return readReg(miscReg) ;
+
+ case MISCREG_HTBA:
+ return readReg(miscReg) & ULL(~0x7FFF);
+ case MISCREG_HVER:
+ return NWindows | MaxTL << 8 | MaxGL << 16;
+
+ default:
+ panic("Invalid read to FS misc register\n");
}
}
/*
ret_data64=0x0000000000000001, update_data=True,
warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+ fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
+ ret_data64=0x0000000000000000, update_data=True,
+ warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
+ fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
+ ret_data64=0x0000000000000000, update_data=True,
+ warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
+ fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
+ ret_data64=0x0000000000000000, update_data=True,
+ warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
+ fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
+ ret_data64=0x0000000000000000, update_data=True,
+ warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000,
warn_access="Accessing SSI -- Unimplemented!")
self.fake_l2_2.pio = bus.port
self.fake_l2_3.pio = bus.port
self.fake_l2_4.pio = bus.port
+ self.fake_l2esr_1.pio = bus.port
+ self.fake_l2esr_2.pio = bus.port
+ self.fake_l2esr_3.pio = bus.port
+ self.fake_l2esr_4.pio = bus.port
self.fake_ssi.pio = bus.port
self.puart0.pio = bus.port
self.hvuart.pio = bus.port
projects / gem5.git / commitdiff