[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Sun, 24 May 2020 20:41:42 +0000 (20:41 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sun, 24 May 2020 20:41:43 +0000 (21:41 +0100)
4e/bc71517c7b8d6d1f02b440c498e0a1a264f689 [new file with mode: 0644]

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+Date: Sun, 24 May 2020 20:41:42 +0000
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+X-Bugzilla-Severity: enhancement
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+Message-ID: <bug-336-13-NO8Sl7dRd0@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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